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50 MHz to 3.5 GHz, 45 dB RF Detector AD8312
FEATURES
Complete RF detector function Typical range: -45 dBm to 0 dBm, re 50 Frequency response from 50 MHz to 3.5 GHz Temperature-stable linear-in-dB response Accurate to 3.5 GHz Rapid response: 85/120 ns (rise/fall) Low power: 12 mW at 2.7 V
Its high sensitivity allows measurement at low power levels, thus reducing the amount of power that needs to be coupled to the detector. It is essentially a voltage-responding device, with a typical signal range of 1.25 mV to 224 mV rms or -45 dBm to 0 dBm, re 50 . For convenience, the signal is internally ac-coupled, using a 5 pF capacitor to a load of 3 k in shunt with 1.3 pF. This highpass coupling, with a corner at approximately 16 MHz, determines the lowest operating frequency. Therefore, the source may be dc grounded. The AD8312 output, VOUT, increases from close to ground to about 1.2 V because the input signal level increases from 1.25 mV to 224 mV. A capacitor may be connected between the VOUT and CFLT pins when it is desirable to increase the time interval over which averaging of the input waveform occurs. The AD8312 is available in a 6-ball, 1.0 mm x 1.5 mm, waferlevel chip scale package and consumes 4.2 mA from a 2.7 V to 5.5 V supply.
APPLICATIONS
Cellular handsets (GSM, CDMA, WCDMA) RSSI and TSSI for wireless terminal devices Transmitter power measurement
GENERAL DESCRIPTION
The AD8312 is a complete, low cost subsystem for the measurement of RF signals in the frequency range of 50 MHz to 3.5 GHz. It has a typical dynamic range of 45 dB and is intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than possible using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of -40C to +85C.
FUNCTIONAL BLOCK DIAGRAM
CFLT - + DET RFIN 10dB 10dB 10dB 10dB DET DET DET DET BAND-GAP REFERENCE VPOS I-V VOUT V-I VSET
COMM
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05260-001
OFFSET COMPENSATION
AD8312
AD8312 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 General Description ....................................................................... 12 Applications..................................................................................... 13 Basic Connections ...................................................................... 13 Transfer Function in Terms of Slope and Intercept ............... 13 Filter Capacitor ....................................................................... 14 Input Coupling Options ........................................................ 14 Increasing the Logarithmic Slope ........................................ 15 Effect of Waveform Type on Intercept ................................ 15 Temperature Drift .................................................................. 16 Operation Above 2.5 GHz .................................................... 16 Device Handling..................................................................... 16 Evaluation Board.................................................................... 16 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
4/05--Revision 0: Initial Version
Rev. 0| Page 2 of 20
AD8312 SPECIFICATIONS
VS = 3 V, CFLT = open, TA = 25C, light condition = 600 LUX, 52.3 termination resistor at RFIN, unless otherwise noted. Table 1.
Parameter SIGNAL INPUT INTERFACE Specified Frequency Range Input Voltage Range Equivalent Power Range DC Resistance to COMM MEASUREMENT MODE f = 50 MHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Conditions RFIN (Pin 6) Internally ac-coupled 52.3 external termination VOUT (Pin 2) shorted to VSET (Pin 3), sinusoidal input signal 3050 || 1.4 50 42 3 -47 20.25 -51.5 0.841 0.232 0.0010 0.0073 2900 || 1.3 48 40 2 -46 21.0 -50.5 0.850 0.222 0.0002 0.0060 890 || 1.15 49 42 1 -48.0 20.25 -51.9 0.847 0.237 0.0019 0.0010 || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C Min 0.05 1.25 -45 100 Typ Max 3.5 224 0 Unit GHz mV rms dBm k
TA = 25C -40C < TA < +85C 1 dB error 1 dB error
PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C
f =100 MHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
TA = 25C -40C < TA < +85C 1 dB error 1 dB error 19.0 -56.0 PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C
23.0 -47.0
f = 900 MHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
TA = 25C -40C < TA < +85C 1 dB error 1 dB error
PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA 85C -40C TA +25C
Rev. 0| Page 3 of 20
AD8312
Parameter f = 1.9 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Conditions Min Typ 450 || 1.13 48 40 1 -47 19.47 -52.4 0.826 0.240 0.004 0.005 430 || 1.09 48 40 1 -47 19.1 -52.1 0.803 0.230 -0.0023 0.0055 400 || 1.03 49 40 1 -48 18.6 -51.2 0.762 0.204 0.005 -0.0126 0.02 2.0 VS - 1 2/0.1 100 1.4 120 85 13 75 0.2 Max Unit || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C V V V mA V V/Hz ns ns k A
TA = 25C -40C < TA < +85C 1 dB error 1 dB error
PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA 85C -40C TA +25C
f = 2.2 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
TA = 25C -40C < TA < +85C 1 dB error 1 dB error
PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA 85C -40C TA +25C
f = 2.5 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
TA = 25C -40C < TA < +85C 1 dB error 1 dB error
OUTPUT INTERFACE Minimum Output Voltage Maximum Output Voltage1 General Limit Available Output Current Residual RF (at 2f) Output Noise Fall Time Rise Time VSET INTERFACE Input Resistance Bias Current Source
PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA 85C -40C TA +25C VOUT (Pin 2) No signal at RFIN, RL 10 k RL 10 k 2.7 V VS 5.5 V Sourcing/sinking f = 0.1 GHz (worst condition) RF input = 2.2 GHz, -10 dBm, fNOISE = 100 kHz, CFLT open Input level = off to 0 dBm, 90% to 10% Input level = 0 dBm to off, 10% to 90% VSET (Pin 3) RFIN = -10 dBm; VSET = 1.2 V
1.8 VS - 1.2
Rev. 0| Page 4 of 20
AD8312
Parameter POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature
1
Conditions VPOS (Pin 1)
Min 2.7 2.8
Typ 3.0 4.2 4.3
Max 5.5 5.7
Unit V mA mA
-40C TA +85C
Increased output is possible when using an attenuator between VOUT and VSET to raise the slope.
Rev. 0| Page 5 of 20
AD8312 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VPOS VOUT, VSET Input Voltage Equivalent Power Internal Power Dissipation JA (WLCSP) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Value 5.5 V 0 V, VPOS 1.6 V rms 17 dBm 200 mW 200C/W 125C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0| Page 6 of 20
AD8312 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8312
VPOS
VOUT
VSET
1
2
3
6
5
4
RFIN
COMM
CFLT
05260-002
TOP VIEW (Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Ball No. 1 2 3 Mnemonic VPOS VOUT VSET Description Positive Supply Voltage (VS), 2.7 V to 5.5 V. Logarithmic Output. Output voltage increases with increasing input amplitude. Setpoint Input. Connect VSET to VOUT for measurement-mode operation. The nominal logarithmic slope of 20 mV/dB can be increased to an arbitrarily high value by attenuating the signal between VOUT and VSET (see the Increasing the Logarithmic Slope section). Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between CFLT and VOUT. Device Common (Ground). RF Input.
4 5 6
CFLT COMM RFIN
Rev. 0| Page 7 of 20
AD8312 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3 V; TA = 25C; CFLT = open; light condition = 600 LUX, 52.3 termination; unless otherwise noted. Colors: +25C = Black, -40C = Blue, +85C = Red.
1.25 +85C +25C -40C 1.00 2.5 2.0 1.5 1.0
1.25 +85C +25C -40C 1.00
2.5 2.0 1.5 1.0
VOUT (V)
VOUT (V)
0.75
0.5 0
0.75
0.5 0
0.50
-0.5 -1.0
0.50
-0.5 -1.0
0.25
-1.5
05260-003
0.25
-1.5 -2.0
05260-006 05260-008
-2.0 0 -60 -2.5 10
-50
-40
-30 -20 PIN (dBm)
-10
0
0 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
-2.5 10
Figure 3. VOUT and Log Conformance vs. Input Amplitude at 50 MHz; Typical Device at -40C, +25C, and +85C
1.25 +85C +25C -40C 1.00 2.5 2.0 1.5 1.0
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz; Typical Device at -40C, +25C, and +85C
1.25 +85C +25C -40C 1.00 2.5 2.0 1.5 1.0
ERROR (dB)
VOUT (V)
0 0.50 -0.5 -1.0 0.25 -1.5
VOUT (V)
0.75
0.5
0.75
0.5 0
0.50
-0.5 -1.0
0.25
05260-004
-1.5 -2.0
05260-007
-2.0 0 -60 -2.5 10
-50
-40
-30 -20 PIN (dBm)
-10
0
0 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
-2.5 10
Figure 4. VOUT and Log Conformance vs. Input Amplitude at 100 MHz; Typical Device at -40C, +25C, and +85C
1.25 +85C +25C -40C 1.00 2.5 2.0 1.5 1.0
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz; Typical Device at -40C, +25C, and +85C
1.25 +85C +25C -40C 1.00 2.5 2.0 1.5 1.0
ERROR (dB)
VOUT (V)
VOUT (V)
0.75
0.5 0
0.75
0.5 0
0.50
-0.5 -1.0
0.50
-0.5 -1.0
0.25
-1.5
05260-005
0.25
-1.5 -2.0
-2.0 0 -60 -2.5 10
-50
-40
-30 -20 PIN (dBm)
-10
0
0 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
-2.5 10
Figure 5. VOUT and Log Conformance vs. Input Amplitude at 900 MHz; Typical Device at -40C, +25C, and +85C
Rev. 0| Page 8 of 20
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz; Typical Device at -40C, +25C, and +85C
ERROR (dB)
ERROR (dB)
ERROR (dB)
ERROR (dB)
AD8312
2.5 2.0 1.5 1.0 +85C +25C -40C 2.5 2.0 1.5 1.0 +85C +25C -40C
ERROR (dB)
0.5 0 -0.5 -1.0 -1.5
05260-009
ERROR (dB)
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -60
05260-012
-2.0 -2.5 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
10
-50
-40
-30 -20 PIN (dBm)
-10
0
10
Figure 9. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 50 MHz for 80 Devices
2.5 2.0 1.5 1.0 +85C +25C -40C
Figure 12. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 1.9 GHz for 80 Devices
2.5 2.0 1.5 1.0 +85C +25C -40C
ERROR (dB)
ERROR (dB)
0.5 0 -0.5 -1.0 -1.5
05260-010
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -60
05260-013
-2.0 -2.5 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
10
-50
-40
-30 -20 PIN (dBm)
-10
0
10
Figure 10. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 100 MHz for 80 Devices
2.5 2.0 1.5 1.0 +85C +25C -40C
Figure 13. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 2.2 GHz for 80 Devices
2.5 2.0 1.5 1.0 +85C +25C -40C
ERROR (dB)
ERROR (dB)
0.5 0 -0.5 -1.0 -1.5
05260-011
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -60
05260-014
-2.0 -2.5 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
10
-50
-40
-30 -20 PIN (dBm)
-10
0
10
Figure 11. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 900 MHz for 80 Devices
Figure 14. Distribution of Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 2.5 GHz for 80 Devices
Rev. 0| Page 9 of 20
AD8312
100ns/HORIZ DIV
RISE TIME 85ns 500mV/ VERT DIV
FALL TIME 120ns VOUT 500mV/VERT DIV
VOUT PULSED RF 0.1GHz, 0dBm
05260-015
RF INPUT
VPOS
2V/VERT DIV 1s/HORIZ DIV
05260-018
200mV/VERT DIV
Figure 15. VOUT Response Time, RF Off to 0 dBm
Figure 18. Power-On and Power-Off Response
TRIG HP8116A OUT PULSE GENERATOR PULSE OUT 49.9
ROHDE & SCHWARZ SMT06 GENERATOR PULSE MODULATION RF OUT +3dB
TRIG OUT
10MHz HP8648B REF OUTPUT SIGNAL GENERATOR 20dBm RF OUT
EXT TRIG
-3dB RF SPLITTER -3dB
6
AD811
732
AD8312
3V 0.1F
2 3 1
VPOS VOUT VSET
RFIN COMM
52.3
5
1
AD8312
VPOS VOUT VSET RFIN
6
CFLT 4 NC CH1
CH3*
TRIG
2
05260-016
COMM 5 CFLT 4 NC
52.3
NC = NO CONNECT
TEKTRONIX TDS51504 SCOPE *50 TERMINATION
3
TRIG
05260-019
05260-020
NC = NO CONNECT
TEKTRONIX P6204 FET PROBE
TEKTRONIX TDS784C SCOPE
Figure 16. Test Setup for Pulse Response
+j1 +j0.5 +j2
Figure 19. Test Setup for Power-On and Power-Off Response
10k
NOISE SPECTRAL DENSITY (nV/ Hz)
+j0.2
1k
100
0
0.2
0.5
1
2
0.1GHz
10
-j0.2 3.5GHz 2.2GHz
0.9GHz 1.9GHz
0dBm -10dBm -20dBm -40dBm -60dBm RF OFF 1 3 10 30 100 300 FREQUENCY (kHz) 1k 3k 10k
1
-j0.5 2.5GHz -j1 -j2
05260-017
Figure 20. Noise Spectral Density of Output; CFLT = Open Figure 17. Input Impedance vs. Frequency; No Termination Resistor on RFIN
Rev. 0| Page 10 of 20
AD8312
Table 4. Typical Specifications at Selected Frequencies at 25C (Mean and )
1 dB Dynamic Range1 (dBm) Frequency (GHz) 0.05 0.1 0.9 1.9 2.2 2.5 3.0 3.5
1
Slope (mV/dB) 0.3 0.2 0.3 0.3 0.4 0.6 0.7 0.7
Intercept (dBm) 0.4 0.4 0.4 0.6 0.85 1.2 2.5 2.5
+3.0 +2.0 +0.2 +1.5 +1.5 +2.0 -4 -1
High Point 0.12 0.1 0.1 0.12 0.2 0.3 0.3 0.3
-48.0 -46.0 -49.0 -48.8 -48.5 -47.7 -46 -39
Low Point 0.13 0.1 0.2 0.3 0.4 0.5 0.4 0.3
20.25 21.0 20.25 19.47 19.1 18.6 17.5 17.1
-51.5 -50.5 -51.9 -52.4 -52.1 -51.2 -46.9 -42.6
Refer to Figure 23.
Rev. 0| Page 11 of 20
AD8312 GENERAL DESCRIPTION
The AD8312 is a logarithmic amplifier (log amp) similar in design to the AD8313; further details about the structure and function may be found in the AD8313 data sheet and the data sheets of other log amplifiers produced by ADI. Figure 21 shows the main features of the AD8312 in block schematic form. The AD8312 combines two key functions needed for the measurement of signal level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals in a chain of four amplifier/limiter cells, each having a small-signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each amplifier stage is a full-wave rectifier, essentially a square-law detector cell, which converts the RF signal voltages to a fluctuating current with an average value that increases with signal level. A further passive detector stage is added ahead of the first stage. Therefore, there are five detectors, each separated by 10 dB, spanning some 50 dB of dynamic range. The overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error, can be judged by reference to Figure 3 through Figure 8, which show that errors across the central 40 dB are moderate. These figures show how the conformance to an ideal logarithmic function varies with temperature and frequency. The output of these detector cells is in the form of a differential current, making their summation a simple matter. It can easily be shown that such summation closely approximates a logarithmic function. This result is then converted to a voltage at the VOUT pin through a high gain stage. In measurement modes, this output is connected back to a voltage-to-current (V-to-I) stage, in such a manner that VOUT is a logarithmic measure of the RF input voltage with a slope and intercept controlled by the design. For a fixed termination resistance at the input of the AD8312, a given voltage corresponds to a certain power level. The external termination added before the AD8312 determines the effective power scaling. This often takes the form of a simple resistor (52.3 provides a net 50 input), but more elaborate matching networks may be used. This impedance determines the logarithmic intercept, the input power for which the output would cross the baseline (VOUT = 0) if the function were continuous for all values of input. Since this is never the case for a practical log amp, the intercept refers to the value obtained by the minimum-error, straight-line fit to the actual graph of VOUT vs. input power. The quoted values assume a sinusoidal (CW) signal. Where there is complex modulation, as in CDMA, the calibration of the power response needs to be adjusted accordingly. Where a true power (waveformindependent) response is needed, the use of an rms-responding detector, such as the AD8361, should be considered. However, in terms of the logarithmic slope, the amount by which the output VOUT changes for each decibel of input change (voltage or power), is, in principle, independent of waveform or termination impedance. In practice, it usually falls off at higher frequencies because of the declining gain of the amplifier stages and other effects in the detector cells. For the AD8312, the slope at low frequencies is nominally 21.0 mV/dB, falling almost linearly with frequency to about 18.6 mV/dB at 2.5 GHz. These values are sensibly independent of temperature and almost totally unaffected by supply voltages of 2.7 V to 5.5 V.
CFLT - + DET RFIN 10dB 10dB 10dB 10dB DET DET DET DET
V-I
VSET
I-V
VOUT
BAND-GAP REFERENCE
VPOS
COMM
Figure 21. Block Schematic
Rev. 0| Page 12 of 20
05260-021
OFFSET COMPENSATION
AD8312
AD8312 APPLICATIONS
BASIC CONNECTIONS
Figure 22 shows the basic connections for measurement mode. A supply voltage of 2.7 V to 5.5 V is required. The supply to the VPOS pin should be decoupled with a low inductance 0.1 F surface-mount ceramic capacitor. A series resistor of about 10 may be added; this resistor slightly reduces the supply voltage to the AD8312 (maximum current into the VPOS pin is approximately 5.7 mA). Its use should be avoided in applications where the power supply voltage is very low (that is, 2.7 V). A series inductor provides similar power supply filtering with minimal drop in supply voltage.
0.1F 52.3
1.2 VS= 2.7V RT = 52.3 1.0 1dB DYNAMIC RANGE 0.8 1 2 3
0.6
0
0.4
-1
0.2
AD8312
VS VOUT OPTIONAL (SEE TEXT)
2 1
0 -60
INTERCEPT -50 -40 -30 -20 PIN (dBm) -10 0
-3 10
VPOS VOUT VSET CF
RFIN
6
INPUT
COMM 5 CFLT
4
Figure 23. VOUT and Log Conformance Error vs. Input Level vs. Input Level at 900 MHz
3
TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT
The transfer function of the AD8312 is characterized in terms of its slope and intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8312, the slope is nominally 20 mV/dB. Therefore, a 10 dB change at the input results in a change at the output of approximately 200 mV. Figure 23 shows the range over which the device maintains its constant slope. The dynamic range can be defined as the range over which the error remains within a certain band, usually 1 dB or 3 dB. In Figure 23, for example, the 1 dB dynamic range is approximately 51 dB (from -49 dBm to +2 dBm). The intercept is the point at which the extrapolated linear response would intersect the horizontal axis (see Figure 23). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range by
VOUT = VSLOPE x (PIN - PO )
05260-022
OPTIONAL (SEE TEXT)
Figure 22. Basic Connections for Operation in Measurement Mode
The AD8312 has an internal input coupling capacitor. This eliminates the need for external ac coupling. In this example, a broadband input match is achieved by connecting a 52.3 resistor between RFIN and ground. This resistance combines with the internal input impedance of approximately 3 k to give an overall broadband input resistance of 50 . Several other coupling methods are possible; these are described in the Input Coupling Options section. The measurement mode is selected by connecting VSET to VOUT, which establishes a feedback path and sets the logarithmic slope to its nominal value. The peak voltage range of the measurement extends from -49 dBm to 0 dBm at 0.9 GHz and is only slightly less at higher frequencies up to 2.5 GHz. At a slope of 21.0 mV/dB, this would amount to an output span of 1.029 V. Figure 23 shows the transfer function for VOUT at a supply voltage of 2.7 V and an input frequency of 900 MHz. The load resistance on VOUT should not be lower than 4 k so that the full-scale output can be generated with the limited available current of 1 mA maximum. Figure 23 shows the logarithmic conformance under the same conditions.
where: VOUT is the demodulated and filtered RSSI output. VSLOPE is the logarithmic slope, expressed in V/dB. PIN is the input signal, expressed in decibels relative to some reference level (dBm in this case). PO is the logarithmic intercept, expressed in decibels relative to the same reference level. For example, at an input level of -27 dBm, the output voltage is
VOUT = 0.020 V/dB x - 27 dBm - (- 50 dBm ) = 0.46 V
[
]
Rev. 0| Page 13 of 20
05260-023
3dB DYNAMIC RANGE
-2
ERROR (dB)
VOUT (V)
AD8312
Filter Capacitor
The video bandwidth of VOUT is approximately 3.5 MHz. In CW applications where the input frequency is much higher than this, no further filtering of the demodulated signal is required. Where there is a low frequency modulation of the carrier amplitude, however, the low-pass corner must be reduced by the addition of an external filter capacitor, CF (see Figure 22). The video bandwidth is related to CF by
1 Video Bandwidth = 2 x 13 k x (3.5 pF + C F )
The impedance matching characteristics of a reactive matching network provide voltage gain ahead of the AD8312, which increases device sensitivity (see Table 5). The voltage gain is calculated by
Voltage GaindB = 20 log 10 R2 R1
where: R2 is the input impedance of the AD8312. R1 is the source impedance to which the AD8312 is being matched. Note that this gain is only achieved for a perfect match. Component tolerances and the use of standard values tend to reduce gain.
50 SOURCE 50 RSHUNT 52.3 RFIN CC CIN VBIAS RIN
05260-024
Input Coupling Options
The internal 5 pF coupling capacitor of the AD8312, along with the low frequency input impedance of 3 k, gives a high-pass input corner frequency of approximately 16 MHz. This sets the minimum operating frequency. Figure 24 to Figure 26 show three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at RFIN (see Figure 24). This 52.3 resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the AD8312 (2.9 k || 1.3 pF) to give a broadband input impedance of 50 . While the input resistance and capacitance (RIN and CIN) varies by approximately 20% from device to device, the dominance of the external shunt resistor means that the variation in the overall input impedance is close to the tolerance of the external resistor. At frequencies above 2 GHz, the input impedance drops below 450 ; therefore, it is appropriate to use a larger shunt resistor value. This value is calculated by plotting the input impedance (resistance and capacitance) on a Smith Chart and by choosing the best shunt resistor value to bring the input impedance closest to the center of the chart (see Figure 17). At 2.5 GHz, a shunt resistor of 57.6 is recommended. A reactive match can also be implemented as shown in Figure 25. This is not recommended at low frequencies because device tolerances dramatically vary the quality of the match due to the large input resistance. For low frequencies, Figure 24 or Figure 26 is recommended. In Figure 25, the matching components are drawn as general reactances. Depending on the frequency, the input impedance at that frequency and the availability of standard value components, either a capacitor or an inductor, is used. As in the previous case, the input impedance at a particular frequency is plotted on a Smith Chart and matching components are chosen (Shunt or Series L, or Shunt or Series C) to move the impedance to the center of the chart. Matching components for specific frequencies can be calculated using the Smith Chart (see Figure 17). Table 5 outlines the input impedances for some commonly used frequencies.
AD8312
Figure 24. Broadband Resistive Method for Input Coupling
50 SOURCE 50 X1 X2 RFIN CC
AD8312
CIN VBIAS
RIN
05260-025
Figure 25. Narrow-Band Reactive Method for Input Coupling
AD8312
RFIN STRIPLINE RATTN CC CIN VBIAS RIN
05260-026
Figure 26. Series Attenuation Method for Input Coupling
Figure 26 shows a third method for coupling the input signal into the AD8312, which is applicable in applications where the input signal is larger than the input range of the log amp. A series resistor, connected to the RF source, combines with the input impedance of the AD8312 to resistively divide the input signal being applied to the input. This has the advantage of very little power being tapped off in RF power transmission applications.
Rev. 0| Page 14 of 20
AD8312
Table 5. Input Impedance for Select Frequency
Frequency (GHz) 0.05 0.1 0.9 1.9 2.2 2.5 3.0 3.5 Real 0.967 0.962 0.728 0.322 0.230 0.165 0.126 0.146 S11 Imaginary -0.043 -0.081 -0.535 -0.891 -0.832 -0.845 -0.849 -0.826 Impedance (Series) 1090 - j 1461 422.6 - j 1015 25.6 - j 148.5 11.5 - j 72.69 9.91 - j 64.74 9.16 - j 59.91 8.83 - j 57.21 10.5 - j 58.54
4.0 3.5 3.0 2.5
VOUT (V)
5.0V SUPPLY
2.0 3.0x 1.5 1.0 1.0x
05260-028
2.0x
2.7V SUPPLY
Increasing the Logarithmic Slope
The nominal logarithmic slope of 20 mV/dB can be increased to an arbitrarily high value by attenuating the signal between VOUT and VSET, as shown in Figure 27. The ratio R1/R2 is set by
0.5 0 -60
-50
-40
-30 -20 PIN (dBm)
-10
0
10
New Slope -1 R1/R2 = Original Slope In the example shown, two 2 k resistors combine to change the slope at 1900 MHz from approximately 20 mV/dB to 40 mV/dB. Note that R2 is in parallel with the input resistance of VSET, typically 13 k. Therefore, the exact R1/R2 ration may vary.
AD8312
VOUT R1 2k VSET R2 2k ~40mV/dB @ 1900MHz
Figure 28. VOUT vs. Input Level at Various Logarithmic Slopes
Effect of Waveform Type on Intercept
Although specified for input levels in dBm (dB relative to 1 mW), the AD8312 fundamentally responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power but differing crest factors, produce different results at the log amplifier's output. The effect of differing signal waveforms is to shift the effective value of the intercept upwards or downwards. Graphically, this looks like a vertical shift in the log amplifier's transfer function. The logarithmic slope, however, is not affected. For example, consider the case of the AD8312 being alternately fed by an unmodulated sine wave and by a 64 QAM signal of the same rms power. The AD8312's output voltage differs by the equivalent of 1.6 dB (31 mV) over the complete dynamic range of the device (with the output for a 64 QAM input being lower). Figure 29 shows the transfer function of the AD8312 when driven by both an unmodulated sine wave and several different signal waveforms. For precision operation, the AD8312 should be calibrated for each signal type that is driving it. To measure the rms power of a 64 QAM input, for example, the mV equivalent of the dB value (19.47 mV/dB x 1.6 dB) should be subtracted from the output voltage of the AD8312.
Figure 27. Increasing the Output Slope
The slope can be increased to higher levels, as shown in Figure 28. This, however, reduces the usable dynamic range of the device, depending on the supply voltage. Output loading should be considered when choosing resistor values for slope adjustment to ensure proper output swing. Note that the load resistance on VOUT should not be lower than 4 k in order that the full-scale output can be generated with the limited available current of 1 mA.
05260-027
Rev. 0| Page 15 of 20
AD8312
5 4 3 2
1.0 0.9 0.8 0.7 +85C +25C -40C 5 4 3 2 1 0 -1 -2 -3 -4 -5 -45 -35 -25 PIN (dBm) -15 -5 5
05260-031 05260-032
VOUT (V)
1 0 -1
CW
IS-95 REV
VOUT (V)
0.6 0.5 0.4 0.3
-2
0.2
-3 WCDMA 64-CH -4 -5 -60 64 QAM
05260-029
0.1 0 -55
-50
-40
-30 -20 INPUT (dBm)
-10
0
10
Figure 29. Shift in Transfer Function due to Several Different Signal Waveforms
Figure 31.Output Voltage and Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 3.0 GHz for 60 Devices
1.0 0.9 0.8 0.7 +85C +25C -40C 5 4 3 2 1 0 -1 -2 -3 -4 -5 -45 -35 -25 PIN (dBm) -15 -5 5
Temperature Drift
Figure 30 shows the log slope and error over temperature for a 0.9 GHz input signal. Error due to drift over temperature consistently remains within 0.5 dB and only begins to exceed this limit when the ambient temperature goes above 70C. For all frequencies using a reduced temperature range, higher measurement accuracy is achievable.
1.3 2.5 2.0 1.0 1.5 1.0
VOUT (V)
0.6 0.5 0.4 0.3 0.2 0.1 0 -55
VOUT (V)
0.8
0.5 0
ERROR (dB)
0.5 +85C +70C +25C 0C -10C -20C -40C -50 -40 -30 -20 PIN (dBm) -10 0
-0.5 -1.0 -1.5 -2.0 -2.5 10
Figure 32. Output Voltage and Error at -40C, +25C, and +85C After Ambient Normalization vs. Input Amplitude at 3.5 GHz for 30 Devices
Device Handling
The wafer-level chip scale package consists of solder bumps connected to the active side of the die. The part is lead-free with 95.5% tin, 4.0% silver, and 0.5% copper solder bump composition. The WLCSP package can be mounted on printed circuit boards using standard surface-mount assembly techniques; however, caution should be taken to avoid damaging the die. See the AN-617 application note for additional information. WLCSP devices are bumped die, and exposed die can be sensitive to light condition, which can influence specified limits.
05260-030
0.3
0 -60
Figure 30. Typical Drift at 900 GHz for Various Temperatures
Operation Above 2.5 GHz
The AD8312 works at high frequencies, but exhibits slightly higher output voltage temperature drift. Figure 31 and Figure 32 show the transfer functions and error distributions of a large population of devices at 3.0 GHz and 3.5 GHz over temperature. Due to the repeatability of the drift from part-topart, compensation can be applied to reduce the effects of temperature drift. In the case of the 3.5 GHz distribution, an intercept correction of 2.0 dB at 85C would improve the accuracy of the distribution to 2 dB over a +40 dB range.
Evaluation Board
Figure 33 shows the schematic of the AD8312 evaluation board. The layout and silkscreen of the component and circuit sides are shown in Figure 34 to Figure 37. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by a single 0.1 F capacitor. Table 6 details the various configuration options of the evaluation board.
Rev. 0| Page 16 of 20
ERROR (dB)
ERROR (dB)
AD8312
C2 0.1F R1 52.3
AD8312
VPOS R3 0 VOUT C4 (OPEN) R7 0 VSET R5 (OPEN) TO EDGE CONNECTOR R8 (OPEN) R6 (OPEN) R4 0
2 1
VPOS VOUT VSET
RFIN 6 COMM 5 CFLT 4
INPUT
3
TO EDGE CONNECTOR R2 (OPEN)
Figure 33. Evaluation Board Schematic
05260-036
05260-033
C3 (OPEN)
Figure 34. Silkscreen of Component Side (WLCSP)
Figure 36. Silkscreen of Circuit Side (WLCSP)
05260-034
Figure 35. Layout of Component Side (WLCSP)
Figure 37. Layout of Circuit Side (WLCSP)
Rev. 0| Page 17 of 20
05260-035
05260-037
AD8312
Table 6. Evaluation Board Configuration Options
Component VPOS, GND C2 R1 R2, R4 Function Supply and Ground Vector Pins. Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 F capacitor (C1). Input Interface. The 52.3 resistor in Position R1 combines with the AD8312's internal input impedance to give a broadband input impedance of around 50 . Slope Adjust. By installing resistors in R2 and R4, the nominal slope of 20 mV/dB can be changed. See the Increasing the Logarithmic Slope section for more details. Default Condition Not Applicable C2 = 0.1 F (Size 0603) R1 = 52.3 (Size 0603) R2 = Open (Size 0402) R4 = 0 (Size 0402) C3 = Open (Size 0603) R3 = 0 (Size 0603) R8 = C4 = Open (Size 0402) R7 = 0 (Size 0603) R5 = R6 = Open (Size 0402)
C3 R3, R8, C4
Filter Capacitor. The response time of VOUT can be modified by placing a capacitor between CFLT (Pin 4) and VOUT (Pin 2). Output Interface. R3, R8, and C4 can be used to check the response of VOUT to capacitive and resistive loading. R3/R8 can be used to attenuate VOUT.
R7 R5, R6
VSET Interface. R7 can be used to reduce capacitive loading from transmission lines. Alternate Interface. R5 and R6 allow for VOUT and VSET to be accessible from the edge connector, which is only used for characterization.
Rev. 0| Page 18 of 20
AD8312 OUTLINE DIMENSIONS
1.00 0.95 0.90 A1 BALL CORNER 1.50 1.45 1.40 0.380 0.355 0.330 0.675 0.595 0.515 SEATING PLANE
B A 1
0.345 0.295 0.245
1.00 BSC
2
0.50 BSC
3
TOP VIEW
(BUMP SIDE DOWN)
0.270 0.240 0.210
0.075 COPLANARITY
0.50 BSC BOTTOM VIEW
(BUMP SIDE UP)
Figure 38. 6-Ball Wafer-Level Chip Scale Package [WLCSP] (CB-6) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8312ACBZ-P71 AD8312ACBZ-P21 AD8312-EVAL
1
Temperature Range -40C to +85C -40C to +85C
Package Description 6-Ball WLCSP, 7" Pocket Tape and Reel 6-Ball WLCSP, 7" Pocket Tape and Reel Evaluation Board
Package Outline CB-6 CB-6
Branding Information Q00 Q00
Ordering Quantity 3000 250
Z = Pb-free part.
Rev. 0| Page 19 of 20
AD8312 NOTES
(c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05260-0-4/05(0)
Rev. 0| Page 20 of 20

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