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MC100E241 5V ECL 8-Bit Scannable Register
Description
The MC100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD and LOAD to be toggled with a single control line without the need for external gating. It also enables switching to scan mode with the single SHIFT control line. The eight inputs D0 - D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a set-up time before the positive-going edge of CLK; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. The 100 Series contains temperature compensation.
Features
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PLCC-28 FN SUFFIX CASE 776
* * * * * * * * * *
* * *
SHIFT overrides HOLD/LOAD Control 1000 ps Max. CLK to Q Asynchronous Master Reset Pin-Compatible with E141 PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 1 kV, Machine Model; > 75 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb-Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 529 devices Pb-Free Packages are Available*
MARKING DIAGRAM*
1 28
MC100E241FNG AWLYYWW
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 3
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Publication Order Number: MC100E241/D
MC100E241
SEL0 NC 25 24 D7 23 D6 22 D5 21 VCCO 20 Q7 19 18 17 16 Q6 Q5 VCC 1 VEE S-IN D0 D1
1
S-IN 1 D0 0 1 0 DQ R Q0
SEL1 CLK MR
26 27 28
1 0
DQ R
Q1 - Q6
2 3 4 5 D2
Pinout: 28-Lead PLCC (Top View)
15 14 13 12
NC VCCO Q4 Q3
D1 - D6
0 BITS 1-6
1 D7 HOLD/LOAD SHIFT CLK MR 0
1 0
DQ R
Q7
6 D3
7 D4
8 VCCO
9 Q0
10 Q1
11 Q2
* All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout Assignment
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN D0 - D7 S-IN SEL0 SEL1 CLK MR Q0 - Q7 VCC, VCCO VEE NC FUNCTION ECL Parallel Date Inputs ECL Serial Data Inputs ECL SHIFT Control ECL HOLD/LOAD Control ECL Clock ECL Master Reset ECL Data Outputs Positive Supply Negative Supply No Connect
Table 2. FUNCTION TABLE
MR 1 0 0 0 SEL0 X 1 0 0 SEL1 X X 1 0 Outputs LOW Shift Data Hold Data Load Data Function
X = Don't Care
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MC100E241
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 -8 6 -6 50 100 0 to +85 -65 to +150 63.5 43.5 22 to 26 265 265 Unit V V V V mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V, VEE = 0.0 V (Note 1)
0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 0.3 3975 3190 3835 3190 Min Typ 125 4050 3295 3975 3355 Max 150 4120 3380 4120 3525 150 0.5 0.25 3975 3190 3835 3190 Min 25C Typ 125 4050 3255 3975 3355 Max 150 4120 3380 4120 3525 150 0.5 0.2 3975 3190 3835 3190 Min 85C Typ 144 4050 3260 3975 3355 Max 173 4120 3380 4120 3525 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 5. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 3)
0C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Current Input LOW Current 0.5 0.3 -1025 -1810 -1165 -1810 Min Typ 125 -950 -1705 -1025 -1645 Max 150 -880 -1620 -880 -1475 150 0.5 0.25 -1025 -1810 -1165 -1810 Min 25C Typ 125 -950 -1745 -1025 -1645 Max 150 -880 -1620 -880 -1475 150 0.5 0.2 -1025 -1810 -1165 -1810 Min 85C Typ 144 -950 -1740 -1025 -1645 Max 173 -880 -1620 -880 -1475 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 4. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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MC100E241
Table 6. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = -5.0 V (Note 5)
0C Symbol fMAX fSHIFT tPLH tPHL ts Setup Time D SEL0 (SHIFT) SEL1 (HOLD/LOAD) S-IN th Hold Time D SEL0 (SHIFT) SEL1 (HOLD/LOAD) S-IN tRR tPW tSKEW tJITTER tr tf Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew (Note 6) Random Clock Jitter (RMS) Rise/Fall Times (20 - 80%) 300 525 800 300 525 800 300 525 800 400 60 <1 400 60 <1 400 60 <1 ps ps ps 200 100 50 300 900 -25 -200 -250 100 600 200 100 50 300 900 -25 -200 -250 100 600 200 100 50 300 900 -25 -200 -250 100 600 ps ps 175 350 400 125 25 200 250 -100 175 350 400 125 25 200 250 -100 175 350 400 125 25 200 250 -100 ps Characteristic Maximum Toggle Frequency Max. Shift Frequency Propagation Delay to Output CLK MR 625 600 750 725 975 975 625 600 750 725 975 975 625 600 750 725 975 975 ps 700 Min Typ 900 900 700 Max Min 25C Typ 900 900 700 Max Min 85C Typ 900 900 Max Unit GHz MHz ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. 100 Series: VEE can vary -0.46 V / +0.8 V. 6. Within-device skew is defined as identical transitions on similar paths through a device.
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MC100E241
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC100E241FN MC100E241FNG MC100E241FNR2 MC100E241FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100E241
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC100E241
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10E241/D

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