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ISL4089
Data Sheet June 28, 2006 FN6192.1
DC-Restored Video Amplifier
The ISL4089 is complete DC-restored monolithic video amplifier sub-system. It contains a high performance video amplifier and a nulling, sample-and-hold amplifier designed to establish a programmable DC output level. When the HOLD logic input "0" is applied the DC restore function is active. The sample-and-hold amplifier loop is closed and used to null the DC offset of the video amplifier. This can occur during sync, or, at any time that a black level is expected. When the HOLD input "1" is applied, the correcting voltage is stored on the video amplifier's input coupling capacitor. This condition must be true during active video. The restored DC voltage level can be adjusted using an external reference voltage applied to the VREF pin. The device operates from a single +5V supply and is ideal for +5V only systems when used with a sync separator, such as the EL1883. The ISL4089 is intended to directly replace the EL4089 only in certain applications. This direct replacement requires that the single positive supply is no higher than +5.5V and that no part of the clamped output goes below ground. The NC on pin 6 is not internally connected, so it can be connected to the -5V pin in existing EL4089 applications. The ISL4089 is specified for operation over -40C to +85C temperature range.
Features
* Complete video level DC-restoration system * 0.03% differential gain and 0.05 differential phase accuracy * 300MHz -3dB small signal bandwidth at AV = 1 * 150MHz -3dB small signal bandwidth at AV = 2 * 300V/s Slew Rate * 0.1dB flatness to 80MHz * +5V single supply operation * TTL/CMOS compatible hold signal * Pb-free plus anneal available (RoHS compliant)
Applications
* Input amplifier in video equipment * DC-restoration amplifier in video mixers
Related Documents
* AN1261: ISL4089EVAL1 User's Guide * AN1089: EL4089 and EL4390 DC-Restored Video Amplifier
Ordering Information
PART NUMBER PART MARKING 4089IBZ 4089IBZ TAPE & REEL PACKAGE 7" 8 Ld SO (Pb-free) 8 Ld SO (Pb-free) PKG. DWG. # MDP0027 MDP0027
Pinout
ISL4089 (8 Ld SOIC) TOP VIEW
ISL4089IBZ (See Note) ISL4089IBZ-T7 (See Note)
IN+
V+
IN+
VOUT
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VREF
+
N/C
-
HOLD
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL4089
Absolute Maximum Ratings (TA = 25C)
Voltage between V+ and GND . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Voltage between IN+, IN-, HOLD, VREF and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5;V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER AMPLIFIER SECTION (HOLD = 5V) Ib+ IbAVOL VOUT+ VOUTISC RESTORE SECTION VOS, Comp IOUT PSRR Ib VREF VH HOLD VL HOLD IIH, Hold IIL, Hold IS
V+ = +5V, Load = 1k; TA = +25C CONDITION MIN TYP MAX UNIT
DESCRIPTION
IN+ Input Bias Current IN- Input Bias Current Open Loop Gain High Output Level Low Output Level Short Circuit Current
VIN+ = 2.5V VIN- = 1.3V
-7 -30 60
20 -1
A A dB V
RL = 1k IL = 0mA
3.5 5 100
mV mA
Composite Input Offset Voltage Restoring Current Available Power Supply Rejection Ratio VREF Input Bias Current HOLD Logic Input Low HOLD Logic Input High HOLD Input Current @ Logic High HOLD Input Current @ Logic Low Supply Current
VREF = 0V to +2.5V
10 300
15
mV A dB
V+ = 5V to 6V VREF = +2.5V
70 -0.8
90 -0.5 -0.2 0.8
A V V
2.0 VHOLD = 5V VHOLD = 0V VHOLD = 0V -15 -5 17 20 30 5 23
A A mA
AC Electrical Specifications
PARAMETER AMPLIFIER SECTION SR tr, tf tpd -3dB BW
VS = +5V, VREF = 0VDC, RL = 150, RF and RG = 475; AV = 2, TA = +25C. CONDITION MIN TYP MAX UNITS
DESCRIPTION
Slew Rate; 2VP-P, 20% to 80% Output Rise and Fall Times Propagation Delay, IN+ to Output Small Signal; Unity Gain Large Signal; Unity Gain Small Signal; AV = +2 Large Signal; AV = +2 VOUT = 0.2Vp-p; 10% to 90% VOUT = 0.2V; 10% to 10% RF = 0; RG = inf.; CL = 0.6pF, VOUT = 0.2VP-P RF = 0; RG = inf.; CL = 0.6pF, VOUT = 2VP-P CL = 0.6pF, VOUT = 0.2VP-P CL = 0.6pF, VOUT = 2VP-P
300 3.2 0.3 300 95 150 85
V/s ns ns MHz MHz MHz MHz
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FN6192.1 June 28, 2006
ISL4089
AC Electrical Specifications
PARAMETER 0.1dB BW VS = +5V, VREF = 0VDC, RL = 150, RF and RG = 475; AV = 2, TA = +25C. (Continued) CONDITION RF = 0; RG = inf.; CL = 0.6pF VOUT = 0.2VP-P RF = 0; RG = inf.; CL = 0.6pF VOUT = 2VP-P 0.1dB Gain Flatness; AV = +2 CL = 0.6pF, VOUT = 0.2VP-P CL = 0.6pF, VOUT = 2VP-P dG dP RESTORE SECTION THE THD NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values Time to Enable Hold; 50% to 50% Time to Disable Hold; 50% to 50% HOLD input 0V to +5V HOLD input 5V to 0V 40 20 ns ns Differential Gain Error Differential Phase Error NTC-7, Restore on sync tip NTC-7, Restore on sync tip MIN TYP 70 60 80 50 0.03 0.05 MAX UNITS MHz MHz MHz MHz %
DESCRIPTION 0.1dB Gain Flatness; Unity Gain
Typical Performance Curves VS = +5V, RL = 150 to GND, CL = 0.6pF, TA = 25C, unless otherwise specified.
10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M 10M FREQUENCY (Hz) 100M 500M AV =4 RF = 475 RG = 158 VOUT = 0.2VP-P RL = 150 AV = 2 RF = RG = 475 AV = 1 RF = 0 10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M 10M FREQUENCY (Hz) 100M 500M AV = 4 RF = 475 RG = 158 AV = 2 RF = RG = 475 AV = 1 RF = 0 VOUT = 2VP-P RL = 150
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY for VARIOUS GAINS
10 8 NORMALIZED GAIN (dB) 6 4 2 0 -2 -4 -6 -8 -10 1M 10M FREQUENCY (Hz) 100M 500M AV = 2 CL = 0.6pF AV = 2 CL = 22pF VOUT = 2VP-P RL = 150 AV = 1 CL = 0.6pF to 22pF
FIGURE 2. LARGE SIGNAL GAIN vs FREQUENCY for VARIOUS GAINS
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1M 10M FREQUENCY (Hz) 100M 500M RF = RG = 301 VOUT = 0.2VP-P RL = 150 AV = 2 RF = RG = 475
RF = RG = 1k
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 4. SMALL SIGNAL GAIN vs RF, RG
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FN6192.1 June 28, 2006
ISL4089 Typical Performance Curves VS = +5V, RL = 150 to GND, CL = 0.6pF, TA = 25C, unless otherwise specified.
0.2 0.1 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M 100M 1G VOUT = 2VP-P NORMALIZED PHASE () AV = 2 RF = RG = 475 RL = 150 0.025 0.02 0.015 0.01 0.005 0 -0.005 -0.01 -0.015 -0.02 -0.025 0.01 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 NORMALIZED GAIN ERROR(%) VOUT = 0.6VP-P
(Continued)
VOUT = 0.2VP-P
VOUT = 0.3VP-P RL = 150 AV = 2 f = 3.58MHz RF = RG = 475 VOUT = 0.6VP-P
VOUT = 0.3VP-P 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (Hz)
VOUT DC (V)
FIGURE 5. 0.1dB GAIN FLATNESS
1.05 1.0 OUTPUT VOLTAGE (V) 0.95 0.9 0.85 0.8 0.75 0.7 0.65 TIME (20ns/DIV) VOUT = 0.2VP-P RF = RG = 475 OUTPUT VOLTAGE (V) CG = 0.5pF 3.0 2.5 2.0 1.5 1.0 0.5 0 4.0 3.5
FIGURE 6. DIFFERENTIAL GAIN - PHASE
VOUT = 2VP-P RF = RG = 475 CG = 0.5pF
TIME (20ns/DIV)
FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE; AV = 2
FIGURE 8. LARGE SIGNAL TRANSIENT RESPONSE; AV = 2
60 VOLTAGE NOISE (nV/Hz) 50 40 30 20 10 0 100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 9. INPUT NOISE vs FREQUENCY
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FN6192.1 June 28, 2006
ISL4089 Typical Performance Curves VS = +5V, RL = 150 to GND, CL = 0.6pF, TA = 25C, unless otherwise specified.
1 POWER DISSIPATION (W) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 909mW 0.8
J 8 /W SO 0C 1 =1
A
(Continued)
0.7 POWER DISSIPATION (W)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
0.6 625mW
J 8 /W SO 0C 6 =1
0.5 0.4 0.3 0.2 0.1 0
A
0.6
0.4
0.2
0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
ISL4089 (8 LD SOIC) 1 2 3 4 5 6 7 8
PIN NAME INN+ VREF HOLD GND NIC VOUT V+
EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 4 Circuit 1 Circuit 3 Circuit 4
V+
DESCRIPTION Video amplifier inverting input Video amplifier non-inverting input Restore amplifier VREF input Hold/restore logic input. Logic "0" selects the restore state; logic "1" selects the hold state Ground No internal connection Video amplifier output Positive power supply
V+ 21k
IN
LOGIC PIN
V-
GND
CIRCUIT 1
CIRCUIT 2
V+ V+ OUT GND GND
CAPACITIVELY COUPLED ESD CLAMP
CIRCUIT 3
CIRCUIT 4
5
FN6192.1 June 28, 2006
ISL4089 AC Test Circuits
RG VIN 50 + CL RF RS 118 86.6 TEST EQUIPMENT 50
DC-Restore Amplifier (Figure 13)
The DC-restore circuit contains a voltage reference amplifier and an analog switch function that closes the DC-restore loop under control of the HOLD logic input. The reference amplifier uses an internal 10mV offset voltage (V2) to enable the VREF input to sense down to the negative supply. The A2 amplifier output stage operates in a current-feed mode with a source/sink capability of 300A (Typ). A logic "0" at the HOLD input closes switch S1 which closes the DC-restore loop. The video input AC coupling capacitor, CX1, acts as a DC hold capacitor (through the 75 termination resistor RX1) to average the current-source output of amplifier A2. When the DC-restore loop has reached equilibrium, the DC voltage stored on CX1 will the value required to force the output voltages at A1 (VOUT) and A2 (VIN+) according to the following:
V OUT (DC) = V REF + 10mV (EQ. 2)
1. HOLD INPUT = 1
FIGURE 12A. VIDEO AMPLIFIER AC TEST CIRCUIT FOR 50
RG VIN 75
RF RS 75 CL TEST EQUIPMENT 75
+
1. HOLD INPUT = 1
FIGURE 12B. BACKTERMINATED TEST CIRCUIT FOR VIDEO CABLE APPLICATION.
and; the DC voltage at the non-inverting input of the video amplifier A1 is given in Equation 3:
V IN+ = V OUT (DC) + 1.2V (EQ. 3)
Figure 12A illustrates the AC test circuit used to operate the video amplifier into a 150 load while providing a 50 matched impedance. Figure 12B illustrates the test circuit for impedance matching to 75 test equipment.
Therefore, if VREF is set to 0V (GND); VOUT = 10mV, and the DC voltage stored on CX1 is ~1.2V. The CX1 capacitor value is chosen from the system requirements. A typical DC-restore application using the horizontal sync to drive the HOLD pin will result in a 62s hold time. The typical input bias current to the video amplifier is 1.2A, so for a 62s hold time, and a 0.01F capacitor, the output voltage drift is 7.5mV in one line. The restore amplifier can provide a typical current of 300A to charge capacitor CX1, so with a 1.2s sampling time, the output can be corrected by 36mV in each line. Using a smaller value of CX1 increases both the voltage that can be corrected, as well as the droop while being held. Likewise, using a larger value of CX1, reduces the correction and droop voltages. A sample of charging and droop rates are shown on the following table.
TABLE OF CHARGE STORAGE CAPACITOR VS DROOP CHARGING RATES (NOTE) CAP VALUE (if) 10 33 100 DROOP IN 62s (mV) 7.5 2.3 0.75 CHARGE IN 1.2s (mV) 36 11 3.6 CHARGE IN 4s (mV) 120 36 12
Application Information
General
The ISL4089 implements the video DC-restore function using a high performance gain adjustable video amplifier and a nulling, sample-hold amplifier to establish a user defined DC reference voltage at the video amplifier output. A detailed description of the DC-restore function implemented in the ISL4089 can be found in application note AN1089, EL4089 and EL4390 DC-Restored Video Amplifier. The ISL4089 performs the same function with the exception that it is designed for single supply operation.
Video Amplifier Operation (Figure 13)
The ISL4089 video amplifier (A1) is voltage-feed, high performance video amplifier designed for +5V operation. The output stage is capable of swinging to within 10mV of the negative rail. The differential input stage contains an internal voltage reference that positions the non-inverting input DC level (V1) to ~1.2V higher than the negative supply rail. This offset ensures that the amplifier input DC level is maintained within the common mode input voltage range. The amplifier non-inverting gain is given in Equation 1.
RF V OUT = ( V IN+ - 1.2V ) * 1 + ------- R G (EQ. 1)
NOTE: Basic formulae are: V (droop) = Ib+ * (Line time - Sample time)/Capacitor and V (charge) = IOUT * Sample time/Capacitor
6
FN6192.1 June 28, 2006
ISL4089
RG 475 RF 475
VINVIDEO INPUT
ISL4089
RXT A1 75 VOUT
VIDEO OUT
CX1
VIN+
1.2V + V1 S1
+
RX1 75
4k V+ +5V A2 + VREF + 10mV + V2 40pF VRef
0V to +4.5V
0.1F -
4.7F GND
Using the Reference Voltage Input (VREF)
Implementing DC-restore and amplifying composite video using a single +5V supply amplifier, requires attention to the performance of the amplifier over the minimum to maximum range of output voltage swing. The differential gain - phase plot in Figure 6 shows the amplifier accuracy operating from a single +5V supply, driving a 300mVP-P and a 600mVP-P signal into a 150 load. Over the output DC voltage range of 0.5V to 3.25V, differential gain and phase are less than 0.05% and 0.05 respectively and defines the optimum output voltage range of the ISL4089. Figure 6 also shows that as the signal level increases, a corresponding decrease in the output DC level (min/max voltage swing) can be expected. The VREF input enables the output DC voltage level to be optimally programmed within the min/max voltage range, according to Equation 2. The values in Figure 6 take into account the additional amplifier overhead (300mVP-P and 600mVP-P) needed by the video signal. Although the AC performance degrades below ~0.5V, the ISL4089 maintains DC accuracy down to 10mV.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 60mA. Adequate thermal heat sinking of the parts is also required.
-
HOLD TTL INPUT
GND
FIGURE 13. BASIC +5V APPLICATION CIRCUIT
Application Information
A typical single supply application circuit using the EL1883 sync separator to generate the DC-restore hold command, is shown in Figure 13. The ISL4089 is configured for a gain of 2, and 75 input and output terminations are used for cable driving; providing an end to end gain of 1. DC-restore is performed during sync tip using the composite sync output of the EL1883, which clamps the -300mV input sync tip level to 0VDC at the ISL4089 output (Figure 15 - lower trace). Clamping sync tip to 0VDC forces the black level, color burst and active video to the +300mV level at the 75 load in the terminal equipment, and to +600mV at the ISL4089 output pin. The +600mV DC offset is safely within the lower linear range of the ISL4089 output (Figure 6 - Differential Gain Phase) and the 2V maximum video amplitude at the output is safely within the upper limit. In applications where the sync tip level can't be guaranteed, positioning the active video within the linear range can be accomplished using the back porch clamp output of the EL1883 and supplying +1V to the VREF input. This has the effect of clamping the back porch to the +1V VREF level at the output while enabling the negative sync tip level to pass through to the output.
7
FN6192.1 June 28, 2006
ISL4089
R5 475 ohms
R4 475 ohms
1 INVIDEO INPUT C4 0.01uF
ISL4089
V+
+
+5V
C2, C3 0.1uF C1 4.7uF
2
R3 75 ohms
Ground Vout
R6 75 ohms
IN+ 3 Vref
Out
+
-
NC
4 Hold GND
Composite Sync Out Back-porch Clamp Out
1
C5 0.1uF
EL1883
8
Horizontal Sync Out
2
Vertical Sync Out
7
3
6
R7 681K C6 0.056 uF
4
5
FIGURE 14. APPLICATION CIRCUIT USING THE EL1883 SYNC SEPARATOR TO GENERATE DC-RESTORE HOLD CONTROL
COMPOSITE VIDEO INPUT
0VDC COMPOSITE SYNC INPUT 0VDC
DC-RESTORED VIDEO OUTPUT
0VDC
FIGURE 15. DC-RESTORE USING COMPOSITE SYNC AND VREF = 0VDC
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FN6192.1 June 28, 2006
ISL4089 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6192.1 June 28, 2006

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