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| a FEATURES Low Cost 3.3 V MxFETM for DOCSIS EURO DOCSIS DVB DAVIC Compliant Set-Top Box and Cable Modem Applications 232 MHz Quadrature Digital Upconverter 12-Bit Direct IF DAC (TxDAC+TM) Up to 65 MHz Carrier Frequency DDS Programmable Sampling Clock Rates 16 Upsampling Interpolation LPF Single-Tone Frequency Synthesis Analog Tx Output Level Adjust Direct Cable Amp Interface 12-Bit, 33 MSPS Direct IF ADC with Optional Video Clamping Input 10-Bit, 33 MSPS Direct IF ADC Dual 7-Bit, 16.5 MSPS Sampling I/Q ADC 12-Bit Sigma-Delta Auxiliary DAC APPLICATIONS Cable Modem and Satellite Systems Set-Top Boxes Power Line Modem PC Multimedia Digital Communications Data and Video Modems QAM, OFDM, FSK Modulation GENERAL DESCRIPTION TX DATA Mixed-Signal Front End Set-Top Box, Cable Modem AD9879 FUNCTIONAL BLOCK DIAGRAM I Tx Q 16 DDS SPORT 4 CONTROL REGISTERS PLL XM/N 2 RXIQ[3:0] 8 MUX ADC MUX 2 - _OUT CAPORT MCLK SINC-1 12 DAC TX RXI RXQ 10 ADC RX10 RXIF[11:0] MUX 12 ADC MUX CLAMP RX12 VIDEO AD9879 The AD9879 is a single-supply cable modem/set-top box mixed signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit DAC. The receive path contains a 12-bit ADC, a 10-bit ADC, and dual 7-Bit ADCs. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input. The transmit path interpolation filter provides an upsampling factor of 16x with an output signal bandwidth as high as 8.3 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required. The 12-bit and 10-bit IF ADCs can convert direct IF inputs up to 70 MHz and run at sample rates up to 33 MSPS. A video input with an adjustable signal clamping level, along with the 10-bit ADC, allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable sigma-delta DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners. The CA PORT provides an interface to the AD8321/AD8323 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers enabling host processor control via the MxFE SPORT. The AD9879 is available in a 100-lead MQFP package. It offers enhanced receive path undersampling performance and lower cost when compared with the pin compatible AD9873. The AD9879 is specified over the commercial (-40C to +85C) temperature range. MxFE and TxDAC are trademarks of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD9879-SPECIFICATIONS f(V Parameter OSCIN AND XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle to Cycle Jitter Tx DAC CHARACTERISTICS Resolution Maximum Sample Rate Full-Scale Output Current Gain Error (Using Internal Reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Crystal and OSCIN Multiplier Enabled at 16 Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Narrow-band SFDR ( 1 MHz Window): 5 MHz Analog Out, IOUT = 10 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass-Band Amplitude Ripple (f < fIQCLK/8) Pass-Band Amplitude Ripple (f < fIQCLK/4) Stop-Band Response (f > fIQCLK 3/4) Tx GAIN CONTROL Gain Step Size Gain Step Error Settling Time to 1% (Full-Scale Step) IQ ADC CHARACTERISTICS Resolution* Maximum Conversion Rate Pipeline Delay Offset Matching between I and Q ADCs Gain Matching between I and Q ADCs Analog Input Input Voltage Range* Input Capacitance Differential Input Resistance AC Performance (AIN = 0.5 dBFS, fIN = 5 MHz) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) AS MCLK = 3.3 V 5%, VDS = 3.3 V 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, = 54 MHz (M = 8), ADC Clock from OSCIN, RSET = 4.02 k , 75 DAC Load) Test Level II II III III N/A II II II III III III III III III II I I I II II II II III III III N/A III N/A Temp Full Full 25C 25C N/A Full Full Full 25C 25C 25C 25C 25C 25C Full Full Full Full Full Full Full Full 25C 25C 25C N/A Full N/A Min 3 35 Typ Max 29 65 Unit MHz % M||pF ps rms Bits MHz mA %FS %FS V LSB LSB pF dBc/Hz V dBc dBc dBc dB dB dB dB dB dB s Bits MHz ADC Cycles LSBs LSBs Vppd pF k Bits dB dB dB 50 100||3 6 12 232 4 -2.0 10 -1.0 1.0 1.23 2.5 8 5 -110 20 +2.0 -0.5 60.8 44.0 65.4 50 66.9 46.2 72.3 55 +1.5 0.1 0.5 -63 0.5 <0.05 1.8 6 14.5 3.5 4.0 2.0 1 2.0 4 5.25 5.8 36.5 -50 51 Full 25C 25C Full Full Full Full III III III I I I I *IQ ADC in Default Mode. ADC Clock Select Register 8, Bit 3 set to "0." -2- REV. 0 AD9879 Parameter 10-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Reference Voltage Error (REFT10-REFB10) -1 V AC Performance (AIN = -0.5 dBFS, fIN = 5 MHz) ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) AC Performance (AIN = -0.5 dBFS, fIN = 50 MHz) ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) 12-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Reference Voltage Error (REFT12-REFB12) -1 V AC Performance (AIN = -0.5 dBFS, fIN = 5 MHz) ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) AC Performance (AIN = -0.5 dBFS, fIN = 50 MHz) ADC Sample Clock Source = OSCIN Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Temp N/A Full N/A Full 25C 25C Full Test Level N/A II N/A III III II I Min Typ 10 29 4.5 2.0 2 4 4 58.3 9.4 58.6 65.7 59.9 9.65 60 -73 76 200 Max Unit Bits MHz ADC Cycles Vppd pF k mV Full Full Full Full Full I I I I I -62 dB Bits dB dB dB Full Full Full Full Full N/A Full N/A Full 25C 25C Full II II II II II N/A II N/A III III III I 57.7 9.29 57.8 +57 64 59.0 9.51 59.1 -75 78 12 dB Bits dB dB dB Bits MHz ADC Cycles Vppd pF k 200 mV 29 5.5 2 2 4 16 60.0 9.67 60.3 64.7 65.2 10.53 65.6 -76.6 79 Full Full Full Full Full I I I I I -58.7 dB Bits dB dB dB Full Full Full Full Full II II II II II 59.5 9.59 59.7 63.8 62.7 10.1 63.0 -75.5 79 -60.5 dB Bits dB dB dB REV. 0 -3- AD9879 Parameter CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (AOUT = 5 MHz) Isolation between Tx and IQ ADCs Isolation between Tx and 10-Bit ADC Isolation between Tx and 12-Bit ADC ADC-to-ADC (AIN = -0.5 dBFS, f = 5 MHz) Isolation between IF10 and IF12 ADCs Isolation between Q and I Inputs TIMING CHARACTERISTICS (10 pF Load) Minimum RESET Pulsewidth Low (tRL) Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (fMCLK) TxSYNC/TxIQ Setup Time (tSU) TxSYNC/TxIQ Hold Time (tHD) MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD) OSCOUT Rising or Falling Edge to RxSYNC/RxIQ/IF Valid Delay (tOD) OSCOUT Edge to MCLK Falling Edge (tEE) Serial Control Bus Maximum SCLK Frequency (fSCLK) Minimum Clock Pulsewidth High (tPWH) Minimum Clock Pulsewidth Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data/Chip-Select Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) CMOS LOGIC INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) Logic "1" Voltage Logic "0" Voltage POWER SUPPLY Supply Current, IS (Full Operation) Analog Supply Current, IAS Digital Supply Current, IDS Supply Current, IS Standby (PWRDN Pin Active) Full Power-Down (Register 2 = 0xF9) Power-Down Tx Path (Register 2 = 0x60) Power-Down Rx Paths (Register 2 = 0x19) Temp Test Level Min Typ Max Unit 25C 25C 25C 25C 25C N/A Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C 25C 25C 25C 25C 25C 25 C 25C 25C 25C 25C 25C 25C III III III III III N/A II II II II II II II II II II II II II II II II II II II II II II III III II III III III 5 2.8 >60 >80 >80 >85 >50 dB dB dB dB dB tMCLK Cycles ns MHz ns ns ns 4 66 3 3 0 TOSC/4 - 2.0 -1.0 1.0 TOSC/4 + 3.0 ns +1.0 ns 15 MHz ns ns ms ns ns ns V V A A pF V V mA mA mA mA mA mA mA 30 30 1 25 0 30 VDRVDD - 0.7 0.4 12 12 3 VDRVDD - 0.6 0.4 163 95 68 119 16 113 110 178 123 -4- REV. 0 AD9879 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Power Supply (VAVDD,VDVDD,VDRVDD) . . . . . . . . . . . . . . 3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Digital Inputs . . . . . . . . . . . . . . . . . -0.3 V to VDRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . . . . . . -0.3 V to VAVDD + 0.3 V Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300C *Absolute Maximum Ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. Devices are 100% production tested at +25C and guaranteed by design and characterization testing for commercial operating temperature range (-40C to +85C). Parameter is guaranteed by design and/or characterization testing. II. III. Parameter is a typical value only. N/A Test level definition is not applicable. ORDERING GUIDE Model AD9879BS Temperature Range -40C to +85C Package Description 100-Lead MQFP THERMAL CHARACTERISTICS Thermal Resistance 100-Lead MQFP JA = 40.5C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9879 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 -5- AD9879 PIN CONFIGURATION 100 VIDEO IN 89 IF10- 88 AGND 99 AGND 98 IF12+ 86 REFT10 85 REFB10 94 REFT12 93 REFB12 96 AGND 95 AVDD 91 AGND 90 IF10+ 84 AVDD 83 AGND 87 AVDD 92 AVDD 97 IF12- 82 Q+ DNC DRGND DRVDD IF(11) IF(10) IF(9) IF(8) IF(7) IF(6) 81 Q- 1 2 3 4 5 6 7 8 9 80 DNC 79 I+ 78 I- 77 DNC 76 DNC 75 DNC 74 AGNDIQ 73 AVDDIQ 72 DRVDD 71 REFCLK 70 DRGND 69 DGND 68 - _OUT 67 FLAG1 66 DVDD 65 CA_EN 64 CA_DATA 63 CA_CLK 62 DVDDOSC 61 OSCIN 60 XTAL 59 DGNDOSC 58 AGNDPLL 57 PLLFILT 56 AVDDPLL 55 DVDDPLL 54 DGNDPLL 53 AVDDTX 52 TX+ 51 TX- TXIQ(0) 32 DVDD 33 PROFILE 36 RESET 37 TXIQ(1) 31 DVDD 38 DGND 39 FSADJ 49 AGNDTX 50 DGND 34 SDO 44 DGNDTX 45 DVDDTX 46 PWRDN 47 REFIO 48 SCLK 41 DGND 40 SDIO 43 DNC 35 CS 42 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 RXIQ(3) 16 RXIQ(2) 17 RXIQ(1) 18 RXIQ(0) 19 RXSYNC 20 DRGND 21 DRVDD 22 MCLK 23 DVDD 24 DGND 25 TXSYNC 26 TXIQ(5) 27 TXIQ(4) 28 TXIQ(3) 29 TXIQ(2) 30 AD9879 TOP VIEW 100-LEAD MQFP -6- REV. 0 AD9879 PIN FUNCTION ASSIGNMENTS Pin No. Mnemonic Pin Function Do Not Connect. Pins are not bonded to die. Pin Driver Digital Ground Pin Driver Digital 3.3 V Supply 12-Bit ADC Digital Output Muxed I and Q ADCs Output Sync Output, IF, I and Q ADCs Master Clock Output Digital 3.3 V Supply Digital Ground Sync Input for Transmit Port Digital Input for Transmit Port Profile Selection Inputs Chip Reset Input (Active Low) SPORT Clock SPORT Chip Select SPORT Data I/O SPORT Data Output Tx Path Digital Ground Tx Path Digital 3.3 V Supply Power-Down Transmit Path TxDAC Decoupling (to AGND) DAC Output Adjust (External Res.) Tx Path Analog Ground Tx Path Complementary Outputs Tx Path Analog 3.3 V Supply PLL Digital Ground PLL Digital 3.3 V Supply Pin No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 71 73 74 78, 79 81, 82 Mnemonic AVDDPLL PLLFILT AGNDPLL DGNDOSC XTAL OSCIN DVDDOSC CA_CLK CA_DATA CA_EN DVDD FLAG1 - _OUT DGND REFCLK AVDDIQ AGNDIQ I-, I+ Q-, Q+ Pin Function PLL Analog 3.3 V Supply PLL Loop Filter Connection PLL Analog Ground Oscillator Digital Ground Crystal Oscillator Inv. Output Oscillator Clock Input Oscillator Digital 3.3 V Supply Serial Clock to Cable Driver Serial Data to Cable Driver Serial Enable to Cable Drive Sigma Delta Digital 3.3 V Supply Digital Output Flag 1 Sigma-Delta DAC Output Sigma-Delta Digital Ground Oscillator Clock Output 7-Bit ADCs Analog 3.3 V Supply 7-Bit ADCs Analog Ground Differential Input to I ADC Differential Input to Q ADC 12-Bit ADC Analog Ground 12-Bit ADC Analog 3.3 V Supply 10-Bit ADC Decoupling Node 10-Bit ADC Decoupling Node 12-Bit ADC Decoupling Node 12-Bit ADC Decoupling Node Video Clamp Input, 12-Bit ADC 1, 35, DNC 75-77, 80 2, 21, 70 3, 22, 72 4-15 16-19 20 23 25, 34, 39, 40 26 27-32 36 37 41 42 43 44 45 46 47 48 49 50 51, 52 53 54 55 DRGND DRVDD IF[11:0] RXIQ[3:0] RXSYNC MCLK DGND TXSYNC TXIQ[5:0] PROFILE RESET SCLK CS SDIO SDO DGNDTX DVDDTX PWRDN REFIO FSADJ AGNDTX TX-, TX+ AVDDTX DGNDPLL DVDDPLL 24, 33, 38 DVDD 83, 88, AGND 91, 96, 99 84, 87, 92, 95 85 86 89, 90 93 94 97, 98 100 AVDD REFB10 REFT10 REFB12 REFT12 VIDEO IN IF10-, IF10+ Differential Input to 10-Bit ADC IF12-, IF12+ Differential Input to IF ADC REV. 0 -7- AD9879 DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity Error (DNL, NO MISSING CODES) Aperture Delay An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating ranges. Integral Nonlinearity Error (INL) The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion. Aperture Uncertainty (Jitter) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Phase Noise Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. Input Reference Noise The rms output noise is measured using histogram techniques. The ADC output codes' standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can directly be referred to the input of the MxFE. Signal-To-Noise and Distortion (S/N+D, SINAD) Ratio Single-sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. Output Compliance Range SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula: N = (SINAD - 1.76)dB/6.02 it is possible to get a performance measurement expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Signal-To-Noise Ratio (SNR) The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Spurious-Free Dynamic Range (SFDR) The difference, in dB, between the rms amplitude of the DAC output signal (or the ADC input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted). Pipeline Delay (Latency) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) The number of clock cycles between conversion initiation and the associated output data being made available. Offset Error THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Power Supply Rejection First transition should occur for an analog value 1/2 LSB above -FS. Offset error is defined as the deviation of the actual transition from that point. Gain Error Power supply rejection specifies the converter's maximum fullscale change when the supplies are varied from nominal to minimum and maximum specified voltages. Channel-To-Channel Isolation (Crosstalk) The first code transition should occur at an analog value 1/2 LSB above full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channelto-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel. -8- REV. 0 AD9879 Table I. Register Map Address (hex) 00h Bit 7 SDIO Bidirectional Bit 6 SPI Bytes LSB First Bit 5 Reset Bit 4 Bit 3 Bit 2 OSCIN Multiplier M[4:0] MCLK/REFCLK Ratio R[5:0] Bit 1 Bit 0 Default (hex) Type 0x08 Read/Write 01h PLL Lock Detect 0x00 Read/Write 02h Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down 0x00 PLL DAC Tx Digital Tx IF12 ADC Reference IF10 ADC Reference IQ ADC IF12 ADC IQ and IF10 ADC Sigma-Delta Output Control Word [3:0] Flag 1 Flag 0 Enable 0x00 Read/Write 03h Read/Write 04h 05h 06h 07h Flag 0 0 0 Video Input Enable ADCs Clocked 0 Direct from OSCIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sigma-Delta Output Control Word [11:4] 0 0 0 0 0 0 0 0 0 0 0x00 0x00 0x00 0x00 Read/Write Read/Write Read-Only Read/Write Clamp Level for Video Input [6:0] 08h Rx Port Power-Down Enable 7-Bits 0 Fast Edge Rate RxSYNC and IQ ADC IQ ADC Clocks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Version [3:0] Send 12-Bit Send 10-Bit 0x80 ADC Data Only ADC Data Only Read/Write 09h 0Ah 0Bh 0Ch 0Dh 0 0 0 0 0 0 0x00 0x00 0x00 0x05 0x00 Read/Write Read/Write Read/Write Read/Write Read/Write Tx Frequency Tuning Word Tx Frequency Tuning Word Profile 1 LSBs [1:0] Profile 0 LSBs [1:0] DAC Fine Gain Control [3:0] Tx Path AD8322/ AD8327 Gain Control Mode Tx Path Bypass Sinc-1 Filter Tx Path Spectral Inversion Tx Path Transmit Single Tone 0Eh 0Fh 0 0 0 0 0 0 0x00 0x00 Read/Write Read/Write Tx Path 0 Select Profile 1 10h 11h 12h 13h 14h 15h 16h 17h Tx Path Frequency Tuning Word Profile 0 [9:2] Tx Path Frequency Tuning Word Profile 0 [17:10] Tx Path Frequency Tuning Word Profile 0 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Tx Path Frequency Tuning Word Profile 1 [9:2] Tx Path Frequency Tuning Word Profile 1 [17:10] Tx Path Frequency Tuning Word Profile 1 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0] Register bits denoted with "0" MUST be programmed with a "0" every time that register is written. REV. 0 -9- AD9879 REGISTER BIT DEFINITIONS Register 00 -- Initialization Bits 0 to 4: OSCIN Multiplier Bit 2: Power-Down IF10 ADC Active high powers down the IF10 ADC. Bit 3: Power-Down IF12 ADC Reference This register field is used to program the on-chip multiplier (PLL) that generates the chip's high frequency system clock fSYSCLK. The value of M will depend on the ADC clocking mode selected as shown in the table below. Table II. Active high powers down the 12-bit ADC reference. Bit 4: Power-Down IF12 ADC Active high powers down the IF12 ADC. Bit 5: Power-Down Digital TX ADC Clock Select 1, fOSCIN 0, fMCLK (PLL Derived) M 8 16 Active high powers down the digital transmit section of the chip, similar to the function of the PWRDN Pin. Bit 6: Power-Down DAC TX Active high powers down the DAC. Bit 7: Power-Down PLL Active high powers down the OSCIN multiplier. When using the AD9879 in systems where the Tx path and Rx path do not operate simultaneously, the value of M can be programmed from 1 to 31. The maximum fSYSCLK rate of 236 MHz must be observed, whatever value is chosen for M. When M is set to 1, the internal PLL is disabled and all internal clocks are derived directly from OSCIN. Bit 5: Reset Registers 03 and 04 -- Sigma-Delta and Flag Control Writing a 1 to this bit resets the registers to their default values and restarts the chip. The Reset bit always reads back 0. The bits in Register 0 are not affected by this software reset. However, a low level at the RESET pin would force all registers, including all bits in Register 0, to their default state. Bit 6: SPI Bytes LSB First The sigma-delta control word is 12 bits wide and split in MSB bits [11:4] and LSB bits [3:0]. Changes to the sigma-delta control words take effect immediately for every MSB or LSB register write. Sigma-delta output control words have a default value of "0." The control words are in straight binary format with 0x000 corresponding to the bottom of the scale and 0xFFF corresponding to the top of the scale. See Figure 6 for details. If the Flag 0 Enable (Register 3, Bit 0) is set high, the - _OUT pin will maintain a fixed logic level determined directly by the MSB of the sigma-delta control word. The FLAG1 pin assumes the logic level programmed into the FLAG1 bit (Register 3, Bit 1). Register 07 --VIDEO INPUT CONFIGURATION Bits 0-6: Clamp Level Control Value Active high indicates SPI serial port access of instruction byte and data registers is least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format. Bit 7: SDIO Bidirectional Active high configures the serial port as a three signal port with the SDIO pin used as a bidirectional input/output pin. Default low indicates the serial port uses four signals with SDIO configured as an input and SDO configured as an output. Register 01 -- Clock Configuration Bits 0 to 5: MCLK/REFCLK Ratio The 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. The actual ADC output will have a clamp level offset equal to 16 times the clamp level control value as shown: Clamp Level Offset = Clamp Level Control Value ( ) 16 The default value for the clamp level control value is 0x20. This results in an ADC output clamp level offset of 512 LSBs. The valid programming range for the clamp level control value is from 0x16 to 0x127. Register 08 -- ADC CLOCK CONFIGURATION Bit 0: Send 10-Bit ADC Data Only This bit field defines, R, the ratio between the auxiliary clock output, REFCLK and MCLK. R can be any integer number between 2 and 63. At default zero (R = 0), REFCLK provides a buffered version of the OSCIN clock signal. Bit 7: PLL Lock Detect When this bit is set low, the REFCLK pin functions in its default mode, and provides an output clock with frequency fMCLK/R as described above. If this bit is set to 1, the REFCLK pin is configured to indicate whether the PLL is locked to fOSCIN. In this mode, the REFCLK pin should be low-pass filtered with an RC filter of 1.0 kW and 0.1 mF. A high output on REFCLK indicates that the PLL has achieved lock with fOSCIN. Register 02 -- POWER-DOWN When this bit is set high, the device enters a Nonmultiplexed mode and only the data from the 10-bit ADC will be sent to the IF [11:0] digital output port. Bit 1: Send 12-Bit ADC Data Only When this bit is set high, the device enters a Nonmultiplexed mode and only data from the 12-bit ADC will be sent to the IF [11:0] digital output port. Bit 3: Enable 7-Bits, IQ ADC Sections of the chip that are not used can be powered down when the corresponding bits are set high. This register has a default value of 0x00; all sections active. Bit 0: Power-Down IQ ADC When this bit is active the IQ ADC is put into 7-bit mode. In this mode, the full-scale input range is 2 Vppd. When this bit is set inactive, the IQ ADC is put into 6-bit mode and the fullscale input voltage range is 1 Vppd. Bit 4: Power-Down RXSYNC and IQ ADC Clocks Active high powers down the IQ ADC. Bit 1: Power-Down IQ and IF10 ADC Reference Setting this bit to 1 powers down the IQ ADC's sampling clock and stops the RXSYNC output pin. It can be used for additional power saving on top of the power-down selections in Register 2. -10- REV. 0 Active high powers down the IQ and IF10 ADC reference. AD9879 Bit 5: Rx Port Fast Edge Rate Setting this bit to 1 increases the output drive strength of all digital output pins, except MCLK, REFCLK, - _OUT, and FLAG1. These pins always have high output drive capability. Bit 7: ADC Clocked Direct from OSCIN control select changes the interpretation of the bits in Registers 13 and 17. See Cable Driver Gain Control. Bit 5: Tx Path Select Profile 1 When set high, the input clock at OSCIN is used directly as the ADC sampling clock. When set low, the internally generated master clock, MCLK, is divided by two and used as the ADC sampling clock. Best ADC performance is achieved when the ADCs are sampled directly from fOSCIN using an external crystal or low jitter crystal oscillator. Register C--DIE REVISION Bits 0 to 3: Version The AD9879 quadrature digital upconverter is capable of storing two preconfigured modulation modes called profiles. Each profile defines a transmit frequency tuning word and cable driver amplifier gain (/DAC gain) setting. The Profile Select bit or PROFILE pin programs the current register profile to be used. The Profile Select bit should always be "0" if the PROFILE pin is to be used to switch between profiles. Using the Profile Select bit as a means of switching between different profiles requires the PROFILE pin to be tied low. Registers 10-17: Carrier Frequency Tuning Tx Path Frequency Tuning Words The die version of the chip can be read from this register. Register D--Tx Frequency Tuning Words LSBs This register accommodates two least significant bits for both of the frequency tuning words. See description of Carrier Frequency Tuning. Register E--DAC Gain Control Bits 0 to 3: DAC Fine Gain Control The frequency tuning word (FTW) determines the DDS-generated carrier frequency (fC) and is formed via a concatenation of register addresses. The 26-bit FTW is spread over four register addresses. Bit 25 is the MSB and Bit 0 is the LSB. The carrier frequency equation is given as: fC = [ FTW fSYSCLK ] / 226 This bit field sets the DAC gain if the Tx Path AD8321/AD8323 Gain Control Select bit (Register F, Bit 3) is set to 0. The DAC gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB. Table III details the programming. Table III. where fSYSCLK = M fOSCIN and FTW < 0 2000000 Changes to FTW bytes take effect immediately. Cable Driver Gain Control Bits [3:0] 0000 0001 0010 0011 .... 1110 1111 DAC Gain 0.0 dB (Default) 0.5 dB 1.0 dB 1.5 dB .... 7.0 dB 7.5 dB The AD9879 has a 3-pin interface to the AD832x family of programmable gain cable driver amplifiers. This allows direct control of the cable driver's gain through the AD9879. In its Default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (CA) interface. If Bit 3 of Register F is set high, Bits [7:4] determine the 8-bit word sent over the CA interface according to Table IV. Table IV. Register F -- Tx PATH CONFIGURATION Bit 0: Tx Path Transmit Single Tone Bits [7:4] 0000 0001 ... 0111 1000 CA Interface Transmit Word 0000 0000 (Default) 0000 0001 ... 0100 0000 1000 0000 Active high configures the AD9879 for single-tone applications (e.g., FSK). The AD9879 will supply a single frequency output as determined by the frequency tuning word selected by the active profile. In this mode, the TXIQ input data pins are ignored but should be tied to a valid logic voltage level. Default value is 0 (inactive). Bit 1: Tx Path Spectral Inversion When set to 1, inverted modulation is performed: MODULAR_OUT = I cos (wt ) + Q sin (wt ) Default is logic zero, noninverted modulation: [ ] In this mode, the lower bits determine the fine gain setting of the DAC output. Table V. Bits [3:0] 0000 0001 ... 1110 1111 DAC Fine Gain 0.0 dB (Default) 0.5 dB ... 7.0 dB 7.5 dB MODULAR_OUT = I cos (wt ) + Q sin (wt ) Bit 2: Tx Path Bypass Sinc Filter -1 [ ] Setting this bit high bypasses the digital inverse sinc filter of the Tx path. Bit 3: Tx Path AD8322/AD8327 Gain Control Mode This bit changes the manner in which transmit gain control is performed. Typically either AD8321/AD8323 (default 0) or AD8222/AD8327 (default 1) variable gain cable drivers are programmed over the chip's 3-wire CA interface. The Tx gain REV. 0 New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain control register changes or a new profile is selected. The default value is 0x00 (lowest gain). -11- AD9879 The formula for the combined output level calculation of the AD9879 fine gain and AD8327 or AD8322 coarse gain is: V 8327 = V 9877( 0) + ( fine ) 2 + 6(coarse ) - 19 12-bit current output DAC. The maximum output current of the DAC is set by an external resistor. The Tx output PGA provides additional transmit signal level control. The transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required. Data Assembler V 8322 = V 9877(0) + ( fine ) 2 + 6(coarse ) - 14 with: fine = decimal value of Bits [3:0] coarse = decimal value of Bits [7:8] V9877(0): Level at AD9879 output in dBmV for fine = 0. V8327: Level at output of AD8327 in dBmV. V8322: Level at output of AD8322 in dBmV. DEVICE OVERVIEW To gain a general understanding of the AD9879, it is helpful to refer to Figure 1, which displays a block diagram of the device architecture. The device consists of a transmit path, receive path, and auxiliary functions, such as a DPLL, a sigma-delta DAC, a serial control port, and a cable amplifier interface. Transmit Path The transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a The AD9879 data path operates on two 12-bit words, the I and Q components, that form a complex symbol. The data assembler builds the 24-bit complex symbols from four consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The nibbles are strobed synchronous to the master clock, MCLK, into the data assembler. A high level on TxSYNC signals the start of a transmit symbol. The first two nibbles of the symbol form the I component, the second two nibbles form the Q component. Symbol components are assumed to be in twos complement format. The timing of the interface is fully described in the Transmit Timing section of this data sheet. AD9879 DATA ASSEMBLER TXIQ 6 I 12 FIR LPF 4 12 CIC LPF QUADRATURE MODULATOR COS 4 -- DAC GAIN CONTROL SINC-1 BYPASS SINC-1 MUX 12 DAC FSADJ TX TXSYNC Q 12 4 12 4 DDS SIN (fSYSCLK) (fOSCIN) PLL OSCIN M XTAL (fIQCLK) 4 MCLK REFCLK R (fMCLK) 4 - INPUT REG 8 12 OSCIN CA_PORT PROFILE SPORT 3 CA INTERFACE PROFILE SELECT - - _OUT FLAG1 2 (fOSCIN) 2 4 SERIAL INTERFACE 7 ADC I INPUT RXIQ[3:0] 4 IQ MUX 7 ADC Q INPUT RXPORT RXSYNC 2 (fOSCIN) 12 10 ADC IF10 INPUT IF[11:0] IF MUX 12 ADC MUX IF12 INPUT VIDEO INPUT - -- + DAC CLAMP LEVEL Figure 1. Block Diagram -12- REV. 0 AD9879 INTERPOLATION FILTER Once through the Data Assembler, the IQ data streams are fed through a 4 FIR low-pass filter and a 4 Cascaded IntegratorComb (CIC) low-pass filter. The combination of these two filters results in the sample rate increasing by a factor of 16. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images between the original sampling frequency and the new (16 higher) sampling frequency. DIGITAL UPCONVERTER signal generated either by the crystal oscillator when a crystal is connected between the OSCIN and XTAL pins, or by the clock that is fed into the OSCIN pin, and L is the multiplier programmed through the serial port. L can have the values of 1, 2, 3, or 8. The transmit path expects a new half word of data at the rate of fCLK-A. When the Tx multiplexer is enabled, the frequency of Tx Port is: fCLK -A = 2 f DAC K = 2 L fOSCIN K where K is the interpolation factor. The interpolation factor can be programmed to be 1, 2, or 4. When the Tx multiplexer is disabled, the frequency of the Tx Port is: The digital quadrature modulator stage following the CIC filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream up to the desired carrier frequency. The carrier frequency is controlled numerically by a Direct Digital Synthesizer (DDS). The DDS uses the internal system clock (fSYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is the modulated carrier. The modulated carrier becomes the 12-bit sample sent to the DAC. The receive path contains a 12-bit ADC, a 10-bit ADC, and a dual 7-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input. The 12-bit and 10-bit IF ADCs can convert direct IF inputs up to 70 MHz and run at sample rates up to 33 MSPS. A video input with an adjustable signal clamping level along with the 10-bit ADC allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable sigma-delta DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners. The CAPORT provides an interface to the AD8321/AD8323 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers enabling host processor control via the MxFE SPORT. OSCIN Clock Multiplier fCLK Receive Section -A = f DAC K = L fOSCIN K The AD9879 includes two high speed, high performance ADCs. The 10-bit and 12-bit direct IF ADC's deliver excellent undersampling performance with input frequencies as high as 70 MHz. The sampling rate can be as high as 33 MSPS. The ADC sampling frequency can be derived directly from the OSCIN signal or from the on-chip OSCIN multiplier. For highest dynamic performance, it is recommended to choose an OSCIN frequency that can directly be used as the ADC sampling clock. Digital IQ ADC outputs are multiplexed to one 4-bit bus, clocked by a frequency (fMCLK) of four times the sampling rate. The IF ADCs use a multiplexed 12-bit interface with an output word rate of fMCLK. CLOCK AND OSCILLATOR CIRCUITRY The AD9879 can accept either an input clock into the OSCIN Pin or a fundamental mode XTAL across the OSCIN Pin and XTAL Pins as the devices main clock source. The internal PLL then generates the fSYSCLK signal from which all other internal signals are derived. The DAC uses fSYSCLK as its sampling clock. For DDS applications, the carrier is typically limited to about 30% of fSYSCLK. For a 65 MHz carrier, the system clock required is above 216 MHz. The OSCIN multiplier function maintains clock integrity as evidenced by the AD9879's systems excellent phase noise characteristics and low clock-related spur in the output spectrum. External loop filter components consisting of a series resistor (1.3 kW) and capacitor (0.01 mF) provide the compensation zero for the OSCIN multiplier PLL loop. The overall loop performance has been optimized for these component values. DPLL-A CLOCK DISTRIBUTION The AD9879's internal oscillator generates all sampling clocks from a simple, low cost, parallel resonance, fundamental frequency quartz crystal. Figure 2 shows how the quartz crystal is connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry can also be overdriven by a TTL-level clock applied to OSCIN with XTAL left unconnected. fOSCIN = f MCLK M An internal phase-locked loop (PLL) generates the DAC sampling frequency, fSYSCLK, by multiplying OSCIN frequency M times. The MCLK signal (Pin 23), fMCLK, is derived by dividing fSYSCLK by 4. f SYSCLK = fOSCIN M f MCLK = fOSCIN M 4 An external PLL loop filter (Pin 57) consisting of a series resistor and ceramic capacitor (Figure 15, R1 = 1.3 kW, C12 = 0.01 F) is required for stability of the PLL. Also, a shield surrounding these components is recommended to minimize external noise coupling into the PLL's voltage controlled oscillator input (guard trace connected to AVDDPLL). Figure 1 shows that ADCs are either sampled directly by a low jitter clock at OSCIN or by a clock that is derived from the PLL output. Operating modes can be selected in Register 8. Sampling the ADCs directly with the OSCIN clock requires MCLK to be programmed to be twice the OSCIN frequency. Figure 1 shows the clock signals used in the transmit path. The DAC sampling clock, fDAC, is generated by DPLL-A. FDAC has a frequency equal to the L fOSCIN, where fOSCIN is the internal REV. 0 -13- AD9879 PROGRAMMABLE CLOCK OUTPUT REFCLK fREFCLK = fMCLK /R, For R = 2-63 fREFCLK = fOSCIN, For R = 0 In its default setting (0x00 in Register 1), the REFCLK pin provides a buffered output of fOSCIN. The AD9879 provides an auxiliary output clock on Pin 71, REFCLK. The value of the MCLK divider bit field, R, determines its output frequency as shown in the equations: CP1 10 F C1 C2 C3 0.1 F 0.1 F 0.1 F 100 VIDEO IN CP2 10 F C4 C5 C6 0.1 F 0.1 F 0.1 F 94 REFT12 93 REFB12 99 AGND 98 IF12+ 89 IF10- 88 AGND 86 REFT10 85 REFB10 96 AGND 95 AVDD 91 AGND 90 IF10+ 84 AVDD 83 AGND 92 AVDD 87 AVDD 97 IF12- 82 Q+ DNC DRGND DRVDD (MSB) IF(11) IF(10) IF(9) IF(8) IF(7) IF(6) 81 Q- 1 2 3 4 5 6 7 8 9 80 DNC 79 I+ 78 I- 77 DNC 76 DNC 75 DNC 74 AGND 73 AVDD 72 DRVDD 71 REFCLK 70 DRGND 69 DGND 68 - _OUT 67 FLAG1 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 (MSB) RXIQ(3) 16 RXIQ(2) 17 RXIQ(1) 18 RXIQ(0) 19 RXSYNC 20 DRGND 21 DRVDD 22 MCLK 23 DVDD 24 DGND 25 TXSYNC 26 (MSB) TXIQ(5) 27 TXIQ(4) 28 TXIQ(3) 29 TXIQ(2) 30 TXIQ(1) 31 TXIQ(0) 32 DVDD 33 RESET 37 DVDD 38 DGND 39 DGND 40 PROFILE 36 FSADJ 49 AGNDTX 50 DGND 34 DNC 35 SCLK 41 CS 42 SDIO 43 SDO 44 DGNDTX 45 DVDDTX 46 PWRDN 47 REFIO 48 AD9879 TOP VIEW (Pins Down) 66 DVDD 65 CA_EN 64 CA_DATA 63 CA_CLK 62 DVDDOSC 61 OSCIN 60 XTAL 59 DGNDOSC 58 AGNDPLL 57 PLLFILTER 56 AVDDPLL 55 DVDDPLL 54 DGNDPLL 53 AVDDTX 52 TX+ 51 TX- R1 1.3k C11 20pF GUARD TRACE C10 20pF C12 0.01 F C13 0.1 F RSET 4.02k Figure 2. Basic Connection Diagram -14- REV. 0 AD9879 RESET AND TRANSMIT POWER-DOWN Power-Up Sequence On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is deasserted, the AD9879 can be programmed over the serial port. The on-chip PLL requires a maximum of 1 millisecond after the rising edge of RESET or a change of the multiplier factor (M) to completely settle. It is recommended that the PWRDN pin be held low during the reset and PLL settling time. Changes to ADC Clock Select (Register 08h) or SYS Clock Divider N (Register 01) should be programmed before the rising edge of PWRDN. Once the PLL is frequency locked and after the PWRDN pin is brought high, transmit data can be sent reliably. If the PWRDN pin cannot be held low throughout the reset and PLL settling time period, then the Power-Down Digital Tx bit or the PWRDN pin should be pulsed after the PLL has settled. This will ensure correct transmit filter initialization. RESET A software reset (writing a 1 into Bit 5 of Register 00h) is functionally equivalent to the hardware reset but does not force Register 00h to its default value. VS RESET 1msmin PWRDN 5MCLKMIN Figure 3. Power-Up Sequence for Tx Data Path Transmit Power-Down A low level on the PWRDN pin stops all clocks linked to the digital transmit data path and resets the CIC filter. Deasserting PWRDN reactivates all clocks. The CIC filter is held in a reset state for 80 MCLK cycles after the rising edge of PWRDN to allow for flushing of the half-band filters with new input data. Transmit data bursts should be padded with at least 20 symbols of null data directly before the PWRDN pin is deasserted. Immediately after PWRDN pin is deasserted, the transmit burst should start with a minimum of 20 null data symbols. This avoids unintended DAC output samples caused by the transmit path latency and filter settling time. Software Power-Down Digital Tx (Bit 5 in Register 02h) is functionally equivalent to the hardware PWRDN pin and takes effect immediately after the last register bit has been written over the serial port. To initiate hardware reset, the RESET pin should be held low for at least 100 nanoseconds. All internally generated clocks but OSCOUT stop during reset. The rising edge of RESET resets the PLL clock multiplier and reinitializes the programmable registers to their default values. The same sequence as described above in the Power-Up Sequence section should be followed after a reset or change in M. PWRDN 5MCLKMIN 20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS 0 0 0 0 TxIQ 0 0 0 0 TxSYNC Figure 4. Timing Sequence to Flush Tx Data Path REV. 0 -15- AD9879 SIGMA-DELTA OUTPUTS SERIAL INTERFACE FOR REGISTER CONTROL The AD9879 contains an on-chip sigma-delta output that provides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 5. 8 t MCLK 4096 000h 001h 002h 800h FFFh 4096 8 t MCLK 8 t MCLK 8 t MCLK The AD9879 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9879. Single or multiple byte transfers are supported. Also, the interface can be programmed to read words either MSB first or LSB first. The AD9879's serial interface port I/O can be configured to have one bidirectional I/O (SDIO) pin or two unidirectional I/O (SDIO/SDO) pins. General Operation of the Serial Interface Figure 5. Sigma-Delta Output Signals This bit stream can be low-pass filtered to generate a programmable dc voltage of: VDC = (Sigma-Delta Code/4096)(VH) + VL where: VH = VDRVDD - 0.6 V VL = 0.4 V In cable modem set-top box applications, the output can be used to control external variable gain amplifiers or RF tuners. A simple single-pole RC low-pass filter provides sufficient filtering (see Figure 6). AD9879 CONTROL WORD MCLK 8 12 DAC R DC(VL TO VH) C There are two phases to a communication cycle with the AD9879. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9879, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9879 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9879. The eight remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9879 and the system controller. Phase 2 of the communication cycle is a transfer of 1 to 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. Instruction Byte The instruction byte contains the following information as shown below: MSB LSB 17 16 15 N0 14 A4 13 12 11 A1 10 A0 R/W N1 A3 A2 TYPICAL: R = 50k C = 0.1 F f-3dB = 1/(2 RC) = 318Hz Figure 6. Sigma-Delta RC Filter In more demanding applications where additional gain, level shift, or drive capability is required, a first or second order active filter might be considered for each sigma-delta output (see Figure 7). C AD9879 R1 SIGMA-DELTA R VSD C R VOFFSET VOUT = (VSD + VOFFSET) (1 + R/R1)/2 TYPICAL: R = 50k C = 0.1 F f-3dB = 1/(2 RC) = 318Hz OP250 VOUT R The R/W bit of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates a read operation. Logic zero indicates a write operation. The N1:N0 bits determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table VI. Table VI. N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes Figure 7. Sigma-Delta Active Filter with Gain and Offset The Bits A4:A0 determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9879. -16- REV. 0 AD9879 Serial Interface Port Pin Description SCLK--Serial Clock. The serial clock pin is used to synchronize data transfers from the AD9879 and to run the serial port state machine. The maximum SCLK frequency is 15 MHz. Input data to the AD9879 is sampled on the rising edge of SCLK. Output data changes on the falling edge of SCLK. CS--Chip Select. Active low input starts and gates a communication cycle. It allows multiple devices to share a common serial port bus. The SDO and SDIO pins go to a high impedance state when CS is high. Chip select should stay low during the entire communication cycle. SDIO--Serial Data I/O. Data is always written into the AD9879 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register 0. The default is Logic 0, which configures the SDIO pin as unidirectional. SDO--Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9879 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. MSB/LSB Transfers A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with the RESET bit low and the serial port configuration as specified above (XY) reprograms the OSCIN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of tbd fMCLK cycles (wake-up time). CS SCLK SDIO SDO R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n D7n D6n D20 D10 D00 D20 D10 D00 INSTRUCTION CYCLE DATA TRANSFER CYCLE Figure 8a. Serial Register Interface Timing MSB First CS SCLK SDIO SDO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D00 D10 D20 D6n D7n D6n D7n INSTRUCTION CYCLE DATA TRANSFER CYCLE The AD9879 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB First Bit in Register 0. The default is MSB first. When this bit is set active high, the AD9879 serial port is in LSB first format. In LSB first mode, the instruction byte and data bytes must be written from the least significant bit to the most significant bit. In LSB first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. When this bit is set default low, the AD9879 serial port is in MSB first format. In MSB first mode, the instruction byte and data bytes must be written from the most significant bit to the least significant bit. In MSB first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator changes to 0x1F. Notes on Serial Port Operation Figure 8b. Serial Register Interface Timing LSB First tDS CS tSCLK tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 9. Timing Diagram for Register Write to AD9879 CS SCLK tDV SDIO SDO DATA BIT N DATA BIT N Figure 10. Timing Diagram for Register Read TRANSMIT PATH (Tx) Transmit Timing The AD9879 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 00h. It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. The AD9879 provides a master clock MCLK and expects 6-bit multiplexed TxIQ data on each rising edge. Transmit symbols are framed with the TxSYNC input. TxSYNC high indicates the start of a transmit symbol. Four consecutive 6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). Data Assembler The input data stream is representative complex data. Two 6-bit words form a 12-bit symbol component (in twos complement format). Four input samples are required to produce one I/Q data pair. The I/Q sample rate fIQCLK at the input to the first half-band filter is a quarter of the input data rate fMCLK. The I/Q sample rate fIQCLK puts a bandwidth limit on the maximum transmit spectrum. This is the familiar Nyquist limit and is equal to one-half fIQCLK that hereafter will be referred to as fNYQ. REV. 0 -17- AD9879 tSU MCLK tHD TxSYNC TxIQ TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] Figure 11. Timing Diagram for Register Read Half-Band Filters (HBFs) HBF 1 and HBF 2 are both interpolating filters, each of which doubles the sampling rate. Together, HBF 1 and HBF 2 have 26 taps and provide a factor-of-four increase in the sampling rate (4 fIQCLK or 8 fNYQ). In relation to phase response, both HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature as phase distortion is generally intolerable in a data transmission system. Cascaded Integrator-COMB (CIC) Filter The CIC filter is configured as a programmable interpolator and provides a sample rate increase by a factor of 4. The frequency response of the CIC filter is given by: 1 1 - e - j(2 f ( 4 )) 1 sin( 4f ) H( f ) = = 1 - e j2 f 4 sin( f ) 4 3 3 The frequency response in this form is such that f is scaled to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the CIC filter. H(f/R) will yield the frequency response with respect to the input sample of the CIC filter. Combined Filter Response signals having a bandwidth of no more than about 60% of fNYQ. Thus, in order to keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of two prior to representing it to the AD9879. Note that without oversampling, the Nyquist bandwidth of the baseband data corresponds to the fNYQ. As such, the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of the digital filters. Furthermore, if the baseband data applied to the AD9879 has been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an value is used to modify the bandwidth of the data where the value of is such that 0 < < 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwith. Thus, with 2 oversampling of the baseband data and =1, the Nyquist bandwidth of the data will correspond with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of that can be implemented is 0.45. This is because the data bandwidth becomes: 1 2 (1 + ) f NYQ = 0.725 f NYQ which puts the data bandwidth at the extreme edge of the flat portion of the filter response. If a particular application requires an value between 0.45 and 1, then the user must oversample the baseband data by at least a factor of four. The combined HB1, HB2, and CIC filter introduces, over the frequency range of the data to be transmitted, a worst-case droop of less than 0.2 dB. The combined frequency response of HBF 1, HBF 2, and CIC puts a limit on the input signal bandwidth that can be propagated through the AD9879. The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9879. A look at the pass-band detail of the combined filter response (Figure 12 and Figure 13) indicates that in order to maintain an amplitude error of no more than 1 dB, we are restricted to 1 1 0 -1 MAGNITUDE - dB MAGNITUDE - dB -2 0 -1 -2 -3 -3 -4 -5 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW 1.0 -4 -5 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW 1.0 Figure 12. Cascaded Filter Pass-Band Detail (N = 4) Figure 13. Cascaded Filter Pass-Band Detail (N = 3) -18- REV. 0 AD9879 Tx Signal Level Considerations The quadrature modulator itself introduces a maximum gain of 3 dB in signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. Then the output of the modulator, z is: The maximum complex input rms value calculation uses both I and Q symbol components that add a factor of 2 (= 6 dB) to the formula. Table VII shows typical I-Q input test signals with amplitude levels related to 12-bit full scale (FS). Tx Throughput and Latency z = x cos(t ) - x sin(t ) O X Z I X [ ] Data inputs effect the output fairly quickly but remain effective due to AD9879's filter characteristics. Data transmit latency through the AD9879 is easiest to describe in terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are when an effect is first seen after an input value change. Latency of I/Q data entering the data assembler (AD9879 input) to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). DC values applied to the data assembler input will take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the DAC output. Frequency hopping is accomplished via changing the PROFILE input pin. The time required to switch from one frequency to another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles). D/A Converter Figure 14. 16-Quadrature Modulation It can be shown that |z| assumes a maximum value of |z| = (x2 + x2) = 2 (a gain of +3 dB). However, if the same number of bits were used to represent the |z|values, as is used to represent the x values, an overflow would occur. To prevent this possibility, an effective -3 dB attenuation is internally implemented on the I and Q data path: |z| = / / (12 + 12) = x AD9879 DAC Tx CA LOW-PASS FILTER 3 CA_EN CA_DATA CA_CLK AD832x 75 A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases (please see the Analog Devices DDS Tutorial at: www.analog.com/dds). The conversion process will produce aliased components of the fundamental signal at n fSYSCLK fCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC output. It is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest so as to avoid modulation impairments. A relatively inexpensive seventh order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. The AD9879 provides true and complement current outputs. The full-scale output current is set by the RSET resistor at Pin 49 and the DAC Gain register. Assuming maximum DAC gain, the value of RSET for a particular full-scale IOUT is determined using the following equation: RSET = 32 V DACRSET IOUT = 39.4 IOUT VARIABLE GAIN CABLE DRIVER AMPLIFIER Figure 15. 16-Quadrature Modulation The following example assumes an PK/rms level of 10 dB: Maximum Symbol Component Input Value = (2047 LSBs - 0.2 dB ) = 2000 LSBs For example, if a full-scale output current of 20 mA is desired, then RSET = (39.4/0.02) , or approximately 2 k. The following equation calculates the full-scale output current including the programmable DAC gain control. IOUT = [39.4 / RSET ] x 10 ((-7.5 + 0.5 NGAIN ) / 20) where NGAIN is the value of DAC Fine Gain Control[3:0]. Maximum Complex Input RMS Value = 2000 LSBs 6 dB - Pk rms (dB ) = 1265 LSBs rms Table VII. I-Q Input Test Signals Analog Output Single Tone (fC - f) Single Tone (fC + f) Dual Tone (fC f) Digital Input I = cos(f) Q = cos(f + 90 ) = -sin(f) I = cos(f) Q = cos(f + 270 ) = +sin(f) I = cos(f) Q = cos(f + 180 ) = -cos(f) or Q = +cos(f) -19- Input Level FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB Modulator Output Level FS - 3.0 dB FS - 3.0 dB FS REV. 0 AD9879 The full-scale output current range of the AD9879 is 4 mA-20 mA. Full-scale output currents outside of this range will degrade SFDR performance. SFDR is also slightly affected by output matching, that is, the two outputs should be terminated equally for best SFDR performance. The output load should be located as close as possible to the AD9879 package to minimize stray capacitance and inductance. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads (such as an LC filter). Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the AD9879 will see for signals within the filter pass band. For example, a 50 terminated input/output low-pass filter will look like a 25 load to the AD9879. The output compliance voltage of the AD9879 is -0.5 V to +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V, otherwise signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The AD9879 true and complement outputs can be differentially combined for common-mode rejection using a broadband 1:1 transformer. Using a grounded center tap results in signals at the AD9879 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. A differential combiner might consist of a transformer or an operational amplifier. The object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 Hz hum or clock feedthrough that is equally present on both individual signals. AD9879 Tx DAC CA 3 CA_EN CA_DATA CA_CLK LOW-PASS FILTER 75 Connecting the AD9879 true and complement outputs to the differential inputs of the gain programmable cable drivers AD8321/AD8323 or AD8322/AD8327 provides an optimized solution for the standard compliant cable modem upstream channel. The cable driver's gain can be programmed through a direct 3-wire interface using the AD9879's profile registers. PROGRAMMING THE AD8321/AD8323 OR AD8323/AD8327 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain of the AD832x family of cable driver amplifiers can be accomplished via the AD9879 cable amplifier control interface. Four 8-bit registers within the AD9879 (one per profile) store the gain value to be written to the serial 3-wire port. Typically, either the AD8321/AD8323 or AD8222/AD8227 variable gain cable amplifiers are connected to the chip's 3-wire cable amplifier interface. The Tx Gain Control Select bit in Register 0Fh changes the interpretation of the bits in Register 13h, 17h, 1Bh, and 1Fh. See Cable Driver Gain Control Register description. Data transfers to the gain programmable cable driver amplifier are initiated by four conditions including: 1. Power-up and Hardware Reset--Upon initial power up and every hardware reset, the AD9879 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9879 writes all 0s out of the 3-wire cable amplifier control interface. 2. Software Reset--Writing a 1 to Bit 5 of Address 00h initiates a software reset. On a software reset, the AD9879 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9879 writes all 0s out of the 3-wire cable amplifier control interface if the gain was on a different setting (different from 0) before. 3. Change in Profile Selection--The AD9879 sample the PROFILE input pin together with the two Profile Select Bits and writes to the AD832x gain control registers when a change in profile and gain is determined. The data written to the cable driver amplifier comes from the AD9879 gain control register associated with the current profile. 4. Write to AD9879 Cable Driver Amplifier Control Registers--The AD9879 will write gain control data associated with the current profile to the AD832x whenever the selected AD9879 cable driver amplifier gain setting is changed. Once a new stable gain value has been detected (48 MCLK to 64 MCLK cycles after initiation) data write starts with CA_EN going low. The AD9879 will always finish a write sequence to the cable driver amplifier once it is started. The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and has been designed to prevent erroneous write cycles from ever occurring. AD832x VARIABLE GAIN CABLE DRIVER AMPLIFIER Figure 16. Cable Amplifier Connection 8 t MCLK 8 t MCLK 4 t MCLK 4 t MCLK CA_EN CA_CLK CA_DATA MSB LSB 8 t MCLK Figure 17. Cable Amplifier Interface Timing -20- REV. 0 AD9879 RECEIVE PATH (Rx) IF10 and IF12 ADC Operation The IF10 and IF12 ADCs have a common architecture and share many of the same characteristics from an applications standpoint. Most of the information in the section below will be applicable to both IF ADCs. Differences, where they exist, will be highlighted. Input Signal Range and Digital Output Codes Another consideration for getting the best performance from the ADC inputs is the dc biasing of the input signal. Ideally, the signal should be biased to a dc level equal to the midpoint of the ADC reference voltages, REFT12 and REFB12. Nominally, this level will be 1.2 V. When ac-coupled, the ADC inputs will selfbias to this voltage and requires no additional input circuitry. Figure 20 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the ADC input. The 33 series termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. The series capacitors provide ac signal coupling which ensures that the ADC inputs operate at the optimal dc bias voltage. The shunt capacitor sources the dynamic currents required to charge the SHA input capacitors, removing this requirement from the ADC buffer. The values of CC and CS should be calculated to get the correct HPF and LPF corner frequencies. t EE The IF ADCs have differential analog inputs labelled IF+ and IF-. The signal input, VAIN, is the voltage difference between the two input pins, VAIN = VIF+ - VIF-. The full-scale input voltage range is determined by the internal reference voltages, REFT and REFB, which define the top and bottom of the scale. The peak input voltage to the ADC is the difference between REFT and REFB which is 1 VPD. This results in the ADC fullscale input voltage range of 2 VPPD. The digital output code is straight binary and is illustrated in Table VIII. Table VIII. REFCLK M=8 IF[11:0] 111...111 111...111 111...110 ... 100...001 100...000 011...111 ... 000...001 000...000 000...000 Input Signal Voltage VAIN >= +1.0 V VAIN = +1.0 - (1 LSB) V VAIN = +1.0 - (2 LSB) V VAIN = +1 LSB V VAIN = 0.0 V VAIN = -1 LSB V VAIN = -1.0 + (2 LSB) V VAIN = -1.0 V VAIN < -1.0 V t MD MCLK t OD RxIQ DATA I[7:4] I[3:0] Q[7:4] Q[3:0] I[7:4] I[3:0] RxSYNC IF DATA IF10 IF12 IF10 IF12 IF10 IF12 Figure 18. Rx Port Timing (Default Mode: Multiplexed IF ADC Data) t EE REFCLK M=8 The IF10 ADC digital output code occupies the 10 most significant bits of the Rx digital output port (IF[11:2]). The output codes clamp to the top or the bottom of the scale when the inputs are overdriven. Driving the Input t OD t MD MCLK The IF ADCs have differential switched capacitor sample-andhold amplifier (SHA) inputs. The nominal differential input impedance is 4.0 k||3 pF. This impedance can be used as the effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from non-zero source impedances. It should be noted however that for best performance additional requirements must be met by the signal source. The SHA has input capacitors that must be recharged each time the input is sampled. This results in a dynamic input current at the device input. This demands that the source has low (<50 V) output impedance at frequencies up to the ADC sampling frequency. Also, the source must have settling to better than 0.1% in <1/2 ADC CLK period. RxIQ DATA I[7:4] I[3:0] Q[7:4] Q[3:0] I[7:4] I[3:0] RxSYNC IF DATA IF10 OR IF12 IF10 OR IF12 IF10 OR IF12 Figure 19. Rx Port Timing (Nonmultiplexed Data) 33 VS 33 CC AINP CC CS AINN Figure 20. Simple ADC Drive Configuration REV. 0 -21- AD9879 PCB DESIGN CONSIDERATIONS Although the AD9879 is a mixed-signal device, the part should be treated as an analog component. The digital circuitry on-chip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. Following the power, grounding, and layout recommendations in this section will help the user get the best performance from the MxFE. Component Placement The DVDD portion of the plane brings the current used to power the digital portion of the MxFE to the device. This should be treated similar to the 3VDD power plane and be kept from going underneath the MxFE or analog components. The MxFE should largely sit above the AVDD portion of the power plane. The AVDD and DVDD power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the DVDD portion of the MxFE from corrupting the AVDD supply. This can be done by using ferrite beads between the voltage source and DVDD and between the source and AVDD. Both DVDD and AVDD should have a low ESR, bulk decoupling capacitor on the MxFE side of the ferrite as well as a low ESR, ESL decoupling capacitors on each supply pin (i.e., the AD9879 requires 17 power supply decoupling caps). The decoupling caps should be placed as close to the MxFE supply pins as possible. An example of the proper decoupling is shown in the AD9875 evaluation board schematic. Ground Planes If the three following guidelines of component placement are followed, chances for getting the best performance from the MxFE are greatly increased. First, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the MxFE or analog circuits. Second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. Third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. In order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. This will keep the highest frequency return current paths short, and prevent them from traveling over the sensitive MxFE and analog portions of the ground plane. Also, these circuits should be generously bypassed at each device which will further reduce the high frequency ground currents. The MxFE should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the MxFE. The analog circuits should be placed furthest from the power supply. The AD9879 has several pins which are used to decouple sensitive internal nodes. These pins are REFIO, REFB10, REFT10, REFB12, and REFT12. The decoupling capacitors connected to these points should have low ESR and ESL. These capacitors should be placed as close to the MxFE as possible and be connected directly to the analog ground plane. The resistor connected to the FSADJ pin and the RC network connected to the PLLFILT pin should also be placed close to the device and connected directly to the analog ground plane. Power Planes and Decoupling In general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. All ground connections should be made as short as possible. This will result in the lowest impedance return paths and the quietest ground connections. If the components cannot be placed in a manner that would keep the high frequency ground currents from traversing under the MxFE and analog components, it may be necessary to put current steering channels into the ground plane to route the high frequency currents around these sensitive areas. These current steering channels should be made only when and where necessary. Signal Routing The AD9879 evaluation board demonstrates a good power supply distribution and decoupling strategy. The board has four layers; two signal layers, one ground plane and one power plane. The power plane is split into a 3 VDD section which is used for the 3 V digital logic circuits, a DVDD section that is used to supply the digital supply pins of the AD9879, an AVDD section that is used to supply the analog supply pins of the AD9879, and a VANLG section that supplies the higher voltage analog components on the board. The 3 VDD section will typically have the highest frequency currents on the power plane and should be kept the furthest from the MxFE and analog sections of the board. The digital Rx and Tx signal paths should be kept as short as possible. Also, the impedance of these traces should have a controlled impedance of about 50 . This will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. If the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 to 47 ) should be placed close to all signal sources. It is a good idea to series terminate all clock signals at their source regardless of trace length. The receive (I in, Q in, and RF in) signals are the most sensitive signals on the entire board. Careful routing of these signals is essential for good receive path performance. The Rx+/- signals form a differential pair and should be routed together as a pair. By keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the MxFE will further reduce the possibility of noise corrupting these signals. -22- REV. 0 AD9879 OUTLINE DIMENSIONS 100-Lead Plastic Quad Flatpack (MQFP) (S-100C) Dimensions shown in millimeters 23.20 BSC 20.00 BSC 3.40 MAX 80 81 18.85 REF 51 50 12.35 REF TOP VIEW (PINS DOWN) 14.00 BSC 17.20 BSC PIN 1 100 1 30 31 0.65 BSC 0.40 0.22 2.90 2.70 2.50 1.03 0.88 0.73 SEATING PLANE 0.13 COPLANARITY 0.50 0.25 COMPLIANT TO JEDEC STANDARDS MS-022-GC-1 REV. 0 -23- -24- C02773-0-8/02(0) PRINTED IN U.S.A. This datasheet has been download from: www..com Datasheets for electronics components. |
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