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MC3479 Stepper Motor Driver
The MC3479 is designed to drive a two-phase stepper motor in the bipolar mode. The circuit consists of four input sections, a logic decoding/sequencing section, two driver-stages for the motor coils, and an output to indicate the Phase A drive state.
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Single Supply Operation: 7.2 to 16.5 V 350 mA/Coil Drive Capability Clamp Diodes Provided for Back-EMF Suppression Selectable CW/CCW and Full/Half Step Operation Selectable High/Low Output Impedance (Half Step Mode) TTL/CMOS Compatible Inputs Input Hysteresis: 400 mV Minimum Phase Logic Can Be Initialized to Phase A Phase A Output Drive State Indication (Open-Collector) Pb-Free Package is Available*
VM
PDIP-16 P SUFFIX CASE 648C
MARKING DIAGRAM
16 MC3479P AWLYYWWG
Clk
Clock Driver
L1
1
L2 CW/CCW CW/CCW Logic VD L3 Full/Half Step F/H Step Driver L4 OIC OIC
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
VD L2 L1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VM L3 L4 GND Phase A CW/CCW Full/Half Step
Phase A
Bias/Set
GND
GND
Figure 1. Representative Block Diagram
Bias/Set Clk OIC
ORDERING INFORMATION
Device MC3479P MC3479PG TA = 0 to +70C Operating Temperature Range Package PDIP-16 PDIP-16 (Pb-Free) 25 Units / Rail CW/CCW Full/Half Step OIC Clk *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
(Top View)
Shipping
INPUT TRUTH TABLE
Input Low CW Full Step Hi Z Input High CCW Half Step Low Z
Positive Edge Triggered
1
June, 2006 - Rev. 7
Publication Order Number: MC3479/D
MC3479
MAXIMUM RATINGS
Rating Supply Voltage Clamp Diode Cathode Voltage (Pin 1) Driver Output Voltage Drive Output Current/Coil Input Voltage (Logic Controls) Bias/Set Current Phase A Output Voltage Phase A Sink Current Junction Temperature Storage Temperature Range Symbol VM VD VOD IOD Vin IBS VOA IOA TJ Tstg Value + 18 VM + 5.0 VM + 6.0 500 - 0.5 to + 7.0 - 10 + 18 20 + 150 - 65 to + 150 Unit Vdc Vdc Vdc mA Vdc mA Vdc mA C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic Supply Voltage Clamp Diode Cathode Voltage Driver Output Current (Per Coil) (Note 1) Input Voltage (Logic Controls) Bias/Set Current (Outputs Active) Phase A Output Voltage Phase A Sink Current Operating Ambient Temperature 1. See section on Power Dissipation in Application Information. Symbol VM VD IOD Vin IBS VOA IOA TA Min + 7.2 VM - 0 -300 - 0 0 Max + 16.5 VM + 4.5 350 + 5.5 - 75 VM 8.0 + 70 Unit Vdc Vdc mA Vdc mA Vdc mA C
DC ELECTRICAL CHARACTERISTICS (Specifications apply over the recommended supply voltage and temperature range,
(Notes 2, 3) unless otherwise noted.) Characteristic INPUT LOGIC LEVELS Threshold Voltage (Low-to-High) Threshold Voltage (High-to-Low) Hysteresis Current: (VI = 0.4 V) (VI = 5.5 V) (VI = 2.7 V) DRIVER OUTPUT LEVELS Output High Voltage (IBS = - 300 mA) Output Low Voltage (IBS = - 300 mA, IOD = 350 mA) Differential Mode Output Voltage Difference (Note 4) (IBS = - 300 mA, IOD = 350 mA) Output Leakage, Hi Z State (0 v VOD v VM, IBS = - 5.0 mA) (0 v VOD v VM, IBS = - 300 mA, F/H = 2.0 V, OIC = 0.8 V) CLAMP DIODES Forward Voltage Leakage Current (Per Diode) (ID = 350 mA) (Pin 1 = 21 V; Outputs = 0 V; IBS = 0 mA) 1, 2, 3, 14, 15 VDF IDR - - 2.5 - 3.0 100 Vdc mA 14, 15 14, 15 IOD = - 350 mA IOD = - 0.1 mA 2, 3, 14, 15 VOHD VOLD DVOD CVOD IOZ1 IOZ2 VM -2.0 VM -1.2 - - - -100 -100 - - - - - - - - - 0.8 0.15 0.15 +100 +100 Vdc Vdc Vdc mA 7, 8, 9, 10 VTLH VTHL VHYS IIL - 0.8 0.4 -100 - - - - - - - - 2.0 - - - + 100 + 20 Vdc Vdc Vdc mA Pins Symbol Min Typ Max Unit
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MC3479
DC ELECTRICAL CHARACTERISTICS (Specifications apply over the recommended supply voltage and temperature range,
(Notes 2, 3) unless otherwise noted.) Characteristic PHASE A OUTPUT Output Low Voltage Off State Leakage Current POWER SUPPLY Power Supply Current (IOD = 0 mA, IBS = - 300 mA) (L1 = VOHD, L2 = VOLD, L3 = VOHD, L4 = VOLD) (L1 = VOHD, L2 = VOLD, L3 = Hi Z, L4 = Hi Z) (L1 = VOHD, L2 = VOLD, L3 = VOHD, L4 = VOHD) 16 IMW IMZ IMN - - - - - - 70 40 75 mA (IOA = 8.0 mA) (VOHA = 16.5 V) 11 VOLA IOHA - - - - 0.4 100 Vdc mA Pins Symbol Min Typ Max Unit
BIAS/SET CURRENT To Set Phase A 6 IBS - 5.0 - - mA
2. Algebraic convention rather than absolute values is used to designate limit values. 3. Current into a pin is designated as positive. Current out of a pin is designated as negative. 4. DVOD = VOD1,2 - VOD3,4 where:VOD1,2 = (VOHD1 - VOLD2) or (VOHD2 - VOLD1), and VOD3,4 = (VOHD3 - VOLD4) or (VOHD4 - VOLD3).
PACKAGE THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction-to-Ambient (No Heatsink) Symbol RqJA Min - Typ 45 Max - Unit C/W
AC SWITCHING CHARACTERISTICS (TA = + 25C, VM = 12 V) (See Figures 2, 3, 4) (Notes 5, 6)
Characteristic Clock Frequency Clock Pulse Width (High) Clock Pulse Width (Low) Bias/Set Pulse Width Setup Time (CW/CCW and F/HS) Hold Time (CW/CCW and F/HS) Propagation Delay (Clk-to-Driver Output) Propagation Delay (Bias/Set-to-Driver Output) Propagation Delay (Clk-to-Phase A Low) Propagation Delay (Clk-to-Phase A High) 7-11 7-11 Pins 7 7 7 6 10-7 9-7 10-7 9-7 Symbol fCK PWCKH PWCKL PWBS tsu th tPCD tPBSD tPHLA tPLHA Min 0 10 10 10 5.0 10 - - - - Typ - - - - - - 8.0 1.0 12 5.0 Max 50 - - - - - - - - - Unit kHz ms ms ms ms ms ms ms ms ms
5. Algebraic convention rather than absolute values is used to designate limit values. 6. Current into a pin is designated as positive. Current out of a pin is designated as negative.
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MC3479
+ 12 V 0.1 mF VM 16 56 k Bias/Set 6 3 L1 L4 1.0 k 1.0 k 1.0 k L3 15 11 4.0 k Phase A 1.0 k + 12 V L1 - L4 Outputs 2 L2 1.0 k 1.0 k Bias/Set Input VM 0 tPBSD (High Impedance) tPBSD VM - 1.0
PWBS VM - 1.0
MC3479P
Clk OIC F / HS CW / CCW 7 8 9 10 4 5 12 13 14
Note: tr, tf (10% to 90%) for input signals are p 25 ns.
Figure 2. AC Test Circuit
Figure 3. Bias/Set Timing (Refer to Figure 2)
PIN FUNCTION DESCRIPTION
Pin # 16 4, 5, 12, 13 1 Function Power Supply Ground Clamp Diode Voltage Symbol VM GND VD Description Power supply pin for both the logic circuit and the motor coil current. Voltage range is + 7.2 to + 16.5 V. Ground pins for the logic circuit and the motor coil current. The physical configuration of the pins aids in dissipating heat from within the IC package. This pin is used to protect the outputs where large voltage spikes may occur as the motor coils are switched. Typically a diode is connected between this pin and Pin 16. See Figure 12. High current outputs for the motor coils. L1 and L2 are connected to one coil, and L3 and L4 to the other coil. This pin is typically 0.7 volts below VM. The current out of this pin (through a resistor to ground) determines the maximum output sink current. If the pin is opened (IBS < 5.0 mA) the outputs assume a high impedance condition, while the internal logic presets to a Phase A condition. The positive edge of the clock input switches the outputs to the next position. This input has no effect if Pin 6 is open. When low (Logic "0"), each clock input pulse will cause the motor to rotate one full step. When high, each clock pulse will cause the motor to rotate one-half step. See Figure 7 for sequence. This input allows reversing the rotation of the motor. See Figure 7 for sequence. This input is relevant only in the half step mode (Pin 9 > 2.0 V). When low (Logic "0"), the two driver outputs of the non-energized coil will be in a high impedance condition. When high the same driver outputs will be at a low impedance referenced to VM. See Figure 7. This open-collector output indicates (when low) that the driver outputs are in the Phase A condition (L1 = L3 = VOHD, L2 = L4 = VOLD).
2, 3, 14, 15 6
Driver Outputs Bias/Set
L1, L2 L3, L4 B/S
7 9
Clock Full/Half Step
Clk F/HS
10 8
Clockwise/ Counterclockwise Output Impedance Control
CW/CCW OIC
11
Phase A
Ph A
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MC3479
APPLICATION INFORMATION
General Outputs
The MC3479 integrated circuit is designed to drive a stepper positioning motor in applications such as disk drives and robotics. The outputs can provide up to 350 mA to each of two coils of a two-phase motor. The outputs change state with each low-to-high transition of the clock input, with the new output state depending on the previous state, as well as the input conditions at the logic controls.
The outputs (L1-L4) are high current outputs (see Figure 5), which when connected to a two-phase motor, provide two full-bridge configurations (L3 and L4 are not shown in Figure 5). The polarities applied to the motor coils depend on which transistor (QH or QL) of each output is on, which in turn depends on the inputs and the decoding circuitry.
3.0 V Clk 0 tPCD
PWCLKH 1.5 V
PWCLKL
L1 - L4 Outputs 3.0 V F/HS, CW/CCW Inputs 0 Phase A Output
6.0 V tsu 1.5 V tPHLA 1.5 V tPLHA th Note: tr, tf (10% to 90%) for input signals are p 10 ns.
Figure 4. Clock Timing (Refer to Figure 2)
VM
VD
QH IBS B/S IBS L1 QL Current Drivers and Logic Logic Decoding Circuit To L3, L4 Transistors CW / CCW F/HS Inputs
QH Motor Coil
L2
QL
RB
Parasitic Diodes
OIC Clk
Figure 5. Output Stages
The maximum sink current available at the outputs is a function of the resistor connected between Pin 6 and ground (see section on Bias/Set operation). Whenever the outputs
are to be in a high impedance state, both transistors (QH and QL of Figure 5) of each output are off.
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MC3479
VD
This pin allows for provision of a current path for the motor coil current during switching, in order to suppress back-EMF voltage spikes. VD is normally connected to VM (Pin 16) through a diode (zener or regular), a resistor, or directly. The peaks instantaneous voltage at the outputs must not exceed VM by more than 6.0 V. The voltage drop across the internal clamping diodes must be included in this portion of the design (see Figure 6). Note the parasitic diodes (Figure 5) across each QL of each output provide for a complete circuit path for the switched current.
When taken to a Logic "1" (>2.0 V), the outputs change a half step with each clock cycle, with the sequence direction depending on the CW/CCW input. Eight steps (Phase A to H) result for each complete cycle of the sequencing logic. Phase A, C, E and G correspond (in polarity) to Phase A, B, C, and D, respectively, of the full step sequence. Phase B, D, F and H provide current to one motor coil, while de-energizing the other coil. The condition of the outputs of the de-energized coil depends on the OIC input, see Figure 7 timing diagram.
OIC
3.0
2.0
1.0
The output impedance control input determines the output impedance to the de-energized coil when operating in the half-step mode. When the outputs are in Phase B, D, F or H (Figure 7) and this input is at a Logic "0" (<0.8 V), the two outputs to the de-energized coil are in a high impedance condition - QL and QH of both outputs (Figure 5) are off. When this input is at a Logic "1" (>2.0 V), a low impedance output is provided to the de-energized coil as both outputs have QH on (QL off). To complete the low impedance path requires connecting VD to VM as described elsewhere in this data sheet.
0 100 200 ID (mA) 300
VF (V)
0
Bias/Set
Figure 6. Clamp Diode Characteristics Full/Half Step
When this input is at a Logic "0" (< 0.8 V), the outputs change a full step with each clock cycle, with the sequence direction depending on the CW/CCW input. There are four steps (Phase A, B, C, D) for each complete cycle of the sequencing logic. Current flows through both motor coils during each step, as shown in Figure 7.
This pin can be used for three functions: a) determining the maximum output sink current; b) setting the internal logic to a known state; and c) reducing power consumption. a) The maximum output sink current is determined by the base drive current supplied to the lower transistors (QLs of Figure 5) of each output, which in turn, is a function of IBS. The appropriate value of IBS can be approximated using Figure 11.
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MC3479
Clk Bias/Set CW/CCW Phase A L1 L2 L3 L4 Phase A Output F/HS OIC = High Impedance = Logic 0" = Dont Care B C D A B C B A D C B
(a) Full Step Mode A L1 L2 L3 L4 B C D E F G
H
A
B
C
D
(b) Half Step Mode
CW/CCW F/HS
= High Impedance = Logic 0" = Logic 1", OIC = Logic 0"
A L1 L2 L3 L4 Phase A Output
B
C
D
E
F
G
H
A
B
C
D
CW/CCW = Logic 0" = Logic 1" F/HS = Logic 1" OIC (c) Half Step Mode
Figure 7. Output Sequence
The value of RB (between this pin and ground) is then determined by:
V * 0.7 V R+M B I BS
Power Dissipation
b) When this pin is opened (raised to VM) such that IBS is < 5.0 mA, the internal logic is set to the Phase A condition, and the four driver outputs are put into a high impedance state. The Phase A output (Pin 11) goes active (low), and input signals at the controls are ignored during this time. Upon re-establishing IBS, the driver outputs become active, and will be in the Phase A position (L1 = L3 = VOHD, L2 = L4 = VOLD). The circuit will then respond to the inputs at the controls. The Set function (opening this pin) can be used as a powerup reset while supply voltages are settling. A CMOS logic gate (powered by VM) can be used to control this pin as shown in Figure 12. c) Whenever the motor is not being stepped, power dissipation in the IC and in the motor may be lowered by reducing IBS, so as to reduce the output (motor) current. Setting IBS to 75 mA will reduce the motor current, but will not reset the internal logic as described above. See Figure 13 for a suggested circuit.
The power dissipated by the MC3479 must be such that the junction temperature (TJ) does not exceed 150C. The power dissipated can be expressed as: P = (VM IM) + (2 IOD) [(VM - VOHD) + VOLD] where VM = Supply voltage; IM = Supply current other than IOD; IOD = Output current to each motor coil; VOHD = Driver output high voltage; VOLD = Driver output low voltage. The power supply current (IM) is obtained from Figure 8. After the power dissipation is calculated, the junction temperature can be calculated using: TJ = (P RqJA) + TA where RqJA = Junction-to-ambient thermal resistance (52C/W for the DIP, 72C/W for the FN Package); TA = Ambient Temperature.
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MC3479
0.8 70 60 I M (mA) 50 40 30 20 10 0 50 100 150 200 250 IBS (mA) 300 350 0 0 100 200 IOD (mA) 300 IOD = 0 VOLD (VOLTS) 0.6
0.4
0.2
Figure 8. Power Supply Current
Figure 9. Maximum Saturation Voltage - Driver Output Low
For example, assume an application where VM = 12 V, the motor requires 200 mA/coil, operating at room temperature with no heatsink on the IC. From Figure 11, IBS is determined to be 95 mA. RB is calculated: RB = (12 - 0.7) V/95 mA RB = 118.9 kW From Figure 8, IM (max) is determined to be 22 mA. From Figure 9, VOLD is 0.46 V, and from Figure 10, (VM - VOHD) is 1.4 volts. P = (12 0.022) + (2 0.2) (1.4 + 0.46) P = 1.01 W
2.0
TJ = (1.01 W 52C/W) + 25C TJ = 77.5C This temperature is well below the maximum limit. If the calculated TJ had been higher than 150C, a heatsink such as the Staver Co. V-7 Series, Aavid #5802, or Thermalloy #6012 could be used to reduce RqJA. In extreme cases, forced air cooling should be considered. The above calculation, and RqJA, assumes that a ground plane is provided under the MC3479 (either or both sides of the PC board) to aid in the heat dissipation. Single nominal width traces leading from the four ground pins should be avoided as this will increase TJ, as well as provide potentially disruptive ground noise and IR drops when switching the motor current.
140.00 120.00
[V - V M OHD] (VOLTS)
1.5
100.00 IBS (mA) 80.00 60.00 40.00 20.00
1.0
0.5
0 0 100 200 IOD (mA) 300
0.00 0.00
50.00
100.00
150.00 IOD (mA)
200.00 250.00
300.00
Figure 10. Maximum Saturation Voltage - Driver Output High
Figure 11. Bias/Set Current - Output Drive Current
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MC3479
+V +V 2.0 kW Typ Phase A Clock Digital Inputs CW/CCW Full/Half Step OIC 11 7 MC3479 10 9 L4 8 GND RB Set Normal Operation MC14049UB or equivalent 4 5 12 13 6 14 Bias/Set 2 15 L3 VM 16 1 1N5221A (3.0 V) VD 3 L2
L1 Motor
Figure 12. Typical Applications Circuit
MC3479 6 Bias/Set
RB Normal Operation Reduced Power MC14049UB or equivalent
RB1
- Suggested value for RB1 (VM = 12 V) is 150 kW. - RB calculation (see text) must take into account the current through RB1.
Figure 13. Power Reduction
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MC3479
PACKAGE DIMENSIONS
PDIP-16 CASE 648C-04 ISSUE D
A A
16 9
J
0.005 (0.13)
16X
B
L
M
TB
B M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 0.744 0.783 0.240 0.260 0.145 0.185 0.015 0.021 0.050 BSC 0.040 0.70 0.100 BSC 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.040 MILLIMETERS MIN MAX 18.90 19.90 6.10 6.60 3.69 4.69 0.38 0.53 1.27 BSC 1.02 1.78 2.54 BSC 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
1
8
F
DIM A B C D E F G J K L M N
N K C
E G
16X
T D
M
SEATING PLANE
0.005 (0.13)
TA
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MC3479/D

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