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| STD95NH02L N-CHANNEL 24V - 0.0039 - 80A DPAK ULTRA LOW GATE CHARGE STripFETTM MOSFET Table 1: General Features TYPE STD95NH02L s s s Figure 1: Package RDS(on) < 0.005 ID 80(*) A VDSS 24 V TYPICAL RDS(on) = 0.0039 @ 10 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 1 DESCRIPTION The STD95NH02L is based on the latest generation of ST's proprietary STripFETTM technology. An innovative layout enables the device to also exhibit extremely low gate charge for the most demanding requirements in high-frequency DC-DC converters. It's therefore ideal for high-density converters in Telecom and Computer applications. DPAK TO-252 (Suffix "T4") Figure 2: Internal Schematic Diagram APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS Table 2: Order Codes PART NUMBER STD95NH02LT4 MARKING D95NH02L PACKAGE DPAK PACKAGING TAPE & REEL Rev. 2 September 2004 1/11 STD95NH02L Table 3: Absolute Maximum ratings Symbol Vspike(1) VDS VDGR VGS ID (*) ID IDM (2) PTOT EAS (3) Tstg Tj Parameter Drain-source Voltage Rating Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 24 24 20 80 68 320 100 0.67 600 -55 to 175 Unit V V V V A A A W W/C mJ C (1) Garanted when external Rg = 4.7 and tf < tf max. (2) Pulse width limited by safe operating area. (3) Starting Tj = 25C, ID = 40A, VDD = 22V (*) Value limited by wires Table 4: Thermal Data Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1.5 100 275 C/W C/W C ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 250A VGS = 10 V, ID = 40 A VGS = 5 V, ID =40 A 1 0.0039 0.0055 0.005 0.009 Min. 24 1 10 100 Typ. Max. Unit V A A nA V 2/11 STD95NH02L ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic Symbol gfs (4) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Qoss (5) Qgls (6) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Output Charge Third-Quadrant Gate Charge Gate Input Resistance Test Conditions VDS = 10 V, ID = 10 A VDS = 15V, f = 1 MHz, VGS = 0 Min. Typ. 30 2070 990 90 20 110 47 20 17 7.6 6.8 22.6 15 1.8 Max. Unit S pF pF pF ns ns ns ns nC nC nC nC nC VDD = 12 V, ID = 40 A, RG= 4.7 VGS = 10 V (see Figure 16) VDD = 12 V, ID = 80 A, VGS = 5 V (see Figure 19) VDS = 19 V, VGS = 0 V VDS < 0 V, VGS = 5 V f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain Table 7: Source Drain Diode Symbol ISD ISDM VSD (4) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40A, VGS = 0 ISD = 80A, di/dt = 100 A/s, VDD =20 V, Tj = 150C (see Figure 16) 42 50.4 2.4 Test Conditions Min. Typ. Max. 80 320 1.3 Unit A A V ns nC A (4). Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (5). Qoss = Coss* Vin, Coss = Cgd+Cds. See Appendix A. (6). Gate charge for Syncronous Operation. 3/11 STD95NH02L Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/11 STD95NH02L Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature 5/11 STD95NH02L Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/11 STD95NH02L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0 o DIM. 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 inch MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 1.00 8 o TYP. TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 0.8 0.024 0 o 0.039 0o P032P_B 7/11 STD95NH02L DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix "T4")* REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 * on sales type 8/11 STD95NH02L Appendix A: Buck Converter Power Losses Estimation DESCRIPTION The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: - Very low RDS(on) to reduce conduction losses - Small Qgls to reduce the gate charge losses - Small Coss to reduce losses due to output capaci tance - Small Qrr to reduce losses on SW1 during its turn-on - The Cgd/C gs ratio lower than Vth /VGG ratio especially with low drain to source voltage to avoid the cross conduction phenomenon The high side (SW1) device requires: - Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate - Small Qg to have a faster commutation and to reduce gate charge losses - Low RDS(on) to reduce the conduction losses High Side Switch (SW1) Low Side Switch (SW2) Pconduction Pswitching RDS(on)SW1 I2 * *L RDS(on)SW2* I2 *(1- ) L Vin *(Qgsth(SW1)+ Qgd(SW1)) *f * IL Ig Zero Voltage Switching Pdiode Recovery Not Applicable 1 Vin * Qrr(SW2)*f Conduction Not Applicable Vf(SW2) * IL * t deadtime*f Qgls(SW2)* Vgg * f Vin *Qoss(SW2)*f 2 Pgate(Q ) G PQoss Qg(SW1)* Vgg * f Vin *Qoss(SW1)*f 2 Parameter Qgsth Qgls Pconduction Pswitching Pdiode Pdiode PQoss Meaning Duty-Cycle Post Threshold Gate Charge Third Quadrant Gate Charge On State Losses On-off Transition Losses Conduction and Reverse Recovery Diode Losses Gate Drive Losses Output Capacitance Losses 9/11 STD95NH02L Table 8: Revision History Date 27-Aug-2004 10-Sep-2004 Revision 1 2 Description of Changes First Release. Values changed in table 7 10/11 STD95NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 11/11 |
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