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(R)
MH89770
T1/ESF Framer & Interface Preliminary Information
Features
* * * * * * * * * * * * * * * * Complete interface to a bidirectional T1 link D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance improved to 156UI Insertion and detection of A, B, C, D bits Signalling freeze, optional debounce Selectable B8ZS, jammed bit (ZCS) or no zero code suppression Yellow and blue alarm signal capabilities Bipolar violation count, FT error count, CRC error count Frame and superframe sync. signals, Tx and Rx Per channel, overall, and remote loop around 8 kHz synchronization output Digital phase detector between T1 line and ST-BUS ST-BUS compatible Pin compatible with the MH89760BN/BS Inductorless clock recovery Loss of Signal (LOS) indication Available in standard, narrow and surface mount formats
MH89770N MH89770S
ISSUE 2
March 1995
Ordering Information
40 Pin DIL Hybrid 0.8" row pitch 40 Pin Surface Mount Hybrid
0C to 70C
Applications
* * * DS1/ESF digital trunk interfaces Computer to PBX interfaces (DMI and CPI) High speed computer to computer data links
Description
The MH89770 is a complete T1 interface solution, meeting the Extended Super Frame (ESF), D3/D4 and SLC-96 formats. The MH89770 interfaces to the DS1 1.544 Mbit/sec digital trunk and has the capability of meeting ACCUNET(R)1 T1.5 wander tolerance (138 UI). The MH89770 is a pin-compatible enhancement of the MH89760B.
1. ACCUNET (R) T1.5 is a registered trademark of AT & T.
TxSF C2i F0i RxSF DSTo DSTi CSTi0 CSTi1 CSTo
C1.5i ST-BUS Timing Circuitry Two Frame Elastic Buffer with Slip Control DS1 LINK INTERFACE 2048 - 1544 Converter Serial Control Interface Transmitter RxFDLClk RxFDL TxFDLClk TxFDL OUTA OUTB RxA RxT LOS RxR RxB
Data Interface
Receiver
ABCD Signalling RAM VDD XCtl XSt Control Logic Phase Detector
Clock Extractor DS1 Counter
E1.5o E8Ko VSS
Figure 1 - Functional Block Diagram
4-125
MH89770
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC LOS NC TxFDL NC TxFDLClk VSS RxFDLClk DSTo RxFDL OUTB C1.5i RxSF TxSF OUTA NC NC NC VSS
Preliminary Information
NC E1.5o VDD RxA RxT RxR RxB NC CSTi1 CSTi0 E8Ko XCtl XSt CSTo NC DSTi C2i E1.5o F0i
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 2 - Pin Connections
Pin Description
Pin # 2 3 4 5 6 7 8 9 10 11 12 Name NC E1.5o VDD RxA RxT RxR RxB NC CSTi1 CSTi0 E8Ko No Connection. 1.544 MHz Extracted Clock (Output): This clock is extracted by the device from the received DS1 signal. It is used internally to clock in data received at RxT and RxR. System Power Supply. +5V. Received A (Output): The bipolar DS1 signal received by the device at RxR and RxT is converted to a unipolar format and output at this pin. Receive Tip and Ring Inputs: Bipolar split phase inputs designed to be connected directly to the input transformer. Impedance to ground is approximately 1k. Impedance between pins=430. Received B (Output): The bipolar DS1 signal received by the device at RxR and RxT is converted to a unipolar format and output at this pin. No Connection. Control ST-BUS Input #1: A 2048 kbit/s serial control stream which carries 24 per-channel control words. Control ST-BUS Input #0: A 2048 kbit/s serial control stream that contains 24 per channel control words and two master control words. 8 kHz Extracted Clock (Output): This is an 8 kHz output generated by dividing the extracted 1.544 MHz clock by 193 and aligning it with the received DS1 frame. The 8 kHz signal can be used for synchronizing system clocks to the extracted 1.544 MHz clock. When digital loopback is enabled, the 8kHz is derived from C1.5. External Control (Output): This is an uncommitted external output pin which is set or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per frame. External Status (Schmitt Trigger Input): The state of this pin is sampled once per frame and the status is reported in bit 5 of Master Status Word 2 on CSTo. Control ST-BUS Output: This is a 2048 kbit/s serial control stream which provides the 24 per-channel status words, and two master status words. No Connection. Description
13
XCtl
14 15 16
XSt CSTo NC
4-126
Preliminary Information
Pin Description (Continued)
Pin # 17 18 Name DSTi C2i Description
MH89770
Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 24 PCM or data channels to be transmitted on the T1 trunk. 2.048 MHz System Clock (Input): This is the master clock for the ST-BUS section of the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the rising edge. 1.544 MHz Extracted Clock (Output): Internally connected to Pin 3. Frame Pulse Input: This is the frame synchronization signal which defines the beginning of the 32 channel ST-BUS frame. System ground. No Connection. Output A (Open Collector Output): This is the output of the DS1 transmitter circuit. It is suitable for use with an external pulse transformer to generate the transmit bipolar line signal. Transmit Superframe Pulse Input: A low pulse applied at this pin will determine the start of the next transmit superframe as illustrated in Figure 20. The device will free run if this pin is held high. Received Superframe Pulse Output: A pulse output on this pin indicates that the next frame of data on the ST-BUS is from frame 1 of the received superframe. The period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is synchronized to received DS1 signal. 1.544 MHz Clock Input: The rising edge of this clock is used to output data on OUTA, OUTB. C1.5i must be phase-locked to the C2i system clock. Output B (Open Collector Output): This is the output of the DS1 transmitter circuit. It is suitable for use with an external pulse transformer to generate the transmit bipolar line signal. Received Facility Data Link (Output): A 4 kbit/s serial output stream that is demultiplexed from the FDL bits in ESF mode, or the received F S bit pattern when in SLC96 mode. It is clocked out on the rising edge of RxFDLClk. Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 24 PCM or data channels received from the DS1 line. Receive Facility Data Link Clock Output: A 4 kHz clock used to output FDL information on RxFDL. Data is clocked out on the rising edge of the clock. No Connection. Transmit Facility Data Link Clock Output: A 4 kHz clock used to input FDL information on TxFDL. Data is clocked in on the rising edge of the clock. No Connection. Transmit Facility Data Link (Input): A 4 kbit/s serial input stream that is muxed into the FDL bits in the ESF mode, or the FS pattern when in SLC96 mode. It is clocked in on the rising edge of TxFDLClk. No Connection. Loss of Signal (Output): This pin goes high when 128 contiguous ZEROs are received on the RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is reset when 48 ones are received in a two T1-frame period. No Connection. No Connection.
4-127
19 20 21 22-24 25
E1.5o F0i VSS NC OUTA
26
TxSF
27
RxSF
28 29
C1.5i OUTB
30
RxFDL
31 32 33 34 35 36
DSTo RxFDLClk VSS TxFDLClk NC TxFDL
37 38
NC LOS
39 40
NC NC
4-128 6 7 8 X 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 10 11 12 X 13 14 15 16 X 17 18 19 20 X 21 22 23 24 X 25 26 27 28 X 29 30 31 5 6
DSTi
0 X
1
2
3
4 X
5
DS1
1
2
3
4
MH89770
ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED
6 7 8 X 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 9 10 11 12 X 13 14 15 16 X 17 18 19 20 X 21 22 23 24 X 25 26 27 28 X 29 30 31
DSTo
0 X 5 6
1
2
3
4 X
5
DS1
1
2
3
4
22
23
24
ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED
CSTi0 7 X 11 X 15 MC W1 19 X 23 X 13 14 15 16 17 18
0 1 2 PC PC PC CW CW CW 1 1 1 6 7 8 9 10 11 12
3 X
4 5 6 PC PC PC CW CW CW 1 1 1
8 9 10 PC PC PC CW CW CW 1 1 1
12 13 14 PC PC PC CW CW CW 1 1 1
16 17 18 PC PC PC CW CW CW 1 1 1
20 21 22 PC PC PC CW CW CW 1 1 1
24 25 26 PC PC PC CW CW CW 1 1 1 19 20 21
27 X
28 29 30 PC PC PC CW CW CW 1 1 1 22 23 24
31 MC W2
DS1
1
2
3
4
5
PCCW=Per Channel Control Word, MCW1/2=Master Control Word 1/2
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
CSTi1 7 X 11 X 15 X 8 9 10 PC PC PC CW CW CW 2 2 2 12 13 14 PC PC PC CW CW CW 2 2 2 16 17 18 PC PC PC CW CW CW 2 2 2 13 14 15 10 11 12 7 8 9
0 1 2 PC PC PC CW CW CW 2 2 2 6
3 X
4 5 6 PC PC PC CW CW CW 2 2 2
19 X
20 21 22 PC PC PC CW CW CW 2 2 2 16 17 18
23 X
24 25 26 PC PC PC CW CW CW 2 2 2 19 20 21
27 X
28 29 30 PC PC PC CW CW CW 2 2 2 22 23 24
31 X
DS1
1
2
3
4
5
PCCW=Per Channel Control Word
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
7 X 7 8 9 10 11 8 9 10 PCS PCS PCS W W W 11 X 15 12 13 14 16 17 18 PCS PCS PCS MS PCS PCS PCS W W W W1 W W W 12 13 14 15 19 X 20 21 22 PCS PCS PCS W W W 16 17 18 23 X 24 25 26 PCS PCS PCS W W W 19 20 21 27 X 31 28 29 30 PCS PCS PCS MS W W W W2 22 23 24
CSTo
3 0 1 2 PCS PCS PCS PS W W WW 6
4 5 6 PCS PCS PCS W W W
DS1
1
2
3
4
5
PCSW=Per Channel Status Word, PSW=Phase Status Word, MSW=Master Status Word
ST-BUS VERSUS DS1 CHANNEL STATUS Figure 3 - ST-BUS Channel Allocations
Preliminary Information
X = UNUSED
Preliminary Information
Functional Description
The MH89770 is a thick film hybrid solution for a T1 interface. All of the formatting and signalling insertion and detection is done by the device. Various programmable options in the device include: ESF, D3/D4 or SLC-96 mode, common channel or robbed bit signalling, zero code suppression, alarms, and local and remote loopback. The MH89770 also has built in bipolar line drivers and receivers and a clock extraction circuit. All data and control information is communicated to the MH89770 via 2048 kbit/s serial streams conforming to Mitel's ST-BUS format. The ST-BUS is a TDM serial bus that operates at 2048 kbits/s. The serial streams are divided into 125 sec frames that are made up of 32 8-bit channels. A serial stream that is made up of these 32 8 bit channels is known as an ST-BUS stream, and one of these 64 kbit/s channels is known as an ST-BUS channel. The system side of the MH89770 is made up of ST-BUS inputs and outputs, i.e., control inputs and outputs (CSTi/o) and data inputs and outputs (DSTi/o). These signals are functionally represented in Figure 32. The DS1 line side of the device is made up of split phase inputs (RxT, RxR) and outputs (OUTA, OUTB) which can be connected to line coupling transformers. Functional transmit and receive timing is shown in Figures 33 and 34. Data for transmission on the DS1 line is clocked serially into the device at the DSTi pin. The DSTi pin accepts a 32 channel time division multiplexed ST-BUS stream. Data is clocked in with the falling edge of the C2i clock. ST-BUS frame boundaries are defined by the frame pulse applied at the F0i pin. Only 24 of the available 32 channels on the ST-BUS serial stream are actually transmitted on the DS1 side. The unused 8 channels are ignored by the device. Data received from the DS1 line is clocked out of the device in a similar manner at the DSTo pin. Data is clocked out on the rising edge of the C2i clock. Only 24 of the 32 channels output by the device contain the information from the DS1 line. The DSTo pin is, however, actively driven during the unused channel timeslots. Figure 3 shows the correspondence between the DS1 channels and the ST-BUS channels. All control and monitoring of the device is accomplished through two ST-BUS serial control
MH89770
inputs and one serial control output. Control ST-BUS input number 0 (CSTi0) accepts an ST-BUS serial stream which contains the 24 per channel control words and two master control words. The per channel control words relate directly to the 24 information channels output on the DS1 side. The master control words affect operation of the whole device. Control ST-BUS input number 1 (CSTi1) accepts an ST-BUS stream containing the A, B, C and D signalling bits. The relationship between the CSTi channels and the controlled DS0 channels is shown in Figure 3. Status and signalling information is received from the device via the control ST-BUS output (CSTo). This serial output stream contains two master status words, 24 per channel status words and one Phase Status Word. Figure 3 shows the correspondence between the received DS1 channels and the status words. Detailed information on the operation of the control interface is presented below.
Programmable Features
The main features in the device are programmed through two master control words which occupy channels 15 and 31 in Control ST-BUS input stream number 0 (CSTi0). These two eight bit words are used to: * * Select the different operating modes of the device ESF, D3/D4 or SLC-96. Activate the features that are needed in a certain application; common channel signalling, zero code suppression, signalling debounce, etc. Turn on in service alarms, diagnostic loop arounds, and the external control function
*
Tables 1 and 2 contain a complete explanation of the function of the different bits in Master Control Words 1 and 2.
Major Operating Modes
The major operating modes of the device are enabled by bits 2 and 4 of Master Control Word 2. The Extended Superframe (ESF) mode is enabled when bit 4 is set high. Bit 2 has no effect in this mode. The ESF mode enables the transmission of the S bit pattern shown in Table 3. This includes the frame/superframe pattern, the CRC-6, and the Facility Data Link (FDL). The device generates the frame/multiframe pattern and calculates the CRC for each superframe. The data clocked into the device on the TxFDL pin is incorporated into the FDL. ESF mode will also insert A, B, C and D signalling bits into the 24 frame multiframe. The DS1 frame begins after
4-129
MH89770
Bit 7 Name Debounce Description
Preliminary Information
.
When set the received A, B, C and D signalling bits are reported directly in the per channel status words output at CSTo. When clear, the signalling bits are debounced for 6 to 9 ms before they are placed on CSTo. Transparent Zero Code Suppression. When this bit is set, no zero code suppression is implemented. Binary Eight Zero Suppression. When this bit is set, B8ZS zero code suppression is enabled. When clear, bit 7 in data channels containing all zeros is forced high before being transmitted on the DS1 side. This bit is inactive if the TSPZCS bit is set. 8 kHz Output Select. When set, the E8Ko pin is held high. When clear, the E8Ko generates an 8 kHz output derived from the extracted 1.544 MHz clock or C1.5i clock (see Pin Description for E8Ko). External Control Pin. When set, the XCtl pin is held high. When clear, XCtl is held low. ESF Yellow Alarm. Valid only in ESF mode. When set, a sequence of eight 1's followed by eight 0's is sent in the FDL bit positions. When clear, the FDL bit contains data input at the TxFDL pin. When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When clear, A, B, C and D signalling bits are inserted into bit position 8 of all DS0 channels in every 6th frame. Yellow Alarm. When set, bit 2 of all DS0 channels is set low. When clear, bit 2 operates normally. Table 1. Master Control Word 1 (Channel 15, CSTi0) Description Remote Loopback. When set, the data received at RxR and RxT is looped back to OUTB and OUTA respectively. The data is clocked into the device with the extracted 1.544 MHz clock. The device still monitors the received data and outputs it at DSTo. The device operates normally when the bit is clear. Digital Loopback. When set, the data input on DSTi is looped around to DSTo. The normal received data on RxR and RxT is ignored. However, the data input at DSTi is still transmitted on OUTA and OUTB. The device frames up on the looped data using the C1.5i clock. All One's Alarm. When set, the chip transmits an unframed all 1's signal on OUTA and OUTB. ESF/D4 Select. When set, the device is in ESF mode. When clear, the device is in D3/D4 mode. Reframe. If set for at least one frame and then cleared, the chip will begin to search for a new frame position. Only the change from high to low will cause a reframe, not a continuous low level. SLC-96 Mode Select. The chip is in SLC-96 mode when this bit is set. This enables input and output of the FS bit pattern using the same pins as the facility data link in ESF mode. The chip will use the same framing algorithm as D3/D4 mode. The user must insert the valid FS bits in 2 out of 6 superframes to allow the receiver to find superframe sync, and the transmitter to insert A and B bits in every 6th frame. The SLC-96 FDL completely replaces the FS pattern in the outgoing S bit position. Inactive in ESF mode. In ESF mode, when set, the chip disregards the CRC calculation during synchronization. When clear, the device will check for a correct CRC before going into synchronization. In D3/D4 mode, when set, the device will synchronize on the first correct S-bit pattern detected. When this bit is clear, the device will not synchronize if it has detected more than one candidate for the frame alignment pattern (i.e., a mimic). Maintenance Mode. When set, the device will declare itself out-of-sync if 4 out of 12 consecutive FT bits are in error. When clear, the out-of-sync threshold is 2 errors in 4 FT bits. In this mode, four consecutive bits following an errored FT bit are examined. Table 2. Master Control Word 2 (Channel 31, CSTi0)
6 5
TSPZCS B8ZS
4
8kHSel
3 2
XCtl ESFYLW
1
Robbed bit
0
YLALR
Bit 7
Name RMLOOP
6
DGLOOP
5 4 3
ALL1'S ESF/D4 ReFR
2
SLC-96
1
CRC/MIMIC
0
Maint.
4-130
Preliminary Information
approximately 25 periods of the C1.5i clock from the F0i frame pulse. Frame # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FPS FDL X X 0 X CB2 X 0 X CB3 X 1 X CB4 X 0 X CB5 X 1 X CB6 X 1 D Table 3. ESF Frame Pattern C B A CRC CB1 Signalling
MH89770
FPS) exceed the threshold set with bit 0 in Master Control Word 2. Frame # 1 2 3 4 5 6 7 8 9 10 11 12 FT 1 0 0 1 1 0 1 1 1 0 0 B Table 4. D3/D4 Framer A FS 0 Signalling
These signalling bits are only valid if the robbed bit signalling is active.
Standard D3/D4 framing is enabled when bit 4 of Master Control Word 2 is reset (logic 0). In this mode the device searches for and inserts the framing pattern shown in Table 4. This mode only supports AB bit signalling, and does not contain a CRC check. The CRC/MIMIC bit in Master Control Word 2, when set high, allows the device to synchronize in the presence of a mimic. If this bit is reset, the device will not synchronize in the presence of a mimic. (Also refer to section on Framing Algorithm.) In the D3/D4 mode the device can also be made compatible with SLC-96 by setting bit two of Master Control Word 2. This allows the user to insert and extract the signalling framing pattern on the DS1 bit stream using the FDL input and output pins. The user must format this 4 kbits of information externally to meet all of the requirements of the SLC-96 specification (see Table 5). The device multiplexes and demultiplexes this information into the proper position. This mode of operation can also be used for any other application that uses all or part of the signalling framing pattern. As long as the serial stream clocked into the TxFDL contains two proper sets of consecutive synchronization bits (as shown in Table 5 for frames 1 to 24), the device will be able to insert and extract the A, B signalling bits. The TxSF pin should be held high in this mode. Superframe boundaries cannot be defined by a pulse on this input. The RxSF output functions normally and indicates the superframe boundaries based on the synchronization pattern in the FS received bit position.
These signalling bits are only valid if the robbed bit signalling is active.
During synchronization the receiver locks on to the incoming frame, calculates the CRC and compares it to the CRC received in the next multiframe. The device will not declare itself to be in synchronization unless a valid framing pattern in the S-bit is detected and a correct CRC is received. The CRC check in this case provides protection against false framing. The CRC check can be turned off by setting bit 1 in Master Control Word 2. The device can be forced to resynchronize itself. If Bit 3 in Master Control Word 2 is set for one frame and then subsequently reset, the device will start to search for a new frame position. The decision to reframe is made by the user's system processor on the basis of the status conditions detected in the received master status words. This may include consideration of the number of errors in the received CRC in conjunction with an indication of the presence of a mimic. When the device attains synchronization the mimic bit in Master Status Word 1 is set if the device found another possible candidate when it was searching for the framing pattern. Note that the device will resynchronize automatically if the errors in the terminal framing pattern (FT or
4-131
MH89770
Frame # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FT 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 X 0 X 1 X 0 X 1 X 0 X FS Frame FT # 37 1 38 39 0 40 41 1 42 43 0 44 45 1 46 47 0 Resynchronization 48 Data 49 1 Bits 50 51 0 52 53 1 54 55 0 56 57 1 58 59 0 60 61 1 62 63 0 64 65 1 X =Concentrator 66 Field Bits 67 0 68 69 1 70 71 0 72 Table 5. SLC-96 Framing Pattern Notes
Preliminary Information
FS X X X X X S S S C C C A A L L L L S S = Spoiler Bits L = Line Switch Field Bits A = Alarm Field Bits C = Maintenance Field Bits S = Spoiler Bits X = Concentrator Field Bits
Notes
Note: The FS pattern has to be supplied by the user.
DATA
B B8ZS
0
0
0
V B
0 V
B B V = Violation B = Bipolar 0 = No Pulse
0 B8ZS B
0
0 V
B
0
V B
B
Figure 4 - B8ZS Output Coding
4-132
Preliminary Information
Zero Code Suppression
The combination of bits 5 and 6 in Master Control Word 1 allow one of three zero code suppression schemes to be selected. The three choices are: none, binary 8 zero suppression (B8ZS), or jammed bit (bit 7 forced high). No zero code suppression allows the device to interface with systems that have already applied some form of zero code suppression to the data input on DSTi. B8ZS zero code suppression replaces all strings of 8 zeros with a known bit pattern and a specific pattern of bipolar violations. This bit pattern and violation pattern is shown in Figure 4. The receiver monitors the received bit pattern and the bipolar violation pattern and replaces all matching strings with 8 zeros.
MH89770
is no transmission line or when there is a suspected failure of the line. The all ones transmit alarm (also known as the blue alarm or the keep alive signal) can be activated in conjunction with the digital loop around so that the transmission line sends an all 1's signal while the normal data is looped back locally. The MH89770 also has a per channel loopback mode. See Table 6 and the following section for more information.
Per Channel Control Features
In addition to the two master control words in CSTi0 there are also 24 Per Channel Control Words. These control words only affect individual DS0 channels. The correspondence between the channels on CSTi0 and the affected DS0 channel is shown in Fig. 3. Each control word has three bits that enable robbed bit signalling, DS0 channel loopback and inversion of the DS0 channel. A full description of each of the bits is provided in Table 6. Transmit Signalling Bits Control ST-BUS input number 1 (CSTi1) contains 24 additional per channel control words. These 24 ST-BUS channels contain the A, B, C and D signalling bits that the device uses at transmit time. The position of these 24 per channel control words in the ST-BUS is shown in Figure 3 and the position of the ABCD signalling bits is shown in Table 7. Even though the device only inserts the signalling Description
Loopback Modes
Remote and digital loopback modes are enabled by bits 6 and 7 in Master Control Word 2. These modes can be used for diagnostics in locating the source of a fault condition. Remote loop around loops back data received at RxR and RxT back out on OUTA and OUTB, thus effectively sending the received DS1 data back to the far end unaltered so that the transmission line can be tested. The received signal with the appropriate received channels on the DS1 side made available in the proper format at DSTo. The digital loop around mode diverts the data received at DSTi back out the DSTo pin. Data received on DSTi is, however, still transmitted out via OUTA and OUTB. This loop back mode can be used to test the near end interface equipment when there
Bit 7-3 2
Name IC Polarity
Internal Connections. Must be kept at 0 for normal operation. When set, the applicable channel is not inverted on the transmit or the receive side of the device. When clear, all the bits within the applicable channel are inverted both on transmit and receive side. Per Channel Loopback. When set, the received DS0 channel is replaced with the transmitted DS0 channel. Only one DS0 channel may be looped back in this manner at a time. The transmitted DS0 channel remains unaffected. When clear the transmit and receive DS0 sections operate normally. Data Channel Enable. When set, robbed bit signalling for the applicable channel is disabled. When clear, every 6th DS1 frame is available for robbed bit signalling. This feature is enabled only if bit 1 in Master Control Word is low. Table 6. Per Channel Control Word 1 Input at CSTi0 Description Keep at 0 for normal operation These are the 4 signalling bits inserted in the appropriate channels of the DS1 stream being output from the chip, when in ESF mode. In D3/D4 modes where there are only two signalling bits, the values of C and D are ignored. Table 7. Per Channel Control Word 2 Input at CSTi1
4-133
1
Loop
0
Data
Bit 7-4 3 2 1-0
Name Unused A B C, D
MH89770
Bit 7 6 5 Name YLALR MIMIC ERR Description
Preliminary Information
.
Yellow Alarm Indication. This bit is set when the chip is receiving a 0 in bit position 2 of every DS0 channel. This bit is set if the frame search algorithm found more than one possible frame candidate when it went into frame synchronization. Terminal Framing Bit Error. The state of this bit changes every time the chip detects 4 errors in the FT or FPS bit pattern. The bit will not change state more than once every 96ms. ESF Yellow Alarm. This bit is set when the device has observed a sequence of eight one's and eight 0's in the FDL bit positions. Multiframe Synchronization. This bit is cleared when D3/D4 multiframe synchronization has been achieved. Applicable only in D3/D4 and SLC-96 modes of operation. Bipolar Violation Count. The state of this bit changes every time the device counts 256 bipolar violations. Slip Indication. This bit changes state every time the elastic buffer in the device performs a controlled slip. Synchronization. This bit is set when the device has not achieved synchronization. The bit is clear when the device has synchronized to the received DS1 data stream. Table 8. Master Status Word 1 (Channel 15, CSTo) Description Blue Alarm. This bit is set if the receiver has detected two frames of 1's and an out of frame condition. It is reset by any 250 microsecond interval that contains a zero. Frame Count. This is the ninth and most significant bit of the "Phase Status Word" (see Table 10). If the phase status word is incrementing, this bit will toggle when the phase reading exceeds channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the reading goes below channel 0, bit 0. External Status. This bit reflects the state of the external status pin (XSt). The state of the XSt pin is sampled once per frame. Bipolar Violation Count. These two bits change state every 128 and every 64 bipolar violations, respectively. CRC Error Count. These three bits count received CRC errors. The counter will reset to zero when it reaches terminal count. Valid only in ESF mode. Table 9. Master Status Word 2 (Channel 31, CSTo) Description Channel Count. These five bits indicate the ST-BUS channel count between the ST-BUS frame pulse and the rising edge of E8Ko. Bit Count. These three bits provide one bit resolution within the channel count described above. Table 10. Phase Status Word (Channel 3, CSTo) Operating Status Information Status Information regarding the operation of the device is output serially via the Control ST-BUS output (CSTo). The CSTo serial stream contains Master Status Words 1 and 2, 24 Per Channel Status Words, and a Phase Status Word. The Master Status Words contain all of the information needed to determine the state of the interface and how well it is operating. The information provided includes frame and super frame synchronization, slip, bipolar
4 3
ESFYLW MFSYNC
2 1 0
BPV SLIP SYN
Bit 7 6
Name BlAlm FrCnt
5 4-3 2-0
XSt BPVCnt CRCCNT
Bit 7-3 2-0
Name ChannelCnt BitCnt
information in every 6th DS1 frame this information must be input every ST-BUS frame. Robbed bit signalling can be disabled for all channels on the DS1 link by bit 1 of Master Control Word 1. It can also be disabled on a per channel basis by bit 0 in the Per Channel Control Word 1.
4-134
Preliminary Information
Bit 7-4 3 2 1 0 Name Unused A B C D Unused Bits. Will be output as 0's. Description
MH89770
.
These are the 4 signalling bits as extracted from the received DS1 bit stream. The bits are debounced for 6 to 9 ms if the debounce feature is enabled via bit 7 in Master Control Word 1. Table 11. Per Channel Status Word Output on CSTo
violation counter, alarms, CRC error count, FT error count, synchronization pattern mimic and a phase status word. Tables 8 and 9 give a description of each of the bits in Master Status Words 1 and 2, and Table 10 gives a description of the Phase Status Word. In addition, the MH89770 has a Loss of Signal (LOS) pin that is set High when 128 consecutive ZEROs are received. While LOS is set High, RxA and RxB are forced High. The LOS signal goes Low when a ONEs density on 12.5% of the bits (equivalent to 48 bits) occurs in a two DS1 frame period. Alarm Detection The device detects the yellow alarm for both D3/D4 frame format and ESF format. The D3/D4 yellow alarm will be activated if a `0' is received in bit position 2 of every DS0 channel for 600 msec. It will be released in 200 msec after the contents of the bit change. The alarm is detectable in the presence of errors on the line. The ESF yellow alarm will become active when the device has detected a string of eight 0's followed by eight 1's in the facility data link. It is not detectable in the presence of errors on the line. This means that the ESF yellow alarm will drop out for relatively short periods of time, so the system will have to integrate the ESF yellow alarm. The blue alarm signal, in Master Status Word 2, will also drop out if there are errors on the line.
received signal. It has a maximum refresh time of 96 ms. This means that the bit can not change state faster than once every 96 ms. For example, if there are 256 violations in 80 ms the BPV bit will not change state until 96 ms. Any more errors in that extra 16 ms are not counted. If there are 256 errors in 200 ms then the BPV bit will change state after 200 ms. In practical terms this puts an upper limit on the error rate that can be calculated from the BPV information, but this rate (1.7 X 10-3) is well above any normal operating condition. Bits 4 and 3 also provide bipolar violations infor-mation. Bit 4 will change state after 128 violations. Bit 3 changes state after 64 bipolar violations. These bits are refreshed independently and are not subject to the 96 ms refresh rate described above.
DS1/ST-BUS Phase Difference
An indication of the phase difference between the ST-BUS and the DS1 frame can be ascertained from the information provided by the eight bit Phase Status Word and the Frame Count bit. Channel three on CSTo contains the Phase Status Word. Bits 7-3 in this word indicate the number of ST-BUS channels between the ST-BUS frame pulse and the rising edge of the E8Ko signal. The remaining three bits provide one bit resolution within the channel count indicated by bits 7-3. The frame count bit in Master Status Word 2 is the ninth and most significant bit of the phase status word. It will toggle when the phase status word increments above channel 31, bit 7 or decrements below channel 0, bit 0. The E8Ko signal has a specific relationship with received DS1 frame. The rising edge of E8Ko occurs during bit 2, channel 17 of the received DS1 frame. The Phase Status Word in conjunction with the frame count bit, can be used to monitor the phase relationship between the received DS1 frame and the local ST-BUS frame. The local 2.048 MHz ST-BUS clock must be phase-locked to the 1.544 MHz clock extracted from the received data. When the two clocks are not phase-locked, the input data rate on the DS1 side will differ from the output data rate on the ST-BUS side. If the average input data rate is higher than the
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Mimic Detection
The mimic bit in Master Status Word 1 will be set if, during synchronization, a frame alignment pattern (FT or FPS bit pattern) was observed in more than one position, i.e., if more than one candidate for the frame synchronization position was observed. It will be reset when the device resynchronizes. The mimic bit, the terminal framing error bit and the CRC error counter can be used separately or together to decide if the receiver should be forced to reframe.
Bipolar Violation Counter
The Bipolar Violation bit in Master Status Word 1 will toggle after 256 violations have been detected in the
MH89770
average output data rate, the channel count and bit count in the phase status word will be seen to decrease over time, indicating that the E8Ko rising edge, and therefore the DS1 frame boundary is moving with respect to the ST-BUS frame pulse. Conversely, a lower average input data rate will result in an increase in the phase reading. In an application where it is necessary to minimize jitter transfer from the received clock to the local system clock, a phase lock loop with a relatively large time constant can be implemented using information provided by the phase status word. In such a system, the local 2.048 MHz clock is derived from a precision VCO. Frequency corrections are made on the basis of the average trend observed in the phase status word. For example, if the channel count in the phase status word is seen to increase over time, the feedback applied to the VCO is used to decrease the system clock frequency until a reversal in the trend is observed. The elastic buffer in the MT8977 permits the device to handle 26 ST-BUS channels or 156 UI of jitter/ wander (see description of elastic buffer in the next section). In order to prevent slips from occurring, the frequency corrections would have to be implemented such that the deviation in the phase status word is limited to 26 channels peak-to-peak. It is possible to use a more sophisticated protocol, which would center the elastic buffer and permit more jitter/wander to be handled. However, for most applications, including ACCUNET(R) T1.5 (138 UI), the 156 UI of jitter/wander tolerance is acceptable.
Preliminary Information
a random transition stage until the device attains multiframe synchronization.
Clock and Framing Signals
The MH89770 has a built in clock extraction circuit which creates a 1.544 MHz clock synchronized to the received DS1 signal. This clock is used internally by the MH89770 to clock in data received on RxT and RxR, and is also output at the E1.5o pin. The circuit has been designed to operate within the constraints imposed by the minimum 1's density requirements, typically specified for T1 networks (maximum of 15 consecutive 0's). The extracted clock is internally divided by 193 and aligned with the received DS1 frame. The resulting 8 kHz signal is output at the E8Ko pin and can be used to phase lock the local system C2 and the transmit C1.5 clocks to the extracted clock. The MH89770 requires three clock signals which have to be generated externally. The ST-BUS interface on the device requires a 2.048 MHz signal which is applied at the C2i pin and an 8 kHz framing signal applied at the F0i pin. The framing signal is used to delimit individual ST-BUS frames. Figure 19 illustrates the relationship between the C2i and F0i signals. The F0i signal can be derived from the 2.048 MHz C2 clock. The transmit side of the DS1 interface requires a 1.544 MHz clock applied at C1.5i. The C1.5 and C2 clocks must be phase locked. There must be 193 clock cycles of the C1.5 clock for every 256 cycles of the C2 clock in order for the 2.048 to 1.544 rate converter to function properly. MT8941
DPLL #1 F0i C12i MS1 DPLL #2 C8Kb C16i MS0 5V Ai MS2 MS3 Yo Bi F0b C4b C2o ENC4o ENC2o F0i C4i C2i +5V CVb ENCv C1.5 +5V
Received Signalling Bits
The A, B, C and D signalling bits are output from the device in the 24 Per Channel Status Words. Their location in the serial steam output at CSTo is shown in Figure 3 and the bit positions are shown in Table 11. The internal debouncing of the signalling bits can be turned on or off by Master Control Word 1. In ESF mode, A, B, C and D bits are valid. Even though the signalling bits are only received once every six frames the device stores the information so that it is available on the ST-BUS every frame. The ST-BUS will always contain the most recent signalling bits. The state of the signalling bits is frozen if synchronization is lost. In D3/D4 mode, only the A and B bits are valid. The state of the signalling bits is frozen when terminal frame synchronization is lost. The freeze is disabled when the device regains terminal frame synchronization. The signalling bits may go through
Figure 5 - MT8941 Clock Generator
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Preliminary Information
MH89770
MH89770
OUTA +12V Transmit Data L2 C2 OUTB 1:
TR1
MH89761 EIT R1 :0.5 L1 C1 S1 S2 S3 S4 S5 S6 S7 EIR TxT TxR EA EB EC SW RCLT RCHT RCLR RCHR Ti Ri
1:
TL RL
E1.5o
RxA RxB RxT 1: :1 1: RxR TR2
Extracted Clock Received Data
Rx Line Receiver
+5V VDD
S1 S2 S4 S4 S5 S6 S7 COMPONENT VALUES: R1 = 150 1% 1 W 4 C1 = 0.01 F 5% 250V C2 = 0.47 F 5% 100V L1 = 33 H 130mA L2 = 33 H 165 mA TR1 = 1:1:0.5 Filtran* Part # TFS2573 TR2 = 1:1:1 Filtran* Part # TFS2574 *Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 613-226-1626
0-150' CLOSE OPEN OPEN OPEN OPEN OPEN OPEN
150-450' OPEN CLOSE OPEN CLOSE OPEN CLOSE OPEN
450-655' OPEN OPEN CLOSE OPEN CLOSE OPEN CLOSE
Equalizer settings
Note: The equalizer has been optimized for 22 gauge ABAM cable. The exact distances may vary with the type of cable and the output transformer. Different line length settings may be required if a transformer other than the Filtran TFS2573 is used.
Figure 6 - Input/Output Configuration
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MH89770
In synchronous operation the slave end of the link must have its C2 and C1.5 clocks phase locked to the extracted clock. In plesiochronous clocking applications where the master and slave end are operating under controlled slip conditions, phase locking to the extracted clock is generally not required. Mitel's MT8941 Digital Phase Lock Loop (DPLL) can be used to generate all timing signals required by the MH89770. The MT8941 has two DPLLs built into the device. Figure 5 shows how DPLL #1 can be set up to generate the C1.5 clock phase locked to the F0i which in turn is derived from the same source as the C2 clock. Figure 5 also shows how DPLL #2 is set up to generate the ST-BUS clocks that are phase locked to the received data rate. If E8Ko from the MH89770 is connected to the C8Kb input on the MT8941, DPLL #2 in the device will generate the ST-BUS clocks that are phase locked to the T1 line.
Preliminary Information
detailed transformer specification is presented in the applications section of this data sheet. To complete the interfaces to the transmit line, a pre-equalizer and line impedance matching network is required. The pulse output at the transformer secondary must be pre-equalized to drive different lengths of cable. Mitel`s MH89761 T1 Equalizer is configurable to provide pre-emphasis for 0-150, 150-450 and 450-655 foot lengths of 22 AWG transmission line. A separate 6dB pad is also provided on the MH89761 for use in implementing external looparound. Both circuits have input and output impedance of 100. Figure 6 shows how the equalizer is connected in a typical application. (Refer to the MH89761 data sheet for more details.)
Line Receiver
The bipolar receiver inputs on the device, RxT and RxR, are intended to be coupled to the line through a center tapped pulse transformer as shown in Figure 6. The device presents a 400 impedance to the receive transformer to permit matching to 100 twisted pair cable. The signal detect threshold level of the receiver circuit is set at approximately 1.5V. There is no equalization of the received signal. The receiver circuit is designed to accurately decode a signal attenuated by a maximum of 3 dB from the digital crossconnect point. The MH89770 is not designed to directly accept a signal from the last network repeater. Interface to the public network generally requires a Channel Service Unit (CSU). The receiver decodes the bipolar signal into a split phase unipolar return to zero format. The two resulting unipolar signals are used for bipolar violation detection within the device and are also output at RxA and RxB. The input jitter tolerance of the MH89770 is shown in Figure 7.
DS1 Line Interface Line Transmitter
The transmit line interface is made up of two open collector drivers (OUTA and OUTB) that can be coupled to the line with a center tapped pulse transformer (see Figure 6). A step function is applied to the transformer when either of the transistors is turned on. By operating in the transient portion of the inductance response, the secondary of the transformer produces an almost square pulse. The capacitor and inductor on the center tap of the transmit transformer shown in Figure 6 suppress transients in the 12 volt supply. The series RLC across the output of the transformer shape the pulse to meet the AT & T or CCITT pulse templates. A
Write Pointer 60 CH
13 CH
2 CH
Wander Tolerance
47 CH
386 Bit Elastic Store
15 CH
-13 CH
34 CH
28 CH
Figure 7 - Elastic Buffer Functional Diagram (156 UI Wander Tolerance)
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Preliminary Information
Elastic Buffer
The MH89770 has a two frame elastic buffer which absorbs jitter in the received DS1 signal. The buffer is also used in the rate conversion between the 1.544 Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS data rate. The received data is written into the elastic buffer with the extracted 1.544 MHz clock. The data is read out of the buffer on the ST-BUS side with the system 2.048 MHz clock. The maximum delay through the buffer is 1.875 ST-BUS frames or 60 ST-BUS channels, see Figure 7. The minimum delay required to avoid bus contention in the buffer memory is two ST-BUS channels. Under normal operating conditions, the system C2i clock is phase locked to the extracted E1.5o clock using external circuitry. If the two clocks are not phase-locked, then the rate at which the data is being written into the device on the DS1 side may differ from the rate at which it is being read out on the ST-BUS side. The buffer circuit will perform a controlled slip if the throughput delay conditions described above are violated. For example, if the data on the DS1 side is being written in at a rate slower than what it is being read out on the ST-BUS side, the delay between the received DS1 write pointer and the ST-BUS read pointer will begin to decrease over time. When this delay approaches the minimum two channel threshold, the buffer will perform a controlled slip which will reset the internal ST-BUS read pointers so that there is exactly 34 channels delay between the two pointers. This will result in some ST-BUS channels containing information output in the previous frame. Repetition of up to one DS1 frame of information is possible. Conversely, if the data on the DS1 side is being written into the buffer at a rate faster than it is being read out on the ST-BUS side, the delay between the DS1 frame and the ST-BUS frame will increase over time. A controlled slip will be performed when the throughput delay exceeds 60 ST-BUS channels. This slip will reset the internal ST-BUS counters so that there is a 28 channel delay between the DS1 write pointer and the ST-BUS read pointer, resulting in loss of up to one frame of received DS1 data. Figure 7 illustrates the relationship between the read and write pointers of the receive elastic buffer. Measuring clockwise from the write pointer, if the read pointer comes within two channels of the writer pointer a frame slip will occur, which will put the read pointer 34 channels from the write pointer. Conversely, if the read pointer moves more than 60 channels from the write pointer, a slip will occur,
MH89770
which will put the read pointer 28 channels from the write pointer. This provides a worst case hysteresis of 13 ST-BUS channels peak (26 ST-BUS channels peak-to-peak). This can be translated into a low frequency jitter (wander) tolerance value, accounting for the DS1 to ST-BUS rate conversion, as follows: (1.544/2.048) X 26 X 8 = 156 UI pp. There is no loss of frame sync, multiframe sync or any errors in the signalling bits when the device performs a slip. The information on the FDL pins in ESF or SLC-96 mode will, however, undergo slips at the same time.
Framing Algorithm
A state diagram of the framing algorithm is shown in Figure 8. The dotted lines show which feature can be switched in and out depending upon the operating mode of the device. In ESF mode, the framer searches for the FPS bits. Once this pattern is detected and verified, bit 0 in Master Status Word 1 is cleared. When the device is operating in the D3/D4 format, the framer searches for the FT pattern, i.e., a repeating 1010... pattern in a specific bit position every alternate frame. It will synchronize to this pattern and declare valid terminal frame synchronization by clearing bit 0 in Master Status Word 1. The device will subsequently initiate a search for the FS pattern to locate the signalling frames (see Figure 21). When a correct FS pattern has been located, bit 3 in Master Status Word 1 is cleared indicating that the device has achieved multiframe synchronization. Note: the device will remain in terminal frame synchronization even if no FS pattern can be located. In D3/D4 format, when the CRC/MIMIC bit in Master Control Word 1 is cleared, the device will not go into synchronization if more than one bit position in the frame has a repeating 1010.... pattern, i.e., if more than one candidate for the terminal framing position is located. The framer will continue to search until only one terminal framing pattern candidate is discovered. It is, therefore, possible that the device may not synchronize at all in the presence of PCM code sequences (e.g., sequences generated by some types of test signals) which contain mimics of the terminal framing pattern.
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MH89770
Preliminary Information
False Candidate Hunt Mode
Candidate
False Candidate
Forced Reframe False Candidate
Out of Sync.
Verify
Candidate Candidate CRC Check
*
Candidate In sync Maintenance Valid Candidate
Valid Candidate New Frame Position Resync Receiver
* Note: Only when in ESF mode and CRC option is enabled.
Figure 8 - Off-Line Framer State Diagram
Setting CRC/MIMIC bit high will force the framer to synchronize to the first terminal framing pattern detected. In standard D3/D4 applications, the user's system software should monitor the multiframe synchronization state indicated by bit 3 in Master Status Word 1. Failure of the device to achieve multiframe synchronization within 4.5ms of terminal frame synchronization, is an indication that the device has framed up to a terminal framing pattern mimic and should be forced to reframe. One of the main features of the framer is that it performs its function "off line". That is, the framer
repositions the receive circuit only when it has detected a valid frame position. When the framer exits maintenance mode the receive counters remain where they are until the framer has found a new frame position. This means that if the user forces a reframe when the device was really in the right place, there will not be any disturbance in the circuit because the framer has no effect on the receiver until it has found synchronization. The out of synchronization criterion can be controlled by bit 0 in Master Control Word 2. This bit changes the out of frame conditions for the maintenance state.
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Preliminary Information
50 Percentage Reframe Time Probability Versus Reframe Time With Pseudo Random Data
AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AA AAA AA AAA AAA AA AAA AA AA AAA AAA AA AA AAA AA AAA AAA AA AA AAA AA AAA AAA AA AAA AAA AAA AA AAA AA AAA AAA AA AAA AAA AAA AA AAA AA AAA AAA AAA AA AAA AA AAA AAA AA AAA AAA AA AAA AAA AA AAA AAA AA AAA AAA AA AAA AAA AAA AAA AA AAA AA AAA AAA AAA AA AAA AA AAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAA AAA AAAAAA AAAAAAA AAA A A AAAA AAA AAAA AAA AAAAA A A A AAAA A AAAAAA AAA
MH89770
AAAAAAA AAAAAAA AAAAAAA D4 AAAAAAA AAAAAAA AAAAAAA ESF
40
%
30
20
10
0
AA AA AAA AA AAA AAA AA AA AAA AA AAA AA AAAAAAAAAAAAA AAAAAAAAA AA AAAA AAAAAA A A A A AAAAAA AAA
AAAAAAAA AAA AAA A
0
78
10
12
14
16
18 20 22 Reframe Time (ms)
24
26
28
30
32
34
Figure 9 - Reframe Time The out of sync threshold can be changed from 2 out of 4 errors in FT (or FPS) to 4 out of 12 errors in FT (or FPS). The average reframe time is 24 ms for ESF mode, and 12ms for D3/D4 modes. Figure 9 is a bar graph which shows the probability of achieving frame synchronization at a specific time. The chart shows the results for ESF mode with CRC check, and D3/D4 modes of operation. The average reframe time with random data is 24 ms for ESF, and 13 ms for D3/D4 modes. The probability of a reframe time of 35 ms or less is 88% for ESF mode, and 97% for D3/D4 modes. In ESF mode it is recommended that the CRC check be enabled unless the line has a high error rate. With the CRC check disabled the average reframe time is greater because the framer must also check for mimics. application to illustrate how the data on the FDL could be used. The digital phase-locked loop, the MT8941, provides all the clocks necessary to make a functional interface. The 1.544 MHz clock extracted by the MH89770 is used to clock in data at RxT and RxR. It is also internally divided by 193 to obtain an 8 kHz clock which is output at E8Ko. The MT8941 uses this 8 kHz signal to provide a phase locked 2.048 MHz clock for the ST-BUS interface and a 1.544 MHz clock for the DS1 transmit side. Note: the configurations shown in Figures 10 and 12 using the MT8941 may not meet specific jitter performance requirements. A more sophisticated PLL may be required for applications designed to meet specific standards. Please refer to the MT8941 data sheet for further details on its jitter performance. The split phase unipolar signals output by the MT8977 at TxA and TxB are used by the line driver circuit to generate a bipolar AMI signal. The line driver is transformer coupled to an equalization circuit and the DS1 line. Equalization of the transmitted signal is required to meet AT & T specifications for crossconnect compatible equip-ment (see AT&T Technical Advisory #34). Specifica-tions for the input and output transformers are shown in Figure 11. On the receive side the bipolar line signal is converted into a unipolar format by the line receiver circuit. The resulting split phase signals are input at the RxA and RxB pins on the
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Applications
1. Typical T1 Application Figure 10 shows the external components that are required in a typical T1 application using the MH89770. The MT8980 is used to control and monitor the device as well as switch data to DSTi and DSTo (refer to Application Note MSAN-123 for more information on the operation of the MT8980). The MT8952, HDLC protocol controller, is shown in this
MH89770
MH89770
Preliminary Information
DIP SWITCH MT8980 STi3 STo3 STo0 STi0 STo1 STi1 STo2 C4i F0i DSTi DSTo CSTi0 CSTo CSTi1 MT8977 TxA TxB Tx Line Driver OUTB MH89761 RxT OUTA EQU
*
F0i C2i C1.5i
RxA RxB
*
*
RX Line Receiver RxR
MT8952 CDSTo CDSTi Cki
TxFDL TxFLDClk RxFDL RxFDLClk E1.5i RxD TxSF RxSF E8Ko
*
CLOCK EXTRACTOR
MT8941 1.544 MHz CVb F0i Micro Processor C2o F0b C4b C8Kb 12.352 MHz Osc.
*
16.384 MHz Osc.
Figure 10 - Typical ESF Configuration
Line Side 1O
MH89770
MH89770 1O
Line Side
*
* *
O3 O6 O4
* *
*
O4
5 2
O O
8O
O5
6O
O8
Parameter
Input Transformer
Output Transformer
Units
Line Impedance Inductance Turns Ratio Isolation
100 (1-8) >2.2 (1-8):(3-6) 1:1 (1-8):(4-5) 1:1 1500
100 (4-8) 0.46 (1-5):(4-8) 1.89:1 (2-6):(4-8) 1.89:1 1500
mH
V(rms)
Figure 11 - Typical Parameters of the Input and Output Transformers
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Preliminary Information
MH89770
MT8920B (Mode 2) D0-D7 A0-A5 CS R/W OE C4i F0i MMS MS1 24/32 +5V STo0 STi0 STo1 DSTi DSTo CSTi0 CSTo CSTi1 MT8977 OUTA TxA TxB Tx Line Driver OUTB
MH89770
DIP SWITCH
High Speed Parallel Telecom Bus
EQU
MT89761 RxT
*
F0i C2i C1.5i
RxA RxB
*
*
Rx Line Driver
RxR
RxD Signalling and Link Control BUS MT8920B (Mode 1) D0-D7 A0-A5 CS DS R/W DTACK IRQ IACK MMS +5V STo0 STi0 STo1 CLOCK EXTRACTOR E1.5i E8Ko
*
C4i F0i
* *
1.544 MHz
MT8941 CVb F0i C2o 12.352 MHz Osc.
*
F0b C4b C8Kb
16.384 MHz Osc.
Figure 12 - Using the MH89770 in a Parallel Bus Environment MT8976. The signals are combined to produce a composite return to zero signal which is clocked into the MT8976 at RxD. 2. Interfacing the MH89770 to a Parallel Bus The MH89770 can be interfaced to a high speed parallel bus or to a microprocessor using MT8920B Parallel Access Circuit (STPA). Fig. 12 shows the MT8977 interfaced to a parallel bus structure using two STPA's operating in modes 1 and 2. The first STPA operating in mode 2 (MMS=0, MS1=1, 24/32=0), routes data and/or voice information between the parallel telecom bus and the T1 or CEPT link via DSTi and DSTo. The second STPA, operating in mode 1 (MMS=1) provides access from the signalling and link control bus to the MH89770 status and control channels. All signalling and link functions may be controlled easily through the STPA transmit RAM's Tx0, Tx1, while status information is read at receive RAM Rx0. In addition, interrupts can be set up to notify the system in case of slips, loss of sync, alarms, violations, etc. 3. PCM/Voice Channel Bank The D3/D4 channel bank is one of the most widely used pieces of equipment in the North American network today. The D3/D4 channel converts 24 analog telephone lines into the 24 channels of a T1 serial stream. The channel bank is the interface point between a digital switching or transmission system and the analog telephone loop. The industry is moving towards end-to-end digital connections (ISDN), but the analog channel bank will still be in use for many years to come.
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MH89770
Switch Matrix
Preliminary Information
Analog Line Interface
T SLIC #1 CTLi OFHK PCMi
T1 Interface
MH89770
DSTi DSTo CSTi0 CSTo CSTi1 RxR C2i OUTA OUTB RxT Equalizer
*
*
PCMo
R
*
* * * * * * * MUX
*
*
STo0 STi0 STo3 STi3
MT8980 STo1 STi1 STo2 STi2 STo4
* * * *
T SLIC #24 CTLo OFHK R
F0i C4i
F0i C1.5i
E8Ko
P MT8941 DPLL#1
Signalling Interface
C1.5i MT8870 STD #1 D3 Do * * * MT8870 STD #N D3 Do * * * MT8964 #N MT8964 #1 PCMi F0i C4i C2i CVb F0i C12i 12.352 MHz Osc.
*
Shift Reg.
DPLL#2
*
F0b C8Kb C4b C2o 16.384 MHz Osc.
C16i
Shift Reg.
Figure 13 - PCM/Voice Data Channel Bank Figure 13 shows a block diagram of a channel bank that has been divided into four sections, the analog line interface, signalling interface, switch matrix, and T1 interface. The subscriber line interface circuit (SLIC) provides interface to the telephone line, i.e., provides loop current and ringing voltage, and converts the analog voice signal into -Law PCM. The SLIC also detects the off-hook condition for conventional POTS (Plain Old Telephone Set) signalling. Once the voice is encoded into digital format the switch matrix transfers the 24 consecutive channels that are received from the SLICs to the 24 valid channels used by the MH89770. The MH89770 formats and transmits this information on the T1 line. Signalling information from the telephone sets can be routed straight through to the output T1 channel, or it can be routed to the DTMF receiver pool. This is
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easily accomplished by the MT8980 switch matrix once the SLIC has digitized the analog signal. Channel banks must be able to operate in a loop timed mode so that they meet the clock synchronization requirements of a level four entity. Phase-locked loop #2 of the MT8941 generates the ST-BUS clocks that are synchronized to the extracted 8kHz clock, and phase-locked loop #1 generates the transmit T1 clock synchronized to the ST-BUS. 4. ISDN Voice/Data Channel Bank/Concentrator The ISDN channel bank is a term that is used in this context to describe a system that performs the same logical function as the D3/D4 channel bank. That is, it concentrates the subscribers digital loop into the primary digital transmission scheme, the T1 trunk.
Preliminary Information
MH89770
T1 Interface
MH89770
STo1 STi1 STo2 STi3 C4i F0i STo3
Digital Line Interface
MT8910 DSTo DSTi ZT
Switch Matrix
MT8980
*
STi0
*
*
STo0
*
DSTi DSTo CSTi0 CSTo CSTi1
OUTA OUTB RxR RxT
Equalizer
* * * * * * * * * * * * * *
MT8910 DSTo DSTi
C2i F0i P C1.5i E8Ko
D-Channel Processing
MT8952 MT8952 DSTo MT8941 F0i DSTi C1.5
*
* *
DSTo DSTi
ZT
* * * *
MT8952 DSTo DSTi
P
P
*
E8Ko
F0o C2o C4o
P
Figure 14 - ISDN Voice Data Channel Bank The ISDN channel bank in Figure 14 is divided into four blocks, the digital line interface, the switch matrix, the D channel processing, and the T1 interface. Beginning with the digital line interface, the MT8910 provides 2B+D 160k bit bidirectional communication over single twisted pair wiring. The MT8910 converts the 160kbit line signal into ST-Bus format, where it can be manipulated by the MT8980 switch matrix. The data received from the MT8910 is then transferred to the D channel processor by the switch matrix. The D channel processor converts the 2B+D format used on the 160 kBit digital line into the 23B+D format used on the T1 Link. To control and monitor the MT8910s and the T1 interface the switch matrix operates some of its input and output streams in message mode. This enables the system to control all of the functions of the MT8910s and the T1 interface through the Control ST-BUS points, (CSTi/o). Clock synchronization is done by the MT8941. Phase-locked loop # 2 generates ST-BUS clocks that are synchronized to the extracted 8kHz output from the T1 interface. Phase-locked loop #1 generates the transmit T1 clock synchronized to the ST-BUS clocks, which are synchronized to the extracted T1 clock. This scheme will also allow the system to operate in a loop timed mode. With appropriate multiplexing a single D channel processor can handle all 23 2B+D interfaces. If both B channels on all 24 lines are going to be used then it would be necessary to use two T1 trunk interfaces.
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MH89770
5. Digital Access Cross Connect System (DACS) The Digital Access Cross Connect System (DACS) is a T1 switch with 127 T1 lines as input and output plus one T1 line that is reserved for test and maintenance purposes. A DACS is capable of switching any input channel on any T1 trunk to any output channel on any T1 trunk. There are four main blocks in Figure 15, the T1 interfaces, the switch matrix, the control matrix, and the clock generator. The digital trunk interface is made up of the MH89770 plus the additional components required to interface to the transmission line. The MH89770 handles all of the required transmit and receive data formatting, and converts the 1.544 MHz serial stream into ST-BUS format so
Preliminary Information
that it can be routed through synchronous switch matrix. the MT8980
The switch matrix can be built so that the maximum throughput delay is 1 frame +2 channels. The switch matrix will not only route data channels to their destination, but it will also route the received signalling bits through to the destination channel. This is necessary because the receiving MH89770 decodes the T1 stream, and the transmitting MH89770 has to reconstruct the outgoing T1 stream. In other words, there is no multiframe integrity between received data and transmitted data. The total throughput delay is one frame plus ten ST-BUS channels for the MH89770 receiver, 2.5 ST-BUS channels for the MH89770 transmitter, and one frame plus two ST-BUS channels for the switch matrix for a total of 2.5 frames worst case.
Switch Matrix
MT8980 STo0 STi0
MH89770 DSTi DSTo CSTi0 CSTo CSTi1 OUTB RxT RxR OUTA Equalizer
F0i C4i
STo7 STi7 C2i F0i C1.5i MT8980 E8Ko
M I C R O
STo0 STi0 STo1
Control Matrix
F0i C4i
STo2
* * * * * *
MH89770 DSTi DSTo CSTi0 CSTo CSTi1 OUTB RxT RxR C2i OUTA Equalizer
STo7 STi7
MT8941 DPLL #1 C1.5i CVb C12i F0i AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A AA AAAA A DPLL #2 F0i C4i C2i F0b C8Kb C4b C20 C16i
Clock Generator
12.352 MHz Osc.
F0i
16.384 MHz Osc.
* * * * * * *
C1.5i
E8Ko
T1 Interfaces
Figure 15 - Digital Access Cross Connect System (DACS)
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Preliminary Information
MH89770
T1 Interface
MH89770
DSTi DSTo CSTi0 CSTo CSTi1 RxR C2i OUTA OUTB RxT Equalizer
Asynchronous Interface
ACIA D0-D7 A0-A7
Protocol Converter
Switch Matrix
MT8980
MT8952 D0-D7 A0-A7
*
STi0
R S 2 3 2
*
STo0
STo1 STi1 STo2 STi2 STo3
ACIA R S 2 3 2 D0-D7 A0-A7
Micro
*
MT8952
F0i C4i
*
68008
F0i C1.5i
E8Ko
*
*
D0-D7 A0-A7 MT8941 DPLL #1
ACIA R S 2 3 2 D0-D7 A0-A7
* * *
** *
MT8952
C1.5i
CVb F0i C12i DPLL #2 12.352 MHz Osc.
D0-D7 A0-A 7
F0i C4i C2i
*
F0b C8Kb C4b C20 16.384 MHz Osc.
* * *
* * * *
** ** * *
Figure 16 - Digital Multiplex Interface (DMI) The control block only interfaces with the switch matrix. Besides routing channels and signalling through to the proper destination, the switch matrix must also supply the Master Control Words, and monitor the Master Status Words for each MH89770. The clock generation block supplies the ST-BUS clocks and the T1 transmit clocks that are synchronized to one of the T1 trunks. All of the extracted 8 kHz outputs are NANDed together before they are input to PLL #2 of the MT8941. Phase-locked Loop #2 of the MT8941, will generate ST-BUS clock signals for the MH89770s and the MT8980s that are synchronized with the chosen T1 line. The E8Ko of all of the other MH89770s can be tristated from the Master Control Word, which allows the system controller to select any one of 128 T1 lines to act as the synchronization source. By connecting the frame pulse output, F0o, of PLL #2 to F0i of PLL # 1, the MT8941 will generate the T1 transmit clock that is phase-locked to F0o, which in turn is phase-locked to the master synchronization signal, E8Ko. If all of the T1 trunks are from the network any short term differences in the received data rate will be absorbed by the elastic buffer in the MH89770. 6. Digital Multiplex Interface (DMI) Figure 16 illustrates an implementation of the Digital Multiplex Interface (DMI) specification, which defines a computer to PBX interface. This interface can convert 300 baud to 64 kbaud asynchronous or synchronous data channels to T1 format with clear channel capabilities and common channel signalling. Figure 16 is broken down into four functional blocks which are the asynchronous interface (ACIAs), the protocol converter (micro and MT8952s), the switch matrix (MT8980), and the T1 interface (MH89770).
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MH89770
The Asynchronous Communications Interface Adapters (ACIA) provide a standard RS232 interface that is compatible with many off-the-shelf modems and data sets. A single microprocessor is capable of handling the protocol conversion between the RS232 ports and the MT8952 HDLC protocol controller. The MT8952 interfaces directly to the ST-BUS, which in turn interfaces directly to the T1 interface devices. Instead of the MT8952 operating at 64 kbit/s continuously, it operates at 2.048 Mbit/s and inputs/outputs an 8 bit burst every 125 sec. This feature eliminates the need for an additional rate conversion circuit to multiplex the HDLC outputs up to the T1 data rate. Each of the HDLC chips is assigned a timeslot on the ST-BUS in a manner that is similar to enabling a voice codec. When the MT8952 is not enabled the output driver is tristated. The channel assignment circuit is therefore very simple. The switch matrix, in the message mode, passes monitor and control information between the microprocessor and the T1 interface over ST-BUS stream 0. The MT8980 is also used to reformat the ST-BUS data streams between the protocol converter and the MH89770 interface.
Preliminary Information
The MH89770 and the MT8941 form the T1 interface. The MH89770 converts the data received on the ST-BUS into a 1.544 MHz T1 stream. All of the formatting and decoding of the T1 signal is performed by this device. The MT8941 provides the clock synchronization required to operate in a loop timed mode. Digital phase-locked loop #2 provides ST-BUS clocks that are synchronized to the extracted 8kHz, and digital phase-locked loop #1 provides the transmit 1.544 MHz clock synchronized to the ST-BUS. 7. High Speed Data Transmission Link High speed data links are becoming increasingly popular in private networks and computer communications. The basic mode of transmission is to assemble data into packets (e.g., HDLC or ethernet) which are transported on a T1 link configured as a 1.536 Mbit/s serial channel. No T1 repeaters are required if the transmission link length is 1300 ft. or less (e.g., business complex or university). However, if the transmission link length is greater than 1300 ft., a repeatered T1 line must be leased from the local telephone operating company.
AAAAAAAAAAAA AAA AAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAA AAAAA A AA AA AA A AA AA Protocol Converter AA AA A AA AA AA A AA AA AA AA MT8952 AA AA AA A AA A AA AA CDSTo AA AA A AA AA AA AA CDSTi AA AA AA AA AA AA AA AA TxCEN AA AA AA AA RxCEN AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA F0i AA AA AA AA AA AA AA AA C4i AA A AA AA AA AA A AA AA AA AA AA AA A AA AA AA AA A AA AA AA AA A AA AA AA AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA MICRO AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAAA AA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAA A A
Switch Matrix
MT8980 STi0 STo0 STo1 STi1 STo2 STi2 STo3
*
F0i C4i
C1.5i
F0i C4i C2i
*
AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAA A AAAA A AAAA AAAA A AA A AA A AA T1 Interface A AA A AA A A AA A A AA MH89770 A AA A AA AA A A DSTi A AA AA OUTA A A A AA EQUALA AA DSTo A AA IZER A AA OUTB A AA CSTi1 A AA A AA A AA CSTo RxT AA A AA A AA CSTi0 A AA A AA A AA RxR A AA A AA A AA A AA A A AA A AA AA C2i A A A AA AA A A A AA A AA A AA F0i A AA A AA E8Ko A AA C1.5i A AA A AA A AA A AA AA A AA A AA A AA A AA A AA MT8941 A AA A AA A A AA DPLL #1 A AA AA A A A AA AA A A A AA A AA CVb A AA 12.352 A AA A AA MHz Osc. F0i C12i A AA A AA A AA A AA A AA A AA DPLL #2 A AA A AA A AA A AA F0b A AA A AA A C8Kb AA A A AA A AA AA A A C4b A AA AA 16.384 A A A AA AA MHz Osc. C20 C16i A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAA AA
Figure 17 - High Speed Data Transmission Link
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Preliminary Information
Figure 17 is divided into three functional blocks which are the protocol converter, switch matrix, and T1 interface. The protocol section is dependent on the particular format that is chosen. In this example it is assumed that the protocol is HDLC. The Transmit Clock Enable (TxCEN) and the Receive Clock Enable (RxCEN) of the MT8952 are active for a period of 24 consecutive ST-BUS channels, and the clock speed is 2.048 MHz. This enables the protocol conversion section to interface directly to the switch matrix. The switch matrix switches the first 24 channels received from the protocol section into the 24 valid timeslots used by the MH89770. Once the data enters the T1 interface the MH89770 formats and transmits the data on the T1 line. Control and monitoring of the T1 interface is done through the MT8980 switch matrix. CSTi0 and CSTo1 are connected to the ST-BUS streams that are configured for message mode so the controlling microprocessor can access the Master Control Words and the Master Status Words. The received portion of the T1 interface extracts the data from the T1 stream and formats it into ST-BUS channels. The MT8980 switches these ST-BUS channels into the first 24 consecutive channels of an ST-BUS stream, which is passed to the protocol conversion block. HDLC packets are disassembled from the incoming ST-BUS stream by the MT8952.
MH89770
Clock generation and synchronization are handled by the MT8941. DPLL #2 generates ST-BUS clocks that are phase-locked to the extracted 8KHz, and DPLL #1 generates the transmit T1 clock that is phase-locked to the ST-BUS frame pulse. Therefore, the interface is operating in a loop timed mode and there will be no loss of information due to slips. The MT8941 can also be configured to operate in a master timing mode. 8. T1 to CEPT Digital Trunk Converter The two main digital trunk transmission formats in use today are T1 and CEPT. Mitel's T1 and CEPT interfaces convert the digital trunk format into ST-BUS format. The common element between the two systems is the ST-BUS. Therefore, a T1 to CEPT digital trunk converter can be realized. Figure 18 shows five blocks which are the T1 interface, switch matrix, CEPT interface, clock generation and synchronization, and DSP Element. The T1 interface converts the 1.544 MHz serial stream into the ST-BUS format which interfaces to the switch matrix through DSTi and DSTo. The CEPT interface converts the 2.048 MHz serial stream into the ST-BUS format and interfaces to the switch matrix through the DSP element.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAA AAA AAA AAA AAA AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AAA AAA AAA AAA AAA AA A A AA CEPT Interface Switch Matrix AA A A AA AA A A AA AA A A AA AA A A AA AA A A AA MH89790B MT8980 A A AA AA A AA AA A DSP AA A A AA A AA AA A RxA AA A A AA Element DSTi STi0 AA A A STo1 AA A AA A A AA AA A A AA A DSTo STo0 STi1 AA A A AA A A AA A AA RxB AA A A AA AA A A AA AA CSTi0 STo3 STi2 AA A A A AA A A AA AA AA A A A STo4 STo2 CSTi1 AA A A AA AA OUTA AA A A A STi4 STo3 AA A A AA AA CSTo AA A A A AA A A AA AA AA A A A C4i C2i AA A A AA OUTB AA A A AA AA A A AA F0i F0i AA A A AA AA A A AA AA A A AA E8Ko AA A A AA AA A A AA AA A A AA AA A A AA P AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AA AA A AA AA A AA A MT8941 AA A AA A AA A DPLL #1 AA A AA A AA A C1.5o AA A AA A AA A AA A AA A AA A DPLL #2 AA A F0o AA A AA A AA A AA A C2o AA A AA A E8Ki AA A AA A C4o AA A AA A AA A AA A Clock Generator AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A T1 Interface AA A AA A AA A AA A MH89770 AA A AA A AA A RxT AA A AA A AA A DSTi AA A AA A AA A RxR AA A DSTo AA A AA A AA A CSTo AA A AA A AA A CSTi0 AA A AA A OUTA AA A CSTi1 AA A AA A AA A AA A F0i AA A OUTB AA A AA A C2i AA A AA A AA A C1.5i AA A AA A AA A E8Ko AA A AA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAA A
Figure 18 - T1 to CEPT Digital Trunk Converter
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MH89770
With both the T1 data and the CEPT data converted to the ST-BUS format, the two digital trunks can exchange information through the switch matrix. Unfortunately, the signalling information from the two formats is not exchanged as easily. The T1 A and B signalling bits must be read by the controlling microprocessor and converted in software to the CEPT ABCD signalling bits, and vice versa. The circuit must also convert all the channels carrying voice data to the appropriate encoding scheme, (i.e., T1 -Law or CEPT A-Law). This is done by the block labelled DSP in Figure 18, Digital Signal Processor. The final component of the system is the MT8941. The extracted 8 kHz outputs from the T1 and the CEPT interfaces are combined with an AND gate before being connected to the MT8941. One of the interfaces is selected as the synchronization source by enabling its output through the Master Control Word of the chosen interface. Phase-locked loop #2 will then generate ST-BUS clocks that are synchronized to either the T1 network or the CEPT network. Phase-locked loop #1 is configured to generate the T1 transmit clock synchronized to the ST-BUS. Therefore, if the ST-BUS is synchronized to one network then the elastic buffer in the opposite interfaces will perform controlled slips between that network and the T1 to CEPT converter.
Preliminary Information
Packaging
The MH89770 is available in two package options which are: * The MH89770S which is a surface mountable version of the MH89770N is suitable for Infrared Reflow (I.R.) soldering. See Figure 35 for the dimensional drawing, and Figure 36 for the recommended footprint. The MH89770N has a row pitch of 0.8". See Figure 37 for the dimensional drawing for this part.
*
Magnetics Information
For supporting initial design activities, Mitel Semiconductor has available the MH89770 Magnetic Kit which contains the magnetics shown in Figure 11. Alternatively, they are available directly from the following manufacturer: Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 Telephone: (613) 226-1626 Please refer to Figure 6 for the transformer part numbers.
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Preliminary Information
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 6 Supply Voltage with respect to VSS Voltage on any pin other than supplies, OUTA or OUTB Voltage on OUTA or OUTB Current at any pin other than supplies, OUTA or OUTB Current at OUTA or OUTB Storage Temperature TST -20 Symbol VDD Min -0.3 VSS-0.3
MH89770
.
Max 7 VDD+0.3 15 20 200 85
Units V V V mA mW C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameters 1 I n p u t s Operating Temperature Sym TOP Min 0 Typ Max 70 Units C Test Conditions
2 3
Supply Voltage Input High Voltage
VDD VIH VIH
4.5 2.4
5.0
5.5 VDD
V V V Digital Inputs Line Inputs Digital Inputs Line Inputs
3.0 VSS 0.3 0.4
4
Input Low Voltage
VIH VIL
V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Clocked operation over recommended temperature ranges.
Parameters 1 2 3 4 5 6 7 8
O u t p u t s I n p u t s
Sym IDD VIH VIL IIL IOH IOL VOL ZIN
Min
Typ 12
Max 25
Units mA V
Test Conditions Outputs Unloaded Digital Inputs Digital Inputs Digital Inputs VIN=0 to VDD Source Current VOH=2.4V Sink Current VOL=0.4V IOL=10mA
Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output High Current Output Low Current Output Low Voltage OUTA or OUTB Input Impedance RxT to RxR RxT or RxR to Gnd Schmitt Trigger Input (XSt)
2.0 0.8 1 7 2 20 10 0.25 400 1K 10
V A mA mA V
9
VT+ VT1.5
4.0
V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Capacitance
Characteristics 1 2 Input Pin Capacitance Output Pin Capacitance Sym CI CO Min Typ 10 10 Max Units pF pF Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MH89770
AC Electrical Characteristics - Clock Timing (Figure 19 & 20)
Characteristics 1 2 3 4 5 6 7 8 C2i Clock Period C2i Clock Width High or Low Frame Pulse Setup Time Frame Pulse Hold Time Frame Pulse Width RxSF Output Delay TxSF Hold Time TxSF Setup Time Sym tp20 tW20 tFPS tFPH tFPW tFPOD tTxSFH tTxSFS 0.5 0.5 Min 400 200 50 50 50 125 124.5 124.5 Typ 488 244 Max 600 300
Preliminary Information
Units ns ns ns ns ns ns s s
Test Conditions
tP20 = 488 ns
50pF Load
NB: Frame Pulse is repeated every 125s in synchronization with the clock. Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. F0i Frame 1
Frame 12/24
Frame 2
RxSF
TxSF
C2i
ST-BUS BIT CELLS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 7
Bit 6
Bit 5
Bit 4
Figure 19 - Clock & Frame Alignment for ST-BUS Streams
tP20 C2i VIH VIL tW20 tFPS F0i VIH VIL tFPH tFPS tFPW tFPOD RxSF VOH VOL tFPOD tW20
AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA
F0i Frame 12/24 VIH C2i VIL tTxSFH VIH TxSF VIL
Frame 1
tTxSFS
Figure 20 - Clock & Frame Pulse Timing for ST-BUS Streams
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Preliminary Information
AC Electrical Characteristics - Timing For DS1 Link Bit Cells (Figure 21)
Characteristics 1 2 3 4 E1.50 Clock Period E1.5o Clock Width High or Low E1.5o Clock Rise Time E1.5o Clock Fall Time Sym tPEC tWEC tREC tFEC Min Typ 648 324 60 20 Max Units ns ns ns ns
MH89770
Test Conditions
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DS1 BIT CELLS FOR RECEPTION
BIT CELL
BIT CELL
tR1EC E1.5o VOH VOL tP1EC
tW1EC
tR1EC
tW1EC
Figure 21 - DS1 Receive Clock Timing
AC Electrical Characteristics - 2048 kbit/s ST-BUS Streams (Figure 22)
Characteristics 1 2 3 Serial Output Delay Serial Input Setup Time Serial Input Hold Time Sym tSOD tSIS tSIH 15 50 Min Typ Max 125 Units ns ns ns Test Conditions 150pF load
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Bit Cell Boundaries
C2i
V IH VIL
DSTo or CSTo
VOH VOL tSOD tSOD
DSTi, CSTi0/CSTi1
VIH VIL tSIS tSIH
Figure 22 - ST-BUS Stream Timing
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MH89770
Typ
Preliminary Information
AC Electrical Characteristics - XCTL, XSt, & E8Ko (Figure 23, 24, & 25)
Parameters 1 2 3 4 5 6 7 8 External Control Delay External Status Setup Time External Status Hold Time 8 kHz Output Delay 8 kHz Output Low Width 8 kHz Output High Width 8 kHz Rise Time 8 kHz Fall Time Sym tXCD tXSS tXSH t8OD t8OL t8OH t8R t8F 78 47 10 10 Min Max 140 100 400 150 Units ns ns ns ns s s ns ns Test Conditions
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
ST-BUS Bit Cell Boundary Between Bit 0 Channel 15 and Bit 7 and Channel 16
ST-BUS Bit Cell Boundary Between Bit 2 Channel 30 and Bit 1 Channel 30
C2i
2.0V 0.8V
C2i
2.0V 0.8V
2.4V XCtl 0.4V
2.0V XSt 0.8V
tXCD
tXSS
tXSH
Figure 23 - XCTL Timing
Figure 24 - XST Timing
Received DS1 Bits
Channel 2 Bit 1
***
Channel 17 Bit 2
***
Channel 2 Bit 1
VOH E1.5o VOL t8OD VOH E8Ko VOL t8OL t8F t8R t8OH t8F t8OD t8OD
Figure 25 - E8Ko Timing
4-154
Preliminary Information
AC Electrical Characteristics - DS1 Link Timing (Figures 26 and 27)
Characteristics 1 2 3 4 5 6 7 8 9 10 Transmit Steering Delay E1.5o Clock Period E1.5o Clock Width High or Low Receive Data Setup Time Receive Data Hold Time Receive Data Pulse Width Receive Data Fall Time Receive Data Rise Time C1.5i Period C1.5i Pulse Width High or Low Sym tTSD tPEC tWEC tRDS tRDH tRDW tRDF tRDR tPC1.5 tWC1.5 500 250 Min 50 648 324 50 50 324 20 20 648 324 800 Typ Max 150 Units ns ns ns ns ns ns ns ns ns ns
MH89770
Test Conditions 150pF Load
Timing is over recommended operating temperature and power supply voltage ranges. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Transmitted DS1 Link Bit Cells
Bit Cell tPC1.5
VIH C1.5i VIL tTSD OUTA or OUTB VOH VOL tWC1.5 tTSD
Figure 26 - Transmit Timing for DS1 Link
Received DS1 Link Bit Cells tWEC VOH E1.5o VOL tRDS RxA or RxB VOH VOL
Bit Cell tPEC tWEC
tRDH
tRDW tRDF tRDR
Figure 27 - Receive Timing for DS1 Link
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MH89770
Parameters 1 2 3 4 Transmit FDL Setup Time Transmit FDL Hold Time Receive FDL Output Delay Facility Data Link Clock Delay Sym tDLS tDLH tDLOD tFCD Min 110 70 0 135 Typ Max
Preliminary Information
AC Electrical Characteristics - DS1 Link Timing (Figure 28 & 29)
Units ns ns ns ns 50pF Load 50pF Load Test Conditions
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
F0i C2i
Frame 12/24
Frame 1
Frame 2
RxFDLClk RxFDL
TxFDLClk
TxFDL
Figure 28 - Clock & Frame Alignment for RxFDL and TxFDL
C2i
VIH VIL tFCD
TxFDLClk VOH RxFDLClk VOL
or
tDLOD
VOH RxFDL VOL tDLS VIH VIL tDLH
TxFDL
Figure 29 - Facility Data Link Timing
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Preliminary Information
125s CHANNEL 31 CHANNEL 0
MH89770
********
CHANNEL 30
CHANNEL 31
CHANNEL 0
(8/2.048)s NB: Numbering differs from Fig 31. Most Significant Bit (First) Least Significant Bit (Last)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 30 - Format of 2048 kbit/s ST/BUS Streams
125s CHANNEL 24 S Bit CHANNEL 1
******
CHANNEL 23
CHANNEL 24
S Bit
CHANNEL 1
(1/1.544)s NB: Numbering differs from Fig 30.
(8/1.544)s Least Significant Bit (Last)
Most Significant Bit (First)
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 31 - DS1 Link Frame Format
125s C2i
DSTi
DSTo CSTi0/CSTi1
7
6
5
4
3
2
1
0
* ** * * * * * ** * * ** * * * * * ** *
7
CSTo
7
6
5
4
3
2
1
0
7
Figure 32 - Functional ST-BUS Timing
125s E1.5i
INT DATA
1
1
0
0
1
1
0
1
RxT/RxR LINE SIGNAL RxA
RxB
E8Ko
Figure 33 - Functional DS1 Receive Timing
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MH89770
C1.5i
Preliminary Information
INT DATA
OUTA
OUTB
AMI LINE
Figure 34 - DS1 Transmit Timing
2.0 (50.8)
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
0.3 (7.62)
0.78 (19.81) 0.06 (1.52) 0.9 (22.86)
0.125 (3.18)
0.10 + 0.01 (2.54 + 0.25)
0.06 (1.52)
MH89770S
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.125 (3.18)
Note 1
0.020 + 0.002 (0.51 + 0.051)
Notes: 1) Pin 1 not fitted. 2) All dimensions are typical and in inches (mm). 3) Not to scale.
Figure 35 - Physical Dimensions for the 40 Pin Dual in Line S.M.T. Hybrid
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Preliminary Information
MH89770
0.760 (19.3) Pin 2 position 0.090 (2.29)
0.040 (1.02)
0.060 (1.52)
Figure 36 - Recommended Footprint for the 40 Pin Dual in Line S.M.T. Hybrid
2.0 (50.8)
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
0.3 (7.62)
0.8 (20.32) Note 2 0.10 + 0.01 (2.54 + 0.25)
MH89770N
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.09 (2.3) 0.260 (6.6)
Note 1 0.020 + 0.002 (0.51 + 0.051) Notes: 1) Pin 1 not fitted. 2) Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale.
Figure 37 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch
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MH89770
Appendix
Control and Status Register Summary 7
Debounce 1 Disabled 0 Enabled
Preliminary Information
6
TSPZCS 1 Disabled 0 Enabled
5
B8ZS 1 B8ZS 0 Jammed Bit
4
8KHSel 1 Disabled 0 Enabled
3
XCtI 1 Set High 0 Cleared
2
ESFYLW 1 Enabled 0 Disabled
1
Robbed Bit 1 Disabled 0 Enabled
0
YLALR 1 Enabled 0 Disabled
Master Control Word 1 (Channel 15, CSTi0)
RMLOOP 1 Enabled 0 Disabled DGLOOP 1 Enabled 0 Disabled ALL1's 1 Enabled 0 Disabled ESF/D4 1 ESF 0 D3/D4 Reframe Device Reframes on High to Low Transition SLC-96 1 Enabled 0 Disabled CRC/MIMIC See Note 1 Maint. 1 4/12 0 2/4
Master Control Word 2 (Channel 31, CSTi0)
Polarity UNUSED - KEEP AT 0 1 No Inversion 0 Inversion Loop 1 Ch. looped back 0 Normal Data 1 Enabled 0 Disabled
Per Channel Control Words (All Channels on CSTi0 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31)
UNUSED - KEEP AT 0 A Txt. Sig. Bit B Txt. Sig. Bit C Txt. Sig. Bit D Txt. Sig. Bit
Per Channel Control Words (All Channels on CSTi1 Except Channels 3, 7, 11, 15, 19, 23, 27 & 31)
YLAIR 1 Detected 0 Normal MIMIC Detected 0 Not Detected ERR FT Error Count ESFYLW 1 Detected 0 Not Detected MFSYNC 1 Not Detected 0 Detected BPV Bipolar Violation count SLIP Changes State when Slip Performed SYN 1 Out-of-Sync. 0 In-Sync
Master Status Word 1 (Channel 15, CSTo)
BlAlm 1 Detected 0 Not Detected FrCnt Frame Count XSt 1 Xst High 0 Xst Low BIPOLAR VIOLATION COUNT CRC-ERROR COUNT
Master Status Word 2 (Channel 31, CSTo)
CHANNEL COUNT BIT COUNT
Phase Status Word (Channel 3, CSTo)
UNUSED A Rec'd. Sig. Bit B Rec'd. Sig. Bit C Rec'd. Sig. Bit D Rec'd. Sig. Bit
Per Channel Status Word (All Channels on CSTo Except Channels 3, 7, 11, 15, 19, 23, 27, 31)
Note 1: In ESF mode: 1: CRC calc. ignored during Sync. 0: CRC checked for Sync. In D3/D4 mode: 1: Sync. to first correct S-bit pattern. 0: Will not Sync. if Mimic detected.
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