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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
PRELIMINARY
August 2005
ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
General Description
This is Preliminary Information for a product currently in development. ALL specifications are design targets and are subject to change. The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.0V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065's six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. No missing codes performance is guaranteed over the full operating temperature range. The pipeline ADC architecture achieves > 11 Effective Bits over the entire Nyquist band at 65 MSPS. The ADC12QS065 output pins can be put into a high impedance state. The serializer PLL can lock to frequencies between 20 MHz and 65 MHz. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40C to +85C) temperature range, the ADC12QS065 is available in a 64 pin TQFP package.
Features
n n n n n n n n Single +3.0V supply operation Internal sample-and-hold Internal reference Low power consumption Power down mode Clock and Data Frame Timing 780 Mbps serial LVDS data rate (at 65 MHz clock) LVDS serial output rated for 100 Ohm load
Key Specifications
n n n n n n n n Resolution DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) ENOB (at Nyquist) Power Consumption -- Operating, 65 MSPS, per ADC -- Power Down Mode 12 Bits
0.3 LSB (typ)
68.5 dB (typ) 85 dB (typ) 11 Bits (typ) 200 mW (typ) < 3 mW (typ)
Applications
n n n n n Ultrasound Medical Imaging Communications Portable Instrumentation Digital Video
Connection Diagram
20106801
(c) 2005 National Semiconductor Corporation
DS201068
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Ordering Information
Industrial (-40C TA +85C) ADC12QS065CIVS ADC12QS065EVAL Package 64 Pin TQFP Evaluation Board
Block Diagram
20106802
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Pin Descriptions
Pin No. ANALOG I/O 3 7 10 14 4 6 11 13 VIN1+ VIN2+ VIN3+ VIN4+ VIN1VIN2VIN3VIN4Symbol Description
Differential analog input pins. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VCOM. The negative input pins may be connected to VCOM for single-ended operation, but a differential input signal is required for best performance.
24
VREF
This pin is the reference select pin and the external reference input, used in conjunction with the INTREF pin. If the INTREF pin is set to VA , this pin is used as an internal reference select. With VREF = VA, the internal 1.0V reference is selected. With VREF=AGND, the internal 0.5V reference is selected. If the INTREF pin is set to AGND, then this pin is the input for an external reference. A voltage in the range of 0.8 to 1.2V may be applied to this pin. VREF should be bypassed to AGND with a 1.0 F capacitor when an external reference is used. Top ADC Reference. This pin has to be driven to 1.9V if REFPD is high. If REFPD is low, bypass this pin with a 0.1 F low ESR capacitor to AGND and a 10 F low ESR capacitor to VREFB. This is an analog output which can be used as a common mode voltage for the inputs. It should be bypassed to AGND with a minimum of a 1.0 F low ESR capacitor in parallel with a 0.1 F capacitor. Pin 23 may also be used as a 1.5V temperature stable reference voltage. Bottom ADC Reference. This pin has to be driven to 0.9V if REFPD is high. If REFPD is low, bypass this pin with a 0.1 F low ESR capacitor to AGND and a 10 F low ESR capacitor to VREFT. These are bypass pins for the internal 1.8V regulator. Each pin should be bypassed to AGND with a 1.0 F capacitor This pin acts as either a Non-Inverting Differential Clock input or a CMOS clock input. If CLKB is used as the Inverting Clock input, CLK will act as the Non-Inverting Clock input. If CLKB is tied to AGND, CLK will act as a CMOS clock input. ADC power consumption will increase by about 40mW if a Differential Clock is used. Inverting Differential Clock input. If tied to AGND, CLK acts as a CMOS clock input. Internal reference enable input. When this pin is high, two internal reference choices are selectable through the VREF pin. When this pin is low, an external reference must be applied to VREF (pin 24). Serial Data Output Enable. TTL level input. A low, puts the LVDS outputs in High-Impedance State. Power Down pin that, when high, puts the converter into the Power Down mode. With REFPD high, user must drive VREFT12, VREFT34 and VREFB12 & VREFB34 externally. With REFPD low, VREFT12, VREFT34 and VREFB12 & VREFB34 are driven internally.
59 22
VREFT12 VREFT34
58 23
VCOM12 VCOM34
60 21 32,49 DIGITAL I/O
VREFB12 VREFB34 VREG
55
CLK
56
CLKB
57
INTREF
31 25 26 46 44 36 34
DEN PD REFPD DO1+ DO2+ DO3+ DO4+
+ Serial Data Output. Non-inverting LVDS differential output.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Pin Descriptions
Pin No. 47 45 37 35 41 42 39 40 ANALOG POWER 1,16,18,20, 61,63 2,5,8,9, 12,15,17,19, 29,52,62,64 DIGITAL POWER 27,54 28,53
(Continued) Symbol DO1DO2DO3DO4FRAME+ FRAMEOUTCLK+ OUTCLKDescription
- Serial Data Output. Inverting LVDS differential output.
LVDS output, it's rising edge corresponds to the first serial bit of the output streams. FRAME clock frequency is the same as the CLK frequency. LVDS output clock. The data is valid on an output transition. Successive data bits are captured on both edges of this clock. OUTCLK frequency is 6X the CLK frequency. Positive analog supply pins. These pins should be connected to a quiet +3.0V source and bypassed to AGND with 0.1 F capacitors located near these power pins, and with a 10 F capacitor. The ground return for the analog supply.
VA
AGND
VD DGND
Positive digital supply pin. This pin should be connected to the same quiet +3.0V source as is VA and be bypassed to DGND with a 0.1 F capacitor located near the power pin and with a 10 F capacitor. The ground return for the digital supply. Positive driver supply pin for the ADC12QS065's output drivers. This pin should be connected to a voltage source of +2.5V to VD and be bypassed to DR GND with a 0.1 F capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 F capacitor. VDR should never exceed the voltage on VD. All bypass capacitors should be located near the supply pin. The ground return for the ADC12QS065's output drivers.
30, 51
VDR
33,38,43, 48,50
DRGND
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Absolute Maximum Ratings
2)
(Notes 1,
Operating Ratings (Notes 1, 2)
Operating Temperature Supply Voltage (VA, VD, VDR) VIN Differential Input Range VCM Input Common Mode Range (Differential Input) VREF Voltage Range Digital Input Pins Voltage Range (excludes pins 31 to 50) |AGND-DGND| Clock Duty Cycle -40C TA +85C +2.7V to +3.6V
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VA, VD, VDR |VA-VD| 3.8V 100 mV
VREF
VREF/2 to (VA - VREF/2 ) 0.5V to 1.0V -0.3V to (VA + 0.3V)
Voltage on any pin to GND (valid for -0.3V to (VA or VD +0.3V) pins 1-30 and 51-64) Voltage on any Pin to GND (valid for pins 31-50) Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25C LVDS Output Short Circuit Duration ESD Susceptibility Human Body Model (Note 5) Machine Model (Note 5) Soldering Temperature, Infrared, 10 sec. (Note 6) Storage Temperature 2500V 250V 235C -65C to +150C -0.3V to 2.2V
25 mA 50 mA
See (Note 4) 10 ms
100mV 30% to 70%
Converter Electrical Characteristics
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, VCOM=1.5V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) 12 Units (Limits) Bits (min) LSB (max) LSB (max) %FS (max) %FS (max) ppm/C %FS (max) %FS (min) ppm/C 0 4095 0.5 2.0 2.0 VIN = 2.5 Vdc + 0.7 Vrms (CLK LOW) (CLK HIGH) 8 3 1.00 0.8 1.2 V (min) V (max) VP-P pF pF V (min) V (max) A ppm/C
STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL GE NGE TC GE VOFF TC VOFF Integral Non Linearity (Note 11) Differential Non Linearity Positive Gain Error Negative Gain Error Gain Error Tempco Offset Error (VIN+ = VIN-) Offset Error Tempco Under Range Output Code Over Range Output Code REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM VIN CIN VREF IREF TCVCMO Common Mode Input Voltage Analog Differential Input Range VIN Input Capacitance (each pin to GND) External Reference Voltage (Note 13) Reference Input Current Reference Temperature Coefficient 1.5 -40C TA +85C -40C TA +85C
0.6 0.3 0.5 0.5
5
0.15
4 0 4095
<1
80
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Converter Electrical Characteristics
(Continued)
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, VCOM=1.5V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) 300 68.5 68.5 68.3 68.5 68.3 68 11.1 11.1 11 -83 -83 -77 -90 -90 -83 -85 -85 -80 85 85 80 -70 300 Limits (Note 10) Units (Limits) MHz dBc dBc (min) dBc dBc dBc (min) dBc Bits Bits (min) Bits dBc dBc (min) dBc dBc dBc (min) dBc dBc dBc (min) dBc dBc dBc (min) dBc dBFS MHz %FS %FS dBc dBc
DYNAMIC CONVERTER CHARACTERISTICS FPBW SNR Full Power Bandwidth Signal-to-Noise Ratio 0 dBFS Input, Output at -3 dB fIN = 1 MHz, VIN = -0.5 dBFS fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS SINAD Signal-to-Noise and Distortion fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS ENOB Effective Number of Bits fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS THD Total Harmonic Distortion fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS H2 Second Harmonic Distortion fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS H3 Third Harmonic Distortion fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS fIN = 1 MHz, VIN = -0.5 dBFS SFDR Spurious Free Dynamic Range fIN = 10 MHz, VIN = -0.5 dBFS fIN = 33 MHz, VIN = -0.5 dBFS IMD FPBW Intermodulation Distortion Full Power Bandwidth Channel -- Channel Offset Match Channel -- Channel Gain Match Crosstalk (between any two channels) 10 MHz Tested, Channel; 20 MHz Other Channel 10 MHz Tested, Channel; 65 MHz Other Channel fIN = 9.6 MHz and 10.2 MHz, each = -6.0 dBFS
INTER-CHANNEL CHARACTERISTICS
0.3 4
80 80
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
DC and Logic Electrical Characteristics
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) 2.0 0.5 1 -1 215 0.5 35 0.2 60 800 3 TBD Units (Limits) V (min) V (max) A A mA mA mA (max) mA mA mW (max) mW dB
DIGITAL INPUT CHARACTERISTICS VIN(1) VIN(0) IIN(1) IIN(0) Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current VD = 3.6V VD = 3.0V VIN = 3.3V VIN = 0V PD Pin = DGND PD Pin = VD PD Pin = DGND PD Pin = VD PD Pin = DGND, fIN = 33 MHz PD Pin = DGND, CL = 5 pF (Note 15) PD Pin = VD Rejection of Full-Scale Error with VA = 3.0V vs. 3.6V
POWER SUPPLY CHARACTERISTICS IA ID IDR PWR PSRR1 Analog Supply Current Digital Supply Current LVDS Output Supply Current Total Power Consumption Power Supply Rejection Ratio
AC Electrical Characteristics
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9, 12) Symbol fCLK1 fCLK2 Parameter Maximum Clock Frequency Minimum Clock Frequency Clock Duty Cycle tCONV tAD tAJ tPD Conversion Latency Aperture Delay Aperture Jitter Power Down Mode Exit Cycle Input Sample(N) to LSB of Sample(N) Data valid 2 1 20 50 30 70 9 Conditions Typical (Note 10) Limits (Note 10) 65 Units (Limits) MHz (min) MHz % min % max Clock Cycles ns ps rms ms
<5
LVDS Electrical Characteristics
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) 250 400 30 Units (Limits) mV (min) mV (max) mV (max)
LVDS DC CHARACTERISTICS VOD delta VOD Output Differential Voltage (DO+)-(DO-) Output Differential Voltage Unbalance RL = 100 RL = 100 300
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
LVDS Electrical Characteristics
(Continued)
NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN = 2VP-P , VREF = +1.0V external, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25C (Notes 7, 8, 9, 12) Symbol VOS delta VOS IOS IOZ IOX tOCP tOCHL tH tS tFP tFHL tDFS tR, tF tOCJ tFJ tHZD tLZD tZHD tZLD tPLD tSD Parameter Offset Voltage Offset Voltage Unbalance Output Short Circuit Current High Impedance Output Current Power-Off Output Current Output Clock Period Output Clock High/Low Time Data Edge to Output Clock Edge Hold Time Data Edge to Output Clock Edge Set-Up Time Frame Period Frame Clock High/Low Time Data Edge to Frame Edge Skew LVDS Rise/Fall Time Output Clock Jitter Frame Jitter DO High to High-Impedance Delay DO Low to High-Impedance Delay DO High-Impedance to High Delay DO High-Impedance to Low Delay Serializer PLL Lock Time Serializer Delay RL=100 RL = 100 RL = 100 DO = 0V, VIN = 1.1V, DEN = VA DEN = 0V, DO = 0V or VA VA = 0V, DO = 0V or VA 50% to 50% 80%-to-80% for high, 20%-to-20% for low
@ 65 MSPS, 50% to 50% @ 40 MSPS, 50% to 50% @ 65 MSPS, 50% to 50% @ 40 MSPS, 50% to 50%
Conditions
Typical (Note 10) 1.25
Limits (Note 10) 1.2 1.3 30
Units (Limits) V (min) V (max) mV (max) mA (max) A A ns ps ps ps ps ps ns ns ps ps ps ps rms ps rms
-10
-15
1 1
2.56 880 601 1040 601 1040 15.38 7.3 19.4 19.4 400 44 11 3 3 5 5 50 2.76
10 20
LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS
50% to 50% 80%-to-80% for high, 20%-to-20% for low
@ 65 MSPS, 50% to 50% @ 40 MSPS, 50% to 50%
CL=5pF to GND, ROUT=100 Cycle to Cycle Jitter Cycle to Cycle Jitter CL=5pF to GND, RL=100 CL=5pF to GND, RL=100 CL=5pF to GND, RL=100 CL=5pF to GND, RL=100
10 10 10 10
ns ns ns ns s ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (-JA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/JA. In the 64-pin TQFP, JA is 50C/W, so PDMAX = 2 Watts at 25C and 800 mW at the maximum operating ambient temperature of 85C. Note that the power consumption of this device under normal operation will typically be about 900 mW. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0. Note 6: The 235C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220C. Only one excursion above 183C is allowed per reflow cycle.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
LVDS Electrical Characteristics
(Continued)
Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be +3.4V to ensure accurate conversions.
20106807
Note 8: To guarantee accuracy, it is required that |VA-VD| 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 V. Note 10: Typical figures are at TJ = 25C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative full-scale. Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.0V for a rising edge. Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is recommended for external reference applications. Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 15: Excludes IDR. See note 14.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC. CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. CROSSTALK is coupling of energy from one channel into the other channel. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error - Offset Error A gain of unity occurs when the negative and positive full scale errors are equal to each other, including having the same sign. GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average gain of the converters. INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (12 LSB below the first code transition) through positive full scale (12 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS. LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VREF/2n, where "n" is the ADC resolution in bits, which is 12 in the case of the ADC12QS065. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12QS065 is guaranteed not to have any missing codes. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of 12 LSB above negative full scale. OFFSET ERROR is the difference between the two input voltages [(VIN+) - (VIN-)] required to cause a transition from code 2047 to 2048. OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal input range to a specified voltage within the normal input range and the converter makes a conversion with its rated accuracy. PIPELINE DELAY (LATENCY) See CONVERSION LATENCY. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 112 LSB below positive full scale. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. For the ADC12QS065, PSRR1 is the ratio of the change in Full-Scale Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as
where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the first 9 harmonic frequencies in the output spectrum. SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Timing Diagram
20106809
LVDS Output Timing
Transfer Characteristic
20106810
FIGURE 1. Transfer Characteristic
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Functional Description
Operating on a single +3.0V supply, the ADC12QS065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any external reference is buffered on-chip to ease the task of driving that pin. Sampled data is transformed into high speed serial output LVDS data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065's six differential pairs transmit data over backplanes or cable and also make PCB design easier. The output word rate is the same as the clock frequency, which can be between 20 MSPS and 65 MSPS (typical) with fully specified performance at 65 MSPS. The analog input for all channels are acquired at the rising edge of the clock and the digital data for a given sample is delayed by the pipeline for 9 clock cycles.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may result in degraded noise performance. DO NOT LOAD these pins. Loading any of these pins may result in performance degradation. The nominal voltages for the reference bypass pins are as follows: VCOM = 1.5 V VREFT = VCOM + VREF / 2 VREFB = VCOM - VREF / 2 User choice of an on-chip or external reference voltage is provided. When INTREF (pin 57) is high, the VREF pin selects the internal reference voltage. The internal 1.0 Volt reference is in use when the the VREF pin is connected to VA. When the VREF pin is connected to AGND, the internal 0.5 Volt reference is in use. When INTREF (pin 57) is low, a voltage in the range of 0.8V to 1.2V is applied to the VREF pin and that is used for the voltage reference. When an external reference is used, the VREF pin should be bypassed to ground with a 0.1 F capacitor close to the reference input pin. There is no need to bypass the VREF pin when the internal reference is used. 2.2 Signal Inputs The ADC12QS065 has 4 input channels. They are labelled VIN 1+ and VIN1- , VIN 2+ and VIN2- , VIN 3+ and VIN3- , VIN 4+ and VIN4- . The input signal, VIN, is defined as VIN = (VIN+) - (VIN-) Figure 2 shows the expected input signal range. Note that the common mode input voltage, VCM, should be in the range of 0.5V to 2.0V with a typical value of 1.5V. The peaks of the individual input signals should each never exceed 2.6V to maintain THD and SINAD performance. The ADC12QS065 performs best with a differential input signal with each input centered around a common mode voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180 out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms, however, angular errors will result in distortion.
Applications Information
1.0 OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the ADC12QS065: 2.7V VA 3.6V VD = VA = VDR 20 MHz fCLK 65 MHz 0.8V VREF 1.2V (for an external reference) 0.5V VCM 2.0V 2.0 ANALOG INPUTS There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external reference. The ADC12QS065 has four analog signal input pairs, VIN 1+ and VIN 1-, VIN 2+ and VIN 2- , VIN 3+ and VIN 3-, VIN 4+ and VIN 4- . Each pair of pins forms a differential input pair. There are two VREG pins for decoupling the internal 1.8V regulator. 2.1 Reference Pins The ADC12QS065 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference, but performs well with external reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12QS065. Increasing the reference voltage (and the input signal swing) beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies. It is important that all grounds associated with the reference voltage and the analog input signal make connection to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The six Reference Bypass Pins (VREFT12, VREFB12, VCOM12, VREFT34, VREFB34 and VCOM34) are made available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 F capacitor. A 10 F capacitor should be placed between the VREFT12 and VREFB12 pins and between the VREFT34 and VREFB34 pins, as shown in Figure 4. This configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR.
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FIGURE 2. Expected Input Signal Range For single frequency sine waves the full scale error in LSB can be described as approximately EFS = 4096 ( 1 - sin (90 + dev))
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Applications Information
(Continued)
VIN+ VCM - VREF / 2 VCM VCM + VREF / 2 VCM + VREF
VIN- VCM VCM VCM VCM
Binary Output 0100 0000 0000 1000 0000 0000 1100 0000 0000 1111 1111 1111
Where dev is the angular difference in degrees between the two signals having a 180 relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100.
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FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage just below the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM. 2.2.1 Single-Ended Operation Performance with differential input signals is better than with single-ended signals. For this reason, single-ended operation is not recommended. However, if single ended-operation is required and the resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the driven input. The peak-topeak differential input signal at the driven input pin should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 0.5V, bias VIN- to 1.0V and drive VIN+ with a signal range of 0.5V to 1.5V. Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12QS065. TABLE 1. Input to Output Relationship - Differential Input VIN+ VCM - VREF / 2 VCM - VREF / 4 VCM VIN- VCM + VREF / 2 Binary Output 0000 0000 0000
2.2.2 Driving the Analog Inputs The VIN+ and the VIN- inputs of the ADC12QS065 consist of an analog switch followed by a switched-capacitor amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when the clock is low, and 7 pF when the clock is high. As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in voltage spikes at the signal input pins. As a driving amplifier attempts to counteract these voltage spikes, a damped oscillation may appear at the ADC analog input. Do not attempt to filter out these pulses. Rather, use amplifiers to drive the ADC12QS065 input pins that are able to react to these puses and settle before the switch opens and another sample is taken. The LMH6702 LMH6628, LMH6622 and the LMH6655 are good amplifiers for driving the ADC12QS065. To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in Figure 4 . These components should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter that input. For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. A single-ended to differential conversion circuit is shown in Figure 5. Table 3 gives resistor values for that circuit to provide input signals in a range of 1.0V 0.5V at each of the differential input pins of the ADC12QS065. TABLE 3. Resistor Values for Circuit of Figure 5 SIGNAL RANGE 0 - 0.25V 0 - 0.5V R1 open 0 100 R2 0 open 698 R3 124 499 100 R4 R5, R6
VCM + 0100 0000 0000 VREF / 4 VCM 1000 0000 0000
1500 1000 1500 698 499 499
0.25V
VCM - VCM + 1100 0000 0000 VREF / 4 VREF / 4 VCM + VCM - VREF / 2 VREF / 2 1111 1111 1111
TABLE 2. Input to Output Relationship - Single-Ended Input VIN+ VCM - VREF VIN- VCM Binary Output 0000 0000 0000
2.2.3 Input Common Mode Voltage The input common mode voltage, VCM, should be in the range of 0.5V to 2.0V and be a value such that the peak excursions of the analog signal does not go more negative than ground or more positive than 2.6V. The nominal VCM should generally be about 1.5V, but VCOM12 or VCOM34 can be used as a VCM source.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Applications Information
2.3 Internal Regulator
(Continued)
3.3 PD The PD pin, when high, holds the ADC12QS065 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 3 mW with a 65MHz clock.. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass pins 58, 59, 60, 21, 22 and 23 and is as listed in the Electrical Tables with the recommended components on the VREFT, VREFB and VCOM reference bypass pins. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance. 3.4 REFPD When high, the REFPD pin will power down the internal reference. With REFPD high, user must drive VREFT12, VREFT34 and VREFB12 & VREFB34 externally. With REFPD low, VREFT12, VREFT34, VREFB12 and VREFB34 are driven internally. 3.5 INTREF When INTREF is connected to VD , two internal reference choices are selectable through the VREF pin (pin 24). When INTREF is connected to DGND, an external reference must be applied to VREF.Section 2.1 Reference Pins 4.0 OUTPUTS The ADC12QS065 has four Low Voltage Differential Signaling (LVDS) Data Output pairs. Valid data is present at these outputs while the DEN pin is high and the PD pin is low. The OUTCLK and FRAME pins aid in data capture. LVDS signals provide a high level of immunity to common mode noise. The differential data signals consist of two 400mVpp signals that are 180 degrees out of phase. They should be terminated with a 100 resistor near the receiver.
The ADC12QS065 has an internal 1.8V regulator. The VREG pins (pins 32 and 48) should each be bypassed to AGND with a 1.0 F capacitor. 3.0 DIGITAL INPUTS Digital TTL/CMOS compatible inputs consist of CLK, DEN, PD, REFPD, and INTREF. 3.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range of 20 MHz to 65 MHz with rise and fall times of 2 ns or less. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90. The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). 3.2 DEN When the DEN pin is high, the LVDS outputs are in the active state. When low, the output pins are in a high impedance state. The ADC12QS065 will continue to convert whether the pin is high or low, but the output can not be read while the pin is low.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Applications Information
(Continued)
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FIGURE 4. Application Circuit using Transformer Drive Circuit
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Applications Information
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FIGURE 5. Differential Op-Amp Drive Circuit of Figure 4 5.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 F capacitor and with a 0.1 F ceramic chip capacitor within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series inductance. As is the case with all high-speed converters, the ADC12QS065 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off. 6.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12QS065 between these areas, is required to achieve specified performance. The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the ADC12QS065's other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. The LVDS output pairs should be routed with a 100 impedance trace, and should be terminated at the receiver with a 100 resistor. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90 to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90 crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Traces for the input channels should be routed away from each other as much as possible, with Ground plane between channels, to help minimize crosstalk. 7.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Applications Information
(Continued)
tree shown in Figure 6. The gates used in the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be prevented. Best performance will be obtained with a differential input drive, compared with a single-ended drive, as discussed in Sections 1.3.1 and 1.3.2. As mentioned in Section 5.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90 crossings have capacitive coupling, so try to avoid even these 90 crossings of the clock line.
each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12QS065, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100. Using an inadequate amplifier to drive the analog input. As explained in Section 1.3, the capacitance seen at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in Figure 4 and Figure 5) will improve performance. The LMH6702 and the LMH6628 have been successfully used to drive the analog inputs of the ADC12QS065.
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FIGURE 6. Isolating the ADC Clock from other Circuitry with a Clock Tree 8.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 47 to 100 in series with any offending digital input, close to the signal source, will eliminate the problem. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. Be careful not to overdrive the inputs of the ADC12QS065 with a device that is powered from supplies outside the range of the ADC12QS065 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, VREF should be in the range of 0.8V VREF 1.2V Operating outside of these limits could lead to performance degradation. Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in Section 1.2, these pins should be bypassed with 0.1 F capacitors to ground at VRMA and VRMB and with a series RC of 1.5 and 1.0 F between pins VRPA and VRNA and between VRPB and VRNB for best performance. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance.
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ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted
64-Lead TQFP Package Ordering Number ADC12QS065CIVS NS Package Number VECO64A
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