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V-Data
Synchronous DRAM General Description
The VDS8608A8A are four-bank Synchronous DRAMs organized as 8,388,608 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications
VDS8608A8A
8M x 8 Bit x 4 Banks Features
*JEDEC standard LVTTL 3.3V power supply *MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) *4 banks operation *All inputs are sampled at the positive edge of the system clock *Burst Read single write operation *Auto & Self refresh *DQM for masking *8192 Refresh Cycles *Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No. VDS8608A8A-75 VDS8608A8A-75A Frequency 133Mhz-333 133Mhz-222 Interface LVTTL LVTTL Package 400mil 54pin TSOPII 400mil 54pin TSOPII
Pin Assignment
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS BS0 BS1 A10/AP A0 A1 A2 A3 VCC
1 2 3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54
53
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ7 VssQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
54-pin plastic TSOP II 400 mil
Rev 1.0 December, 2001
1
V-Data
Pin Description
PIN CLK CKE NAME System Clock Clock Enable FUNCTION Active on the positive edge to sample all inputs.
VDS8608A8A
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM
A0~A12
Address
Row / Column address are multiplexed on the same pins. Row address : A0~A12 Column address : A0~A9
BS0~BS1 Banks Select
Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time.
DQ0~DQ7 Data /RAS /CAS /WE Row Address Strobe Column Address Strobe Write Enable
Data inputs / outputs are multiplexed on the same pins. Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low Enables write operation and row recharge. Power and Ground for the input buffers and the core logic. Power supply for output buffers. This pin is recommended to be left No Connection on the device.
VCC/VSS Power Supply/Ground VCCQ/VSSQ Data Output Power/Ground NC No Connection
Block Diagram
CLK CKE Address
Clock Generator
Bank3 Bank2 Bank1
RowDecoder
Mode Register
Address Buffer & Refresh Counter
Bank0
Amplifier
DQM
CommandDecoder
/RAS /CAS /WE
ControlLogic
/CS
DataLatch
Column Address Buffer & Refresh Counter
ColumnDecoder
DataControlCircuit
DQ
Rev 1.0 December, 2001
2
V-Data
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, Vout VCC, VCCQ TSTG PD IOUT Value -0.3 ~Vcc+0.3 -0.3 ~ 4.6 -55 ~ +150 1 50
VDS8608A8A
Unit V V W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Supply voltage Input logic high voltage Input logic low voltage Symbol VCC, VCCQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 Max 3.6 VCC+0.3 0.8 Unit V V V 2 2 Note
Note : 1. VIH (max)=Vcc/ VccQ+1.2V for pulse width 5ns acceptable. 2.VIL(min)=-Vss/ VssQ-1.2V for pulse width 5ns acceptable.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Note: 1. 3.15V VDD 3.6V is applied for VDS8608A8A55. Symbol VIH / VIL Vtrip TR / tF Voutfef CL Value 2.4 / 0.4 1.4 2 1.4 50 Unit V V Ns V pF 2 Note
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit.
Rev 1.0 December, 2001
3
V-Data
Capacitance
TA=25, f-=1Mhz, VCC=3.3V Parameter Input capacitance CLK A0~A12,BS0 ,BS1,CKE,/CS,/RAS, /CAS,/WE,LDQM Data input / output capacitance CI/O Pin Symbol Cclk Cl1 Min -
VDS8608A8A
Max 3.5 3.8
Unit pF pF
6.5
pF
Output load circuit
3.3V
50ohms
Output
Z= 50 ohms
50pF
DC Characteristics I
Parameter Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL Symbol Min -5 -5 2.4 Max 5 5 0.4 Unit uA uA V V IOH = -4mA IOL = 4mA Note
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6.
Rev 1.0 December, 2001
4
V-Data
DC Characteristics II
Speed Parameter Symbol Test condition 75 Burst length=1, One bank active Operating Current Precharge standby current in power down mode ICC2PS CKEVIL(max), tCK= CKEVIH(min), /CSVIH(min), tCK=min input signals are Precharge standby current in Non power down mode ICC2S Input signals are stable. No Operating Current ICC3 in power down mode Burst mode operating ICC4 current Auto refresh current ICC5 All banks active ICC6 Self refresh current ICC6L Lower Power 1 Standard 3 3 All banks active tCKtCK(min),IOL=0 mA 170 160 ICC3P CKEVIL(max), tCK=min CKEVIL(max), tCK= tCKtCK(min),IOL=0 mA 100 95 60 10 55 10 ICC2 changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKEVIH(min), tCK= 10 10 40 35 1 1 ICC1 tRCtRC(min),IOL=0mA CKEVIL(max), tCK=min 80 75 75A
VDS8608A8A
Unit
Note
1
ICC2P
1
1
mA
1
2
Note: 1. ICC1 and ICC4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tCK is shown at AC characteristics.
Rev 1.0 December, 2001
5
V-Data
AC Characteristics
Speed Parameter Symbol Min System clock Cycle time /CAS Latency = 2 /CAS Latency = 3 tCK2 tCK3 tCHW tCLW tAC2 tAC3 tWR2 tWR3 tRC tRCD tRAS tRP tRRD tCCD tDS tDH tAS tAH tCKS tCKH tCMS tCMH tOH tHZ tLZ tRSC tREF 7.5 7 56 15 40 15 15 1 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 3 3 0 14 64 7 100K 7.5 7 2.5 2.5 5.4 5.4 10 7.5 65 20 45 20 15 1 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 3 3 0 15 64 7.5 100K 7.5 75 Max 1000 1000 Min 10 7.5 2.5 2.5 75A Max 10 7
VDS8608A8A
Unit
Note
ns ns ns ns 1 1 2
Clock high pulse width Clock low pulse width Access time form /CAS Latency = 2 clock Write Recovery Time /RAS cycle time /RAS to /CAS delay /RAS active time /RAS precharge time /RAS to /RAS bank active delay /CAS to /CAS delay Data - input setup time Data - input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Mode register Set Cycle Time Refresh time /CAS Latency = 3 /CAS Latency = 2 /CAS Latency = 3
ns ns ns ns ns CLK ns ns ns ns ns ns ns ns ns ns ns ns ms 1 1 1 1 1 1 1 1
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit.
Rev 1.0 December, 2001
6
V-Data
Command Truth-Table
Command Mode Register Set No Operation Bank Active Read H Read with Auto Precharge Write Write with Auto Precharge Precharge All Bank H Precharge select Bank Burst Stop DQM Auto Refresh Entry Self Refresh Exit L H L H Entry Precharge Power down Exit L H L H Entry Clock Suspend Exit L H H L L V X V V X H X H X H X X H L L H H X H X H X X H X H X H X X H H H H H L L L H X L H X L L X L L X H H X X H L X V X X X L L H L X X H X L H L L X X L H L H X CKEn-1 H H H CKEn X X L X L H L H H H H X /CS L H /RAS L X /CAS L X /WE L X X DQM X
VDS8608A8A
ADDR A10/AP OP code X RA L CA H CA L H H L X X X
BA
V V
V X V
X
X
X
Rev 1.0 December, 2001
7
V-Data
Package Information
VDS8608A8A
SYMBOL A A1 A2 B c D HE E e L L1 MIN. 0.05 ----- 0.24 -----
22.12
11.56 10.06 ----- 0.40
S
0
MILLIMETER NOM. 0.10 1.00 0.32 0.15 22.22 11.76 10.16 0.80BSC 0.50 0.80REF 0.71REF -
MAX. 1.20 0.15 ----- 0.40 ------
22.62
11.96 10.26 ----- 0.60
MIN. 0.002 ----- 0.009 ----- 0.871 0.455 0.396 ----- 0.016
INCH NOM. 0.004 0.039 0.012 0.005
0.875
MAX. 0.047 0.006 ----- 0.016 -----
0.905
8
0
0.463 0.400 0.031 0.020 0.032REF 0.028REF -
0.471 0.404 ----0.024
8
400mil 54pin TSOP II Package
Rev 1.0 December, 2001
8

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