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  Datasheet File OCR Text:
 January 15, 2003 Rev 2.1
IRACV201
AcceleratorTM Verilog Code Development Tool
Features
Accelerator architecture AC servo development system TM ServoDesigner graphical user interface for configuration, control and monitoring Verilog code library grouped into three segments: FOC blocks Motion peripheral blocks Communication blocks Bilinear transformation based discretization TM Rapid prototyping with Accelerator Hardware Platform
TM
Complete Motion Control Verilog Library
Product Summary
Flexible Target Silicon Field Orientation Control execution Versatile PWM module Communication options
FPGA or ASIC 4 usec (135 sysclk)
Sine or Space Vector PWM Fast SPI (5 MHz), UART (57.6K or 1Mbit)
Description
IRACV201 is a Verilog code development tool including a rich Verilog library and graphical user interface. The tool set is designed to facilitate motion control algorithm development including motion peripheral and communication modules. Flexible configuration allows the user to quickly realize hardware on an FPGA to achieve a high performance AC motor control system.
Closed Loop Velocity Control, Sequencing Control Update Rate = PWM carrier frequency / 2
EXT_REF O
I1 x I2 I1 I3 I3 I2
4096
Closed Loop Current Control Update Rate = PWM carrier frequency x1 or x 2
DCV_FDBK Feedforward path enable VQLIM - VQLIM 2 Optional Current Sense
2 MUX 8 channel Serial A/D Interface
+/-16383 = +/-max_speed
INT_VQ SPDKI SPDKP INT_REF Reference Select Velocity Control Enable REF scale
ADS7818 A/D interface DC bus dynamic brake control
CNVST CLK DATA
BRAKE
CURKI IQREF CURKP
+
RAMP
GSenseL GSenseU ModScl VQS 6
START STOP DIR FLTCLR SYNC FAULT PWM ACTIVE RCV SND RTS CTS
+
-
PI
+
IQLIMIDREF
-
PI
+
VQ
Sequence Control
+
Accel Rate Decel Rate
PI INT_VD - VDLIM VDLIM Slip gain 4096
VD
e
+
j
VDS
Space Vector PWM
Dea d time
Gate Signals
FAULT
IQLIM+
VD enable Slip gain enable
PWMmode 2Pen Dtime PWMen AngleScale MaxEncCount SpdScale InitZval 3 Encoder A/B/Z Encoder Hall A/B/C
RS232C/ RS422 Interface
I2
Configuration Registers
Host Register Interface
I1
I1 x I2 I3
I3 O
dt
0
+
Quadrature Decoding
3 EncType InitZ Optional CurrentSense Zpol 4096
SCK SDO SDI CS
SPI Slave Interface
IQ scale
Data Address Control
17
Parallel Interface
Monitoring Registers
IQ
I2 O
I1 x I2 I3
I3 I1
ID
O I2
I1 x I2 I1 I3 I3
4096
e
j
IV
2/3
IR2175 interface IR2175 interface
Current Offset W Current Offset V
Motor Phase Current V Motor Phase Current W
IW
ID scale
Communication Modules
+/-16383 = +/-4X of rated current for IQ +/-4095 = +/-rated ID for IM field flux
INT_DAC1 INT_DAC2 INT_DAC3 INT_DAC4
DAC_PWM1
4ch DAC module
DAC_PWM2 DAC_PWM3 DAC_PWM4
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
1


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