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NCP5355 12 V Synchronous Buck Power MOSFET Driver
The NCP5355 is a dual MOSFET gate driver optimized to drive the gates of both high- and low-side Power MOSFETs in a Synchronous Buck converter. The NCP5355 is an excellent companion to multiphase controllers that do not have integrated gate drivers, such as ON Semiconductor's NCP5314 or NCP5316. This architecture provides the power supply designer greater flexibility by being able to locate the gate drivers close to the MOSFETs. Driving MOSFETs with a 12 V source as opposed to a 5.0 V can significantly reduce conduction losses. Optimized internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate MOSFET drain voltages as high as 26 V. Both gate outputs can be driven low by applying a low logic level to the Enable (EN) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP5355 has the same pinout as the NCP5351 5.0 V Gate Driver.
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8 8 1 SO-8 D SUFFIX CASE 751 1 8 8 1 SO-8 EP D SUFFIX CASE 751AC 1 5355 ALYW 5355 ALYW
* * * * * * * * * * *
8.0 V - 14 V Gate Drive Capability 2.0 A Peak Drive Current Rise and Fall Times < 15 ns Typical into 3300 pF Propagation Delay from Inputs to Outputs < 30 ns Adaptive Nonoverlap Time Optimized for Large Power MOSFETs Floating Top Driver Accommodates Applications Up to 26 V Undervoltage Lockout to Prevent Switching when the Input Voltage is Low Thermal Shutdown Protection Against Overtemperature TG to DRN Pull-Down Resistor Prevents HV Supply-Induced Turn-On of Top MOSFET BG to PGND Pull-Down Resistor Prevents Transient Turn On of Bottom MOSFET Internal Bootstrap Diode Reduces Parts Count and Total Solution Cost
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
DRN TG BST CO 1 8 PGND BG VS EN
ORDERING INFORMATION
Device NCP5355D NCP5355DR2 NCP5355PDR2 Package SO-8 SO-8 SO-8 EP Shipping 98 Units/Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
June, 2004 - Rev. 6
Publication Order Number: NCP5355/D
NCP5355
5V VS 5 V Regulator 5V Overtemp. Shutdown 5V 5V VS 5V - + Level Shift Driver UVLO 8.0/7.0 V 5V Nonoverlap 30 ns 5V CO 5V 2.0 mA EN Nonoverlap 30 ns 5V 5V 5V Level Shift Driver BG VS VS 20 k 30 k 30 k 20 k 100 k DRN TG 5V BST
PGND 5V
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin 1 Pin Symbol DRN Description The switching node common to the high and low-side FETs. The high-side (TG) driver and supply (BST) are referenced to this pin. Driver output to the high-side MOSFET gate. Bootstrap supply voltage input. In conjunction with an internal diode to VS, a 0.1 mF to 1.0 mF ceramic capacitor connected between BST and DRN develops supply voltage for the high-side driver (TG). Logic level control input produces complementary output states - no inversion at TG; inversion at BG. Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation ensues. No connect defaults EN high. Note: maximum high input is 5.0 V. Power supply input. A 0.1 mF to 1.0 mF ceramic capacitor should be connected from this pin to PGND. Driver output to the low-side (synchronous rectifier) MOSFET gate. Ground.
2 3
TG BST
4
CO
5
EN
6
VS BG PGND
7 8
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NCP5355
MAXIMUM RATINGS
Rating Operating Junction Temperature, TJ Package Thermal Resistance: SO-8 Junction-to-Case, RqJC Junction-to-Ambient, RqJA Package Thermal Resistance: SO-8 EP Junction-to-Ambient, RqJA (Note 2) Storage Temperature Range, TS Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) JEDEC Moisture Sensitivity Value Internally Limited 45 165 50 -65 to 150 230 peak 1 Unit C C/W C/W C/W C C -
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. 60 seconds maximum above 183C. 2. Ratings applies when soldered to an appropriate thermal area on the PCB.
MAXIMUM RATINGS
Pin Symbol VS BST DRN Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Switching Node (Bootstrap Supply Return) High-Side Driver Output (Top Gate) Low-Side Driver Output (Bottom Gate) TG and BG Control Input Enable Input Ground VMAX 15 V 30 V wrt/PGND 15 V wrt/DRN 26 V VMIN -0.3 V -0.3 V wrt/DRN -1.0 V DC -5.0 V for 100 ns -6.0 V for 20 ns -0.3 V wrt/DRN -0.3 V -0.3 V -0.3 V 0V ISOURCE NA NA 2.0 A Peak (< 100 ms) 250 mA DC 2.0 A Peak (< 100 ms) 250 mA DC 2.0 A Peak (< 100 ms) 250 mA DC 1.0 mA 1.0 mA 2.0 A Peak (< 100 ms) 250 mA DC ISINK 2.0 A Peak (< 100 ms) 250 mA DC 2.0 A Peak (< 100 ms) 250 mA DC NA
TG BG CO EN PGND NOTE:
30 V wrt/PGND 15 V wrt/DRN 15 V 5.5 V 5.5 V 0V
2.0 A Peak (< 100 ms) 250 mA DC 2.0 A Peak (< 100 ms) 250 mA DC 1.0 mA 1.0 mA NA
All voltages are with respect to PGND except where noted.
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NCP5355
ELECTRICAL CHARACTERISTICS (Note 3) (0C < TJ < 125C; 9.2 V < VS <13.2 V; 9.2 V < VBST < 26 V; VEN = Float;
CLOAD = 3.3 nF; unless otherwise noted.) Parameter DC OPERATING SPECIFICATIONS POWER SUPPLY VS Quiescent Current, Operating VBST Quiescent Current, Operating UNDERVOLTAGE LOCKOUT Start Threshold Stop Threshold Hysteresis CO INPUT CHARACTERISTICS High Threshold Low Threshold Input Bias Current EN INPUT CHARACTERISTICS High Threshold Low Threshold Input Bias Current THERMAL SHUTDOWN Overtemperature Trip Point Hysteresis HIGH-SIDE DRIVER Peak Output Current Output Resistance (Sourcing) Note 4 Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125C, VBST - VDRN = 12 V, VTG = 10 V + VDRN Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125C, VBST - VDRN = 12 V, VTG = 2.0 V + VDRN - - 2.0 1.0 - - A W Note 4 Note 4 150 - 170 20 - - C C Both outputs respond to CO Both outputs are low independent of CO 0 < VEN < 5.0 V 2.0 - -7.0 - - -3.0 - 0.8 +2.0 V V mA - - 0 < VCO < 5.0 V 2.0 - - - - 0 - 0.8 1.0 V V mA VCO = 0 V VCO = 0 V VCO = 0 V 7.0 6.0 0.70 8.0 7.0 1.00 9.2 8.0 1.60 V V V VCO = 0 V or 4.5 V; No output switching VCO = 0 V or 4.5 V; No output switching - - 1.0 3.8 2.0 5.0 mA mA Test Conditions Min Typ Max Unit
Output Resistance (Sinking)
-
1.0
-
W
LOW-SIDE DRIVER Peak Output Current Output Resistance (Sourcing) Output Resistance (Sinking) CHARGE PUMP DIODE Forward Voltage Drop ID = 100 mA - 1.1 1.4 V Note 4 Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125C, VS = 12 V, VBG = 10 V Duty Cycle < 2.0%, Pulse Width < 100 ms, TJ = 125C, VS = 12 V, VBG = 2.0 V - - - 2.0 1.1 1.0 - - - A W W
3. All limits at temperature extremes are guaranteed by characterization using Standard Statistical Quality Control methods. 4. Guaranteed by design, not 100% tested in production.
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NCP5355
ELECTRICAL CHARACTERISTICS (Note 5) (0C < TJ < 125C; 9.2 V < VS <13.2 V; 9.2 V < VBST < 26 V; VEN = Float;
CLOAD = 3.3 nF; unless otherwise noted.) Parameter Symbol Test Conditions Min Typ Max Unit
AC OPERATING SPECIFICATIONS HIGH-SIDE DRIVER Rise Time Fall Time Propagation Delay Time, TG Going High (Nonoverlap Time) Propagation Delay Time, TG Going Low LOW-SIDE DRIVER Rise Time Fall Time Propagation Delay Time, BG Going High (Nonoverlap Time) Propagation Delay Time, BG Going Low trBG tfBG tpdhBG (Note 6) (Note 6) (Note 6) - - 15 10 10 30 20 20 55 ns ns ns trTG tfTG tpdhTG VBST - VDRN = 12 V, VS = 12 V (Note 6) VBST - VDRN = 12 V, VS = 12 V (Note 6) VBST - VDRN = 12 V, VS = 12 V (Note 6) - - 15 15 15 30 25 25 55 ns ns ns
tpdlTG
VBST - VDRN = 12 V, VS = 12 V (Note 6)
-
45
60
ns
tpdlBG
(Note 6)
-
35
55
ns
5. All limits at temperature extremes are guaranteed by characterization using Standard Statistical Quality Control methods. 6. AC specifications are guaranteed by characterization, not 100% tested in production.
VCO tpdlBG tpdlTG tfTG
VTG-VDRN trTG tpdhTG (Non-overlap) VBG tfBG trBG tpdhBG (Non-overlap) VDRN 5.0 V
Figure 2. Timing Diagram
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5
ATX 12 V
+
12 V 3.3 V
6 VS 4 CO 5 EN 8
ENABLE VID5 VID0 VID1
BST TG DRN PGND BG NCP5355
3 2 1 7
Figure 3. Application Diagram, 12 V to 1.4 V, 60 Amp, Four-Phase Converter
+
VCORE GND
32
31
30
29
28
27
26
VID2 VID3 VID4 3.3 V
1 2 3 4 5 6 7 8
VID1 VID0 VID5 ENABLE CS2N CS2P CS1N CS1P
25
PWRGD
VID2 VID3 VID4 PWRLS VFFB SS PWRGD DRVON
ILIM 24
23 22 21 20 19 18 17 6 VS 4 CO 5 EN 8
NCP5314
ROSC VCC GATE1 GATE2 GATE3 GATE4 GND
BST TG DRN PGND BG NCP5355
3 2 1 7
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NCP5355
SGND VDRP VFB COMP CS4N CS4P CS3N CS3P
10
12
13
14
15
SGND Near Socket VFFB Connection
NTC Near Inductor
6 VS 4 CO 5 EN 8
16
11
9
6
6 VS 4 CO 5 EN 8
BST TG DRN PGND BG NCP5355
3 2 1 7
BST TG DRN PGND BG NCP5355
3 2 1 7
NCP5355
APPLICATIONS INFORMATION
Enable Pin
The Enable pin allows logic level On/Off control of the NCP5355. A Logic Level Low (< 0.8 V) disables the part by forcing both TG and BG low. Bringing both gates low prevents the output voltage from ringing below ground at turn-off. A Logic Level High (> 2.0 V) enables the part by allowing CO to control TG and BG. If the Enable function is not being used, the Enable pin should be left unconnected. This will Enable the part by default, as the Enable pin will be internally pulled high by a 2.0 mA current. The maximum high voltage level is 5.0 V. Voltages greater than this may damage the part.
Undervoltage Lockout
where QTtopFETs is the sum of the Top MOSFETs total gate charge, DVBST is the maximum change in voltage across the bootstrap capacitor and is typically designed for a drop of less than a 1.0 V. For example, a circuit using one Top MOSFET with a typical QTtopFETs of 60 nC (at 12 V Vgs) and 1.0 V of droop would give a minimum value for CBST of 60 nF.
Internal or External Bootstrap Diode
Gates TG and BG are both held low until Vs reaches the UVLO Start Threshold of 8.0 V during startup. Vs exceeding the UVLO threshold allows CO to take control of both gates. If Vs falls below the UVLO Stop Threshold of 7.0 V, both gates are then forced low until Vs again exceeds the Start Threshold.
Supply Capacitor Selection
A 1.0 mF ceramic capacitor (CVS in Figure 4) should be located close to the Vs supply pins to provide peak current and to reduce noise. A small 1.0 W to 5.0 W resistor (RVS in Figure 4) may also be added in series with CVS to provide additional filtering in noisy environments.
Bootstrap Capacitor Selection
For convenience, a bootstrap diode is internally provided by the NCP5355. This internal diode reduces system cost and parts count. However, this diode will have higher losses than a standard small signal switching or Schottky diode. By using an external Schottky diode (DBST in Figure 4) a small improvement in efficiency can be achieved as illustrated by the graph in Figure 5. While the difference in efficiency is relatively small, this difference represents heat loss in the driver and on average driver temperature may be reduced by about 10C if using an external diode. If an external diode is used, it should be a Schottky or switching diode. (For example: ON Semiconductor Part Number BAT54HT1 or BAS16HT1.)
Adaptive Nonoverlap
The size of the Top MOSFET bootstrap capacitor (CBST in Figure 4 ) is determined from the following equation:
CBST w QTtopFETs DVBST
The NCP5355 includes adaptive nonoverlap protection to prevent top and bottom MOSFET cross conduction. When CO goes low signaling TG to turn off the top MOSFET, BG does not go high until the switch node (DRN pin) has fallen below 5.0 V and a fixed amount of delay (tpdhBG) has elapsed. This ensures that the top MOSFET is off before the bottom MOSFET is turned on.
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NCP5355
VIN = 12 V DBST (Optional)
CBST 1.0 m Qtop NTD60N03 Switch Node VCORE = 1.40 V LOUT
+
RVS 2.2 CO 4 CO 5 EN 6 VS BST TG DRN PGND BG 3 2 1 8 7
RGU 2.2
CVS 1.0 m
U1 NCP5355
Qbottom1 NTD80N02 Qbottom2 NTD80N02
CSN 4700 p CIN 4.7 m RSN 2.2
COUT
Figure 4. Typical NCP5355 Application
86 85 84 83 82 Efficiency (%) 81 80 79 78 77 76 75 74 73 10 15 IO (A) 20 25 Internal Diode External Diode Internal Diode External Diode 200 kHz, Series 2 400 kHz, Series 4 600 kHz, Series 8 Internal Diode External Diode
Figure 5. Efficiency With and Without an Added External Bootstrap Diode, See Figure 4 for Test Circuit
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NCP5355
When CO goes high signaling BG turn off the Bottom MOSFET, TG does not go high until BG has fallen below a threshold of 5.0 V and a fixed amount of time has elapsed (tpdhTG). However, caution must be observed if too much gate resistance and inductance is introduced into the path between the IC and the gate of the low MOSFET. A condition can occur where the NCP5355 will sense that BG has fallen below 5.0 V while the gate end of the MOSFET still has not fallen low enough to turn off the device. This parasitic gate impedance between the driver and MOSFET can reduce the nonoverlap time, and result in shoot-through currents.
Power Dissipation Switch Node Overshoot and Ringing
Driver power dissipation may be approximated by the following equation:
Ploss + fSW @ Vs @ (1.5 @ QTtopFETs ) QTbottomFETs) ) Vs @ Is
Due to the high current sourcing capability of the NCP5355, increased overshoot and ringing may be noticed at the switch node (DRN pin). This can be reduced in several ways. One is by adding a low ESR 1.0 mF-10 mF ceramic capacitor (CIN in Figure 4) from VIN to ground near each Qtop. This capacitor should be located in such a manner as to reduce the loop area of the switch node as shown in Figure 6. A smaller loop area from CIN+ to Qtop to Qbottom and back to CIN- will reduce the amount of ringing by reducing the PCB inductance. If further reduction in overshoot and ringing is desired, a Top MOSFET gate drive resistor may be added (RGU in Figure 4) to slow the turn-on of the Top MOSFET without increasing the turn-off time.
Layout Guidelines
where fSW Vs QTtopFETs
is the switching frequency, is the supply voltage, is the sum of the Top MOSFETs total gate charge, QTbottomFETs is the sum of the Bottom MOSFETs total gate charge Is is the supply quiescent current, typically around 5.0 mA The 1.5 factor is a result of the internal bootstrap diode whose loss is equivalent to the charge lost in turning on the Top MOSFET. If an external diode is used to improve efficiency, the 1.5 factor is replaced with 1.0 as this loss will now occur outside the package. Safe design practice requires limiting the SO8 device power dissipation to around 700 mW. Higher frequency designs may require limiting the supply voltage (Vs) to less than 12 V to maintain this limit.
When designing any switching regulator, the layout is very important for proper operation. Gate drivers experience high di/dt during switching, and the inductance of the gate drive traces need to be minimized. Gate drive traces should be kept as short and wide (25 to 30 mils) as practical, and should have a return path directly below the gate trace. The use of a ground plane is a desirable way to return ground signals. Component location is very important. The boost and the Vs capacitor are the most critical, and need to be placed as close as possible to the driver IC pins (CVS and CBST in Figure 4) as shown in Figure 6. Higher frequency designs will magnify any layout problems, and added attention to these guidelines should be observed in designs above 250 kHz.
QTOP CIN CVS RVS
DBST U1
RGU QBOTTOM CBST
Figure 6. Typical NCP5355 PCB Layout
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NCP5355
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE AB
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
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NCP5355
PACKAGE DIMENSIONS
SO-8 EP CASE 751AC-01 ISSUE O
2X
0.10 C A-B D A
8 5
D
EXPOSED PAD 5
F
8
DETAIL A
E1
2X
E
G
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_
0.10 C D
PIN ONE LOCATION
0.10 C
8X
0.10 C
SEATING PLANE
c A1
C
SIDE VIEW
SECTION A-A
H
GAUGE PLANE
0.25
L (L1) DETAIL A q
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CCC EEE CCC EEE
EE EE
1
2X 4
0.20 C
8X b 0.25 C A-B D
4
1
h
e
BOTTOM VIEW A A
B TOP VIEW
END VIEW
A2
A
(b) c1
b1
DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q
NCP5355
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP5355/D

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