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SAA7893HL
Super audio media player
Rev. 02 -- 26 February 2003 Product data
1. General description
Thanks to the superior sound quality and multichannel capability of Super Audio CD (SACD) technology, multimedia devices such as DVD players and home cinema systems are incorporating SACD functionality. Philips' Super Audio Media Player (SA-MP) provides a flexible, state-of-the-art solution for SACD playback on DVD architectures. Built around the SAA7893HL SACD processor, SA-MP system solution delivers complete SACD functionality, avoiding the need for continual redesign and re-integration of SACD into various applications. The system is completed with a single 64 Mbit SDRAM and has extensive software processing options, resulting in low total system cost (see Figure 1). With integrated support for multiple loaders, the SAA7893 supports a variety of DVD platforms. High level and standard software interfaces - optimized for easy design-in - further enhance adaptability, enabling designers to build SACD players on many different hardware and software platforms. This ensures that the SA-MP can be left unchanged even if the SACD playback hardware is altered, again minimizing development effort.
DVD HOST IC DVD SW STACK
ANNEX J+ PLAYBACK API SACD TEXT AND DATA API SPEAKER SETUP API
SW
PSP DECODER SACD DEMUX DST DECODER BE SWITCH
DSD POSTPROCESSOR PCM CONVERTER DSD CONVERTER DAC SWITCH
D/A
HW SAA7893HL SA-MP
HW
MGU724
DVD host
64 Mbit SDRAM
DVD host DAC out
Fig 1. General block diagram.
Philips Semiconductors
SAA7893HL
Super audio media player
1.1 Hardware
The SA-MP hardware consists of the SAA7893HL device. A typical HW block diagram of a DVD system incorporating the SAA7893HL is shown in Figure 2. The SAA7893HL takes sector data from the front-end. The front-end is controlled by the DVD host via the SA-MP software stack. The SAA7893HL uses one 64 Mbit SDRAM for audio data buffering and storage of SACD TOCs. The front-end timing can be fully asynchronous from all clocks. The 6-channel DAC outputs of the DVD host are routed via the SAA7893HL which provides a DAC switch function between SACD mode and DVD mode. The audio outputs of the SAA7893HL operate on the system audio clock. The DVD back-end communicates with the SAA7893HL via a host bus. The system clock and the system audio clock are allowed to be asynchronous.
NVRAM
SDRAM
control DVD BACK-END
video 27 MHz audio clock
FRONTdata END
host bus
ROM
PLL
audio EFM SAA7893HL audio
SDRAM
MGU726
Fig 2. Hardware block diagram.
1.2 Software
The SA-MP software is delivered in the form of a library in the development environment of the DVD host. The SA-MP software has been developed in ANSI-C using conventional software technology to allow easy integration into any development environment. A typical software block diagram of a DVD system incorporating SA-MP is shown in Figure 3. At the device driver and HW-level, SA-MP interfaces with the SAA7893HL and a front-end driver. At the infrastructure level, SA-MP interfaces with an Operating System Abstraction layer (OSA). At the application level, SA-MP provides a high-level playback and post-processing interface which is easy to integrate into typical applications.
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Product data
Rev. 02 -- 26 February 2003
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Philips Semiconductors
SAA7893HL
Super audio media player
APPLICATION LAYER - "SACD PLAYER BEHAVIOUR" Annex J+
MEDIA PLAYERS
SA-MP
POSTPROCESSING LOADER etc.
UI SUBSYSTEM "LOOK-AND-FEEL"
INFRASTRUCTURE (OSA)
DEVICE DRIVERS SAA7893HL
DEVICE DRIVERS
UI DEVICE DRIVERS
MGU725
HW
HW
I/O PERIPHERALS
Fig 3. Software block diagram.
2. Features
2.1 Components
s SAA7893HL second generation SACD processor IC s SA-MP Annex J+ level software stack.
2.2 HW interfaces
s Front-end, supports 3 types: x UDE x FEC x I2S-bus s Flexible PSP detection from EFM signal with AGC, without EFM clock (digital PLL) s (DVD-)host bus, supports 3 types: x Separate address/data bus (SAD16) with 16-bit data bus (3 different modes) x Multiplexed address/data bus (MAD16) with 16-bit data bus (2 different modes) x Separate address/data bus (SAD08) with 8-bit data bus (1 mode) s 16-bit 100 MHz SDRAM interface supports one 64 Mbit device s 6-channel I2S-PCM audio input 44.1, 48, 88.2, 96, 176.4 or 192 kHz at 16-bit or 24-bit s 6-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning configuration s 2-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning configuration s Audio clock reference 256fs, 384fs, 512fs or 768fs s System clock 27 to 35 MHz.
2.3 SW interfaces
s Annex J+ level playback interface
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Product data
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SAA7893HL
Super audio media player
s High-level audio post-processing control s SACD data interface s System configuration
2.4 System
s Full SACD Menu TOC and Area TOC storage in VBR s Front-end clock asynchronous to other clocks
2.5 System configuration
s D/A converters: x DSD and PCM selectable pin sharing configuration x DSD clock polarity s Audio and system clock asynchronous s Front-end type
2.6 SACD playback
s SACD playback: x Multi-channel x 2-channel s PSP processing s Decrypting and demultiplexing s VBR management s DST decoding s Fade processing s Annex J+ level software interface: x Stop x Pause x Play x Fast forward x Fast reverse x Next/previous track x Program and play playlist x Repeat (Track, All or AB) x Shuffle x Introscan x Time search
2.7 Audio postprocessing
s DSD Bass Management with support of: x Dolby(R) configuration 0 (LLL1) x Dolby(R) configuration 1 (SSS1) x Dolby(R) configuration 2 (LSS0) s Programmable bass filter frequency and slope:
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SAA7893HL
Super audio media player
s
s s s
s
x 60, 80, 100, 120 Hz x 12, 18, 24 dB/Oct (other frequencies or slopes are possible on customer request) DSD down mixing: x 2/2 x 3/0 x 2/0 x separate 2/0 DSD attenuation function 0 to -90 dB, programmable per channel DSD delay function total 65 ms (approximately 20 meters), programmable per channel 6-channel PCM input: x 44.1, 88.2, 176.4, 48, 96 or 192 kHz at 16-bit or 24-bit x PCM to DSD upsampling with 3 programmable Sigma-Delta and anti-aliasing filter modes x Attenuation and delay as with DSD DSD to PCM conversion 88.2, 176.4 kHz at 24-bit.
2.8 SACD data and text
s s s s s s Album info Disc info Album or disc text Area text Track data Track text.
2.9 General
s s s s s s E-JTAG for board test and debug 3.3 V pad supply voltage 1.8 V core supply voltage 1.8 V analog supply voltage LQFP128 package 0.18 m CMOS process.
3. Applications
s Consumer DVD players s Home cinema s Car audio systems.
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SAA7893HL
Super audio media player
4. Ordering information
Table 1: Ordering information Package Name SAA7893HL LQFP128 Description plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm2 Version SOT425-1 Type number
5. Block diagram
Figure 4 shows the block diagram of the SAA7893HL with all defined functions.
to host host_sel
HF AGC ADC
HOST INTERFACE MEMORY MANAGER
FRONTEND INTERFACE data-bus
REGISTER HOST INTERFACE
SAA7893HL
PSP-KEY DECODER key control PI-bus
DECRYPTION/ SECTOR PROCESSOR
DEMUX
8-CHANNEL DSD2PCM CONVERSION
PI-BUS CONTROL SDRAM INTERFACE
SACD AUDIO INTERFACE
2, 5 or 6-channel LOSSLESS DECODER
SPEAKER SETUP VOLUME CONTROL DELAY
SWITCH MATRIX
to DSD/PCM DAC
MBL615
to 64 Mbit SDRAM
sys_clk 27-35 MHz
aud_clk 256/384/512/768*fs
external PCM
Fig 4. Block diagram.
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Super audio media player
6. Pinning information
6.1 Pinning
121 DSD_PCM_11 119 DSD_PCM_10 120 DSD_PCM_9 117 DSD_PCM_8 116 DSD_PCM_7 115 DSD_PCM_6 114 DSD_PCM_5 113 DSD_PCM_4 111 DSD_PCM_3 110 DSD_PCM_2 109 DSD_PCM_1 108 DSD_PCM_0
107 D_DQ[15]
104 D_DQ[14]
112 GND_IO6
118 VCC_IO6
106 VCC_IO5
105 D_DQ[0]
103 D_DQ[1] 102 D_DQ[13] 101 D_DQ[2] 100 D_DQ[12] 99 GND_IO5 98 D_DQ[3] 97 D_DQ[11] 96 D_DQ[4] 95 D_DQ[10] 94 D_DQ[9] 93 D_DQ[6] 92 VCC_IO4 91 D_DQ[8] 90 D_DQ[7] 89 D_LDQM 88 D_UDQM 87 D_DQ[5] 86 D_clk 85 VCC_Core2 84 GND_Core2 83 GND_IO4 82 D_CASn 81 D_RASn 80 D_Wen 79 D_ADDR[11] 78 D_ADDR[12] 77 D_ADDR[9] 76 VCC_IO3 75 D_ADDR[13] 74 D_ADDR[8] 73 D_ADDR[10] 72 D_ADDR[7] 71 D_ADDR[0] 70 D_ADDR[6] 69 GND_IO3 68 D_ADDR[1] 67 D_ADDR[5] 66 D_ADDR[2] 65 D_ADDR[4] D_ADDR[3] 64
MCE016
H_A[1] H_DQ[15] H_DQ[14] GND_IO1 H_DQ[13] H_DQ[12] H_DQ[11] H_DQ[10] H_DQ[9]
1 2 3 4 5 6 7 8 9
VCC_IO1 10 H_DQ[8] 11 H_DQ[7] 12 H_DQ[6] 13 H_DQ[5] 14 H_DQ[4] 15 H_DQ[3] 16 GND_IO2 17 H_procclock 18 VCC_Core1 19 GND_Core1 20 sys_clk 21 H_DQ[2] 22 H_DQ[1] 23 H_CSn 24 H_DQ[0] 25 H_RWn 26 H_WAIT 27 H_IRQn 28 aud_clk 29 PCM_dclk_in 30 PCM_wclk_in 31 VDDA 32 VSSA 33 biasin 34 Agcinp 35 Adcrefl 36 VCC_IO7 37 GND_IO7 38 PCM_CeLf_in 39 PCM_LeRi_in 40 PCM_LsRs_in 41 B_FLAG/SERR 42 B_SYNC/Sync 43 B_WCLK/SENB 44 B_DATA/Be_dat(0) 45 B_BCLK/SDCLK 46 UDE_req 47 Data_req 48 Be_dat(1) 49 Be_dat(2) 50 Be_dat(3) 51 Be_dat(4) 52 Be_dat(5) 53 Be_dat(6) 54 Be_dat(7) 55 TRST 56 TMS 57 VCC_IO2 58 TDO 59 TDI 60 TCK 61 H_sel[0] 62 H_sel[1] 63
122 RESETn
123 H_A_sel
128 H_A[2]
127 H_A[3]
126 H_A[4]
125 H_A[5]
124 H_A[6]
SAA7893HL
Fig 5. Pin configuration.
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Super audio media player
6.2 Pin description
Table 2: Symbol H_A[1] H_DQ[15] H_DQ[14] GND_IO1 H_DQ[13] H_DQ[12] H_DQ[11] H_DQ[10] H_DQ[9] VCC_IO1 H_DQ[8] H_DQ[7] H_DQ[6] H_DQ[5] H_DQ[4] H_DQ[3] GND_IO2 H_procclock VCC_Core1 GND_Core1 sys_clk H_DQ[2] H_DQ[1] H_CSn H_DQ[0] H_RWn H_WAIT H_IRQn aud_clk PCM_dclk_in PCM_wclk_in VDDA VSSA biasin Agcinp Adcrefl VCC_IO7 GND_IO7 PCM_CeLf_in
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Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Type[1] IN I/O10 I/O10 GND_IO I/O10 I/O10 I/O10 I/O10 I/O10 VCC_IO I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 GND_IO IN VCC_core IN I/O10 I/O10 IN I/O10 IN O10 O10 IN IN IN VDDCO VSSCO APIO APIO APIO VCC_IO GND_IO IN Description address bus data bus data bus GND I/O pads data bus data bus data bus data bus data bus VCC I/O pads data bus data bus data bus data bus data bus data bus GND I/O pads host processor EMI interface clock core supply voltage system clock data bus data bus host chip select; active LOW data bus read = 1; write = 0 wait signal interrupt request; active LOW DSD audio clock PCM data clock PCM word clock VDD of ADC VSS of AGC and ADC; connected to substrate bias current input AGC positive input signal; HF in ADC decoupling VCC I/O pads GND I/O pads PCM data center or LFE
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GND_core core ground
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SAA7893HL
Super audio media player
Pin description...continued Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Type[1] IN IN IN IN IN IN IN IN O10 IN IN IN IN IN IN IN IN1 IN1 VCC_IO O10 IN1 IN IN IN O10 O10 O10 O10 O10 GND_IO O10 O10 O10 O10 O10 O10 VCC_IO O10 Description PCM data left or right PCM data left or right surround I2S-bus flag (EDC flag) sector sync or absolute time sync I2S-bus word clock or UDE data sense from host I2S-bus data or LSB data of parallel interface I2S-bus bit clock host request data from front-end; routed via the SAA7893HL data request for UDE front-end parallel data interface front-end parallel data interface front-end parallel data interface front-end parallel data interface front-end parallel data interface front-end parallel data interface front-end parallel data interface boundary scan reset boundary scan mode select VCC I/O pads output boundary scan data input boundary scan clock host select signals: SAD16, MAD16 and SAD08 host select signals: SAD16, MAD16 and SAD08 SDRAM address bus SDRAM address bus SDRAM address bus SDRAM address bus SDRAM address bus GND I/O pads SDRAM address bus SDRAM address bus SDRAM address bus SDRAM address bus SDRAM address bus SDRAM address bus VCC I/O pads SDRAM address bus
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Table 2: Symbol
PCM_LeRi_in PCM_LsRs_in B_FLAG/SERR B_SYNC/Sync B_WCLK/SENB B_DATA/Be_dat(0) B_BCLK/SDCLK UDE_req Data_req Be_dat(1) Be_dat(2) Be_dat(3) Be_dat(4) Be_dat(5) Be_dat(6) Be_dat(7) TRST TMS VCC_IO2 TDO TDI TCK H_sel[0] H_sel[1] D_ADDR[3] D_ADDR[4] D_ADDR[2] D_ADDR[5] D_ADDR[1] GND_IO3 D_ADDR[6] D_ADDR[0] D_ADDR[7] D_ADDR[10] D_ADDR[8] D_ADDR[13] VCC_IO3 D_ADDR[9]
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Pin description...continued Pin 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Type[1] O10 O10 O10 O10 O10 GND_IO VCC_core O10 I/O10 O10 O10 I/O10 I/O10 VCC_IO I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 GND_IO I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 VCC_IO I/O10 O10 O10 O10 O10 GND_IO O10 O10 O10 O10 O10 VCC_IO Description SDRAM address bus SDRAM address bus read or write row address select; active LOW column address select; active LOW GND I/O pads core supply voltage clock signal needed for SDRAM data bus DQ mask enable (upper) DQ mask enable (lower) data bus data bus VCC I/O pads data bus data bus data bus data bus data bus data bus GND I/O pads data bus data bus data bus data bus data bus data bus VCC I/O pads data bus 6-channel data output 6-channel data output 6-channel data output 6-channel data output GND I/O pads 6-channel data output 6-channel data output 6-channel clock/control 6-channel clock/control 2-channel clock/control VCC I/O pads
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Table 2: Symbol
D_ADDR[12] D_ADDR[11] D_Wen D_RASn D_CASn GND_IO4 GND_Core2 VCC_Core2 D_clk D_DQ[5] D_UDQM D_LDQM D_DQ[7] D_DQ[8] VCC_IO4 D_DQ[6] D_DQ[9] D_DQ[10] D_DQ[4] D_DQ[11] D_DQ[3] GND_IO5 D_DQ[12] D_DQ[2] D_DQ[13] D_DQ[1] D_DQ[14] D_DQ[0] VCC_IO5 D_DQ[15] DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 GND_IO6 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 VCC_IO6
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GND_core core ground
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Pin description...continued Pin 119 120 121 122 123 124 125 126 127 128 Type[1] O10 O10 O10 IN IN IN IN IN IN IN Description 2-channel data output 2-channel clock or control 2-channel data output asynchronous reset; active LOW address select address bus address bus address bus address bus address bus
Table 2: Symbol
DSD_PCM_10 DSD_PCM_9 DSD_PCM_11 RESETn H_A_sel H_A[6] H_A[5] H_A[4] H_A[3] H_A[2]
[1]
Explanation of input and output ports: IN: digital input port; all dedicated inputs are TTL tolerant. IN1: digital input port with internal pull-up resistor. I/O10: bidirectional port with 10 ns slew rate. O10: 3-state (in test mode) output port with 10 ns slew rate. APIO: analog input port. VDDCO: analog VDD port (1.8 V). VSSCO: analog VSS port. GND_IO: ground for I/O pads. VCC_IO: VCC for I/O pads (3.3 V). GND_core: ground for core. VCC_core: VCC for core (1.8 V).
7. Interfaces
7.1 Host interface
Different types of host busses are supported:
* Separate address/data bus with 16-bit data bus (3 different modes) * Multiplexed address/data bus with 16-bit data bus (2 different modes) * Separate address/data bus with 8-bit data bus (1 mode).
The host interface type is set via the dedicated pins H_sel and sys_clk. The SAA7893HL has a dedicated interrupt output pin.
7.2 Front-end interface
7.2.1 Data input interface The SAA7893HL supports three different front-end interfaces which are selectable via the host interface:
* I2S-bus interface: the front-end interface is in essence an I2S-bus interface and
therefore, it has to conform to the I2S-bus specification.
* FEC interface
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Super audio media player
* Parallel interface (UDE data interface part): a parallel front-end interface with a
handshake protocol. 7.2.2 Analog HF input The analog HF input, coming from the optical pickup unit, is also fed to the SAA7893HL to extract the copy protection information PSP.
7.3 Audio interface
7.3.1 Audio input The audio input is a 6-channel PCM-I2S input. 7.3.2 DAC interface The audio output is a 6-channel output and a separate stereo output. Both outputs can be set in DSD and in PCM-I2S mode.
7.4 SDRAM interface
The SDRAM interface forms a glueless interface to one 64 Mbit SDRAM device. Supported devices are only PC100 compliant or faster SDRAM devices:
* * * * *
Organization: 64 Mbit (1M x 16 x 4 banks) Refresh period: 4096 cycles per 64 ms Clock frequency: fclk 100 MHz Refresh cycle: trcar 70 ns Command period: trc 70 ns.
7.5 Clock and reset input
Different processing clocks are needed in the SAA7893HL:
* sys_clk: system clock for data processing part; frequency can be between
27 and 35 MHz; see Figure 6 and Table 3
* aud_clk: audio clock reference; can be 256/384/512/768 x fs (fs = 44.1 to 48 kHz);
see Figure 7 and Table 4
* proc_clk: host processor clock (only used in SAD16_01/02 mode) * B_BCLK: front-end bit/byte clock.
It is not required that these clocks are locked. RESETn is an asynchronous reset and should be kept LOW for at least 10 periods of sys_clk.
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Super audio media player
7.5.1
System clock (sys_clk) definitions
Tclk tclk(l) tclk(h)
tf
tr
MDB146
Fig 6. Sys_clk characteristics Table 3: Symbol Tclk tclk(l) tclk(h) tf tr clk Definitions of sys_clk Parameter clock cycle time clock time low clock time high fall time rise time clock duty cycle Conditions clock frequency from 27 to 35 MHz Min 28.5 11.4 11.4 40 Max 37.4 22.4 22.4 4 4 60 Unit ns ns ns ns ns %
7.5.2
Audio clock (aud_clk) definitions
Tclk tclk(l) tclk(h)
tf
tr
MDB146
Fig 7. Aud_clk characteristics Table 4: Symbol Tclk tclk(l) tclk(h) tf tr clk Definitions of aud_clk Parameter clock cycle time clock time low clock time high fall time rise time clock duty cycle Conditions clock frequency from 256 x 44.1 kHz to 768 x 48 kHz Min 27 10.8 10.8 40 Max 88.6 53.1 53.1 4 4 60 Unit ns ns ns ns ns %
7.6 Test inputs
Standard BST functionality is provided. Device data: Version: B0010
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Manufacturer ID: B000 0001 0101 Part no: B0011 0101 0110 0100.
8. Host interface
8.1 General description
The SAA7893HL is capable to communicate with the hosts (families) via their own busses as given in Table 5.
Table 5: Name SAD16_01 SAD16_02 SAD16_03 MAD16_01 MAD16_02 SAD08 Host communications Description Separate Address/Data on 16-bit data bus with wait signal, based on proc_clk Separate Address/Data on 16-bit data bus with wait signal, based on sys_clk and proc_clk Separate Address/Data on 16-bit data bus without wait signal Multiplexed Address/Data on 16-bit data bus mode 01 Multiplexed Address/Data on 16-bit data bus mode 02 Separate Address/Data on 8-bit data bus
The type of host is selected via two input pins H_sel[1] and H_sel[0] and the proc_clk signal. In Table 6 the settings for the different host modes are given with the expected input clock(s).
Table 6: H_sel[1:0] 00 10 01 11 11 01 Clock selection Mode SAD16_01 SAD16_02 SAD16_03 MAD16_01 MAD16_02 SAD08 External provided clocks sys_clk no yes yes yes yes yes proc_clk yes yes logic 1 logic 0 logic 1 logic 0 Internal used system clock proc_clk/2 sys_clk sys_clk sys_clk sys_clk sys_clk
In all modes the range of the required internal system clock is between 27 and 35 MHz. The pin mapping in the different modes is shown in Table 7.
Table 7: Host communication data mapping Type IN IN IN IN I/O SAD16_01; SAD16_02 CPU_A(7) CPU_A(4:1) CPU_A(4:1) CPU_A(6:5) CPU_D(7:0) SAD08 A(11) A(3:1) A(4) A(6:5) D(7:0) MAD16_01 ALE LA(2:0) LA(3) AD(21:20) AD(11:4) MAD16_02 ALE addr[3:1] n.c. n.c. data(7:0) SAD16_03 LA(7) LA(3:1) LA(4) LA(6:5) LD(7:0)
SAA7893HL name H_A_sel H_A[3:1] H_A[4] H_A[6:5] H_DQ[7:0]
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Table 7:
Host communication data mapping...continued Type I/O I/O I/O I/O I/O O IN IN IN O IN IN IN SAD16_01; SAD16_02 CPU_D(11:8) CPU_D(12) CPU_D(13) CPU_D(14) CPU_D(15) IRQN CPU_procclk n.c.; sysclk CPU_RWn CPU_wait CPU_CSn 0 logic 0: mode 1; logic 1: mode 2 SAD08 A(10:7) n.c. ASn DSn A(0) IRQn logic 0 PCI-clk R/Wn DSACKn CS logic 1 logic 0 MAD16_01 AD(1512) AD(16) AD(17) AD(18) AD(19) IRQN logic 0 Sclk RD_ ACK XIO logic 1 logic 1 MAD16_02 data(11:8) data(12) data(13) data(14) data(15) IRQN logic 1 sys_clk RD_ HDTACKn CSn logic 1 logic 1 SAD16_03 LD(11:8) LD(12) LD(13) LD(14) LD(15) IRQN logic 1 sys_clk RD_ n.c. CSn logic 1 logic 0
SAA7893HL name H_DQ[11:8] H_DQ[12] H_DQ[13] H_DQ[14] H_DQ[15] H_IRQn H_procclock sys_clk H_RWn H_WAITn H_CSn H_sel[0] H_sel[1]
The internal SAA7893HL address is differently composed in the different modes.
8.2 SAD16_01/02 mode
Reading and writing is always done on 16 bits (Hword) base. To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter called `the base address' into the SAA7893HL. Therefore, to access an address inside the SAA7893HL first these 16 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host device.
indication of an access to the base address
H_CSn
H_A_sel
H_RWn
H_A[6:1]
A(6:1)
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
D(15:0)
MCE038
write base address Fur_base = A(22:7)
write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 8. Write to or read from the SAA7893HL.
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SAA7893HL
Super audio media player
In Figure 8 the principle of first writing the base address indicated by H_A_sel is here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is, of course, not to scale. When the base address is written, multiple accesses can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way a burst of 64 Hwords can be read or written to the same address. The 16 bits base address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a read operation. Remark: The H_waitn signal is synchronized to H_procclock (pin 18). So it depends on the host used which H_procclock is provided. When the host can accept an asynchronous H_waitn signal, the clock signal connected to the sys_clk input (pin 21) can also be used as the clock signal to the H_procclock input. 8.2.1 Write mode: minimum cycle
ttot H_CSn tsu H_RWn th
H_DQ[15:0] H_A[6:1] H_A_sel
H_WAITn
MBL622
Fig 9. Timing diagram of writing registers with no wait cycles. Table 8: Symbol ttot tsu th Timing numbers of writing registers with no wait cycles Parameter total CSn time set-up time from CS to host control/address lines hold time from CS to host control/address lines Min 14 0 Typ Max 30 Unit sys_clk ns ns
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Super audio media player
8.2.2
Read mode: minimum cycle
ttot H_CSn tsu H_RWn th
H_A[6:1] H_A_sel ttri H_DQ[15:0] Z undefined tset H_WAITn
MBL633
th(D) data Z
Fig 10. Timing diagram of reading registers with no wait cycles. Table 9: Symbol ttot tsu th ttri tset th(D) Timing numbers of reading registers with no wait cycles Parameter total CSn time set-up time from CS to host control/address lines hold time from CS to host control/address lines time that data bus is set from 3-state to output time that data is valid before CS is set to logic 1 hold time from CS to data bus maximum time is not needed; can be forever Conditions Min 14 0 0 1 60 0 Typ Max 30 3 Unit sys_clk ns ns sys_clk ns ns
8.2.3
Write mode: cycles extended using wait protocol
ttot H_CSn tsu H_RWn th
H_DQ[15:0] H_A[6:1] H_A_sel twt(st) H_WAITn
MBL635
twt
twt(en)
Fig 11. Timing diagram of writing registers with wait cycles.
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Table 10: Symbol ttot tsu th twt
Timing numbers of writing registers with wait cycles Parameter total CSn time set-up time from CS to host control/address lines hold time from CS to host control/address lines active time of H_WAIT when Pi registers are accessed speed is dependent on load on PI-bus Conditions Min 14 0 0 3 3 5[1] 10 Typ 8 11 Max 30 11 17 6[1] Unit sys_clk ns ns sys_clk sys_clk sys_clk ns
active time of H_WAIT when external SDRAM is speed is dependent on load accessed on PI-bus twt(st) twt(en)
[1]
time from CS until wait becomes active time H_WAIT inactive until CS becomes inactive
When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles.
8.2.4
Read mode: cycles extended using wait protocol
ttot H_CSn tsu H_RWn th
H_A[6:1] H_A_sel t tri H_DQ[15:0] t wt(st) H_WAITn
MBL636
t set Z undefined t wt data
t h(D) Z
t wt(en)
Fig 12. Timing diagram of reading registers via PI-bus. Table 11: Symbol ttot tsu th twt Timing numbers of reading registers via PI-bus Parameter total CSn time set-up time from CS to host control/address lines hold time from CS to host control/address lines active time of H_WAIT when Pi registers are accessed speed is dependent on load on PI-bus Conditions Min 14[1] 0 0 3 3 5[2] Typ 8 11 Max 30 11 17 6[2] Unit sys_clk ns ns sys_clk sys_clk sys_clk
active time of H_WAIT when external SDRAM is speed is dependent on load accessed on PI-bus twt(st)
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time from CS until wait becomes active
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Super audio media player
Table 11: Symbol twt(en) ttri tset th(D)
[1]
Timing numbers of reading registers via PI-bus...continued Parameter time from H_WAIT negative slope to data set-up time that data bus is set from 3-state to output time that data is valid before CS is set to logic 1 hold time from CS to H_data bus Conditions Min 1 30 0 Typ Max 0 3 Unit ns sys_clk ns ns
[2]
When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal of at least 7 sys_clk cycles, then it is no longer required that the minimum time of ttot is 14 sys_clk cycles. The data at the H_DQ output is always available at the negative edge of the H_WAIT signal. The host can deactivate the H_CS signal after the negative edge of the H_WAIT signal and when it has read the data at the H_DQ lines. When a H_WAIT signal is always generated then the timing diagrams in Figure 9 and Figure 10 are no longer applicable. When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles.
8.2.5
Host interface connection
SAD16_01 mode
CPU_RW CE2n CPU_WAIT 10 k CPU_ADDR(7)
SAA7893HL
26 24 27 H_RWn H_CSn H_WAIT
123 124, 125, 126, 127, 128, 1 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25
H_A_sel
CPU_ADDR(6:1)
H_A[6:1]
CPU_ADDR(15:0) CPU_PROCCLK IRQ_x 18 28
H_DQ[15:0] H_procclk H_IRQn
GND_IO GND_IO GND_IO
21 62 63
sys_clk H_sel[0] H_sel[1]
MCE039
Fig 13. Host interface connection.
8.3 SAD16_03 mode
To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter called `the base address', into the SAA7893HL. Therefore, to access an address inside the SAA7893HL first this 16 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host device.
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indication of an access to the base address
H_CSn
H_A_sel
H_RWn
H_A[6:1]
A(6:1)
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
D(15:0)
MCE038
write base address Fur_base = A(22:7)
write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 14. Write to or read from the SAA7893HL.
In Figure 14 the principle of first writing the base address indicated by H_A_sel is here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is of course not to scale. When the base address is written, multiple accesses can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way a burst of 64 Hwords can be read or written to the same address. The 16 bits base address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a read operation. In SAD16_03 mode there is in principle no handshake available. Therefore, to read data a double read must be done.
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8.3.1
Read mode
indication of an access to the base address
H_CSn twt H_A_sel
H_RWn
H_A[6:1]
A(6:1)
undefined
H_DQ[15:0]
A(22:7)
undefined
D(15:0)
MCE040
write base address Fur_base = A(22:7)
data is read indicated by H_A_sel read 'indication' on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1)
Fig 15. Read from the SAA7893HL.
First the 16 bits of the base address are set indicated by the H_A_sel line. Then a read access is started. In SAD16_03 mode there is no handshake line on which the SAA7893HL can indicate that internal read operation is ready. Therefore, to be sure that the requested data is read correctly, an extra read is needed indicated by the H_A_sel line. In this read the data is presented as read by the previous read access. The maximum time that the host must wait before this extra read is started is approximately 30 sys_clk cycles. If in this time a new access is activated this access can be lost.
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Super audio media player
8.3.2
Write mode
indication of an access to the base address
H_CSn twt H_A_sel
H_RWn
H_A[6:1]
undefined
A(6:1)
H_DQ[15:0]
A(22:7)
D(15:0)
write base address Fur_base = A(22:7)
write on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1)
MCE041
Fig 16. Write to the SAA7893HL.
When a write operation is issued the same wait time twt must be taken into account before a next access may start, but here no double write has to be done. 8.3.3 Writing of base address
ttot H_CSn tsu(rw) H_RWn th
twt
H_A_sel tsu(ad) H_A[6:1] undefined
H_DQ[15:0]
address[22:7]
MCE042
Fig 17. Timing diagram of writing the base address.
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Super audio media player
Table 12: Symbol ttot twt
Timing numbers of base address writing Parameter total LOW time of H_CSn wait time before next cycle may start Conditions Min 270 if in this time a new cycle is started, 100 the new access cycle could be neglected Max Unit ns ns
tsu(rw) tsu(ad)
set-up time of H_RWn set-up time for address
0 10
ns ns
8.3.4
Writing data to the SAA7893HL
ttot H_CSn tsu(rw) H_RWn th
twt
H_A_sel tsu(ad) H_A[6:1] address[6:1]
H_DQ[15:0]
data[15:0]
MCE043
Fig 18. Writing data to the SAA7893HL. Table 13: Symbol ttot twt Timing numbers of writing data Parameter total LOW time of H_CSn wait time before next cycle may start Conditions Min 270 if in this time a new cycle is started, 700 the new access cycle could be neglected 0 Max Unit ns ns
tsu(rw) tsu(ad) th
set-up time of H_RWn set-up time for address hold time of H_RWn/address/data with respect to H_CSn
0 10 -
ns ns ns
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Super audio media player
8.3.5
Reading data from the SAA7893HL
ttot H_CSn tsu(rw) H_RWn
twt
ttot
th
H_A_sel tsu(ad) H_address(6:1) td(tri) H_data Z undefined Z H_a(6:1) don't care th(D) data
MCE044
Fig 19. Reading data from the SAA7893HL. Table 14: Symbol ttot twt Timing numbers of reading data Parameter total LOW time of H_CSn wait time before next cycle may start Conditions Min 270 if in this time a new cycle is started, 700 the new access cycle could be neglected time dependent on system clock 1 Max Unit ns ns
tsu(rw) tsu(ad) ttri
set-up time of H_RWn set-up time for address time that data bus is enabled
0 10 3
ns ns sys_clk
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Super audio media player
8.3.6
Host interface connection
SAD16_03 mode
RD_ CSn n.c.
SAA7893HL
26 24 27 H_RWn H_CSn H_WAIT
LA(7)
123 124, 125, 126, 127, 128, 1 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25
H_A_sel
LA(6:1)
H_A[6:1]
LD(15:0) IRQ_x VCC_IO 28 18
H_DQ[15:0] H_IRQn H_procclk
21 sys_clk or video clock VCC_IO GND_IO 62 63
sys_clk H_sel[0] H_sel[1]
MCE045
Fig 20. Host interface connection.
8.4 MAD16_01 mode
Data communication is here always done on a 16-bit data bus. The address is mapped on 6 separate address pins and 16 address/data pins of the SAA7893HL. Therefore, in this mode the complete address is transferred directly in each access cycle. In Table 7 the internal SAA7893HL address is mapped as follows to the SAA7893HL pins: Fur_H_A[22:1] = H_A[6:5] & H_DQ[15:0] & H_A[4:1]. This address mapping is the default setting, the following address is also possible: Fur_H_A[22:1] = H_A[6:1] & H_DQ[15:0]. The system clock provided in the MAD16_01 mode must be synchronized to the host interface timing.
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Super audio media player
8.4.1
Write mode: minimum cycle
sys_clk ttot H_CSn trd H_A_sel
H_RWn
H_WAIT tsu addr th
H_A[6:1]
H_DQ[15:0]
addr tdw
data
MBL637
Fig 21. Timing diagram writing to the SAA7893HL. Table 15: Symbol ttot tsu th trd tsu(D) Timing numbers of writing registers Parameter total H_CSn time set-up time H_A_sel hold time of H_A_sel with respect to sys_clk time H_RWn can change from H_CSn signal data set-up time after H_CSn Min 8 5 5 0 Max 1 1 Unit sys_clk ns ns sys_clk sys_clk
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Super audio media player
8.4.2
Read mode: minimum cycle
sys_clk
H_CSn trd H_A_sel
H_RWn
H_WAIT tsu addr th
H_A[6:1]
H_DQ[15:0]
addr tdr
data
MBL638
Fig 22. Timing diagram reading from the SAA7893HL. Table 16: Symbol tsu th trd tdr tdc Timing numbers of reading registers Parameter set-up time H_A_sel hold time of H_A_sel with respect to sys_clk time H_RWn can change from H_CSn signal data set-up time after CSn data hold time before CSn time dependent on system clock used not important data is sample after detecting H_CSn = logic 0 Conditions Min 5 5 6 Max 1 8 Unit ns ns sys_clk sys_clk ns
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Super audio media player
8.4.3
Write mode: cycles extended using wait protocol
sys_clk ttot H_CSn trd H_A_sel
H_RWn
H_WAIT tsu H_A[6:1] addr
th
H_DQ[15:0]
addr tdw1 tdw2 twt
data
MBL639
Fig 23. Timing diagram writing to the SAA7893HL (with wait cycles). Table 17: Symbol ttot tsu th trd tdw1 tdw2 twt Timing numbers of writing registers (with wait cycles) Parameter total H_CSn time set-up time H_A_sel hold time of H_A_sel with respect to sys_clk time H_RWn can change from H_CSn signal data set-up time after H_CSn time H_WAIT is activated after H_CSn is activated total time wait can be active dependent on SAA7893HL settings Conditions Min 8 5 5 time dependent on system clock used 1 2 2 Max 1 3 6 24 Unit sys_clk ns ns sys_clk sys_clk sys_clk sys_clk
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Super audio media player
8.4.4
Read mode: cycles extended using wait protocol
sys_clk
H_CSn trd H_A_sel
H_RWn
H_WAIT tsu addr
th
H_A[6:1]
H_DQ[15:0]
addr tdw twt tac
data
MBL640
Fig 24. Timing diagram reading from the SAA7893HL (with wait cycles). Table 18: Symbol ttot tsu th trd tdw twt tac Timing numbers of reading registers (with wait cycles) Parameter total H_CSn time set-up time H_A_sel hold time of H_A_sel with respect to sys_clk time H_RWn can change from H_CSn signal time H_WAIT is activated after H_CSn is activated total time wait can be active data active until H_CSn is deactivated Min 8 5 5 dependent on SAA7893HL settings 2 2 1 Max 1 5 24 Unit sys_clk ns ns sys_clk sys_clk sys_clk sys_clk
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Super audio media player
8.4.5
Host interface connection
MAD16_01 mode
XIO_x XIO_x VCC_IO 10 k X_ACK ALE
SAA7893HL
26 24 H_RWn H_CSn
27 123 124, 125, 126, 127, 128, 1
H_WAIT H_A_sel
AD(21:16) 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 AD(15:0) SCLK IRQ_x GND_IO VCC_IO VCC_IO 21 28 18 62 63
H_A[6:1]
H_DQ[15:0] sys_clk H_IRQn H_procclk H_sel[0] H_sel[1]
MCE046
Fig 25. Host interface connection.
8.5 MAD16_02 mode
In the MAD16_02 mode there is a 16-bit combined address/data bus and a dedicated 3-bit address bus.
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H_CSn
H_A_sel
H_RWn
H_A[3:1]
ha[22:20]
ha[3:1]
H_WAITn
H_DQ[15:0]
ha[19:4]
Z
undefined
data[15:0]
Z
MCE047
Fig 26. Principle read.
The multiplexing of the address/data pins is done as a regular host communication, meaning that during a read or write the host must automatically generate the timing according to Figure 26. It is not needed that the provided system clock is a synchronous clock with respect to the H_A_sel line. 8.5.1 Write mode
ttot H_CSn tsu H_A_sel th(ad) H_RWn th(cs)
H_A[3:1]
ha[22:20]
ha[3:1]
H_DQ[15:0]
ha[19:4] tdw1
data[15:0] twt
H_WAITn
MCE048
Fig 27. Timing diagram writing to the SAA7893HL.
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Timing numbers of MAD16_02 write Parameter total LOW time of H_CSn hold time of address/data with respect to H_A_sel wait time until H_WAIT is activated time of H_WAIT signal set-up time of H_RWn/address with respect to H_CSn Min 300 + twt 10 2 2 Max 5 24 10 Unit ns ns sys_clk sys_clk ns
Table 19: Symbol ttot th tdw1 twt tsu
8.5.2
Read mode
ttot H_CSn
H_A_sel th H_RWn
H_A[3:1]
ha[22:20] tsu
ha[3:1] twt
H_WAITn ttri H_DQ[15:0] ha[19:4] Z tdw1 tset(D) undefined data[15:0]
MCE049
Fig 28. Timing diagram reading from the SAA7893HL. Table 20: Symbol ttot tsu th tdw1 Timing numbers of MAD16_02 read Parameter total H_CSn time Min 8 + twt Typ Max 0 4 Unit ns ns ns sys_clk
set-up time of address/data/H_RWn with respect to H_CSn hold time of address with respect to H_A_sel falling edge 10
time H_WAIT is activated after H_CSn is activated
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Timing numbers of MAD16_02 read...continued Parameter time data bus becomes active after H_CSn time data available with respect to H_WAIT signal time H_WAIT can be active Min 15 2 Typ 2 Max 24 Unit sys_clk ns sys_clk
Table 20: Symbol ttri tset(D) twt
8.5.3
Host interface connection
MAD16_02 mode
RD_ CSn HDTACKn
SAA7893HL
26 24 27 H_RWn H_CSn H_WAIT
ALE n.c.
123 124, 125, 126
H_A_sel H_A[6:4]
127, 128, 1 ADDR(3:1) 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 DATA(15:0) IRQ_x VCC_IO 28 18 H_DQ[15:0] H_IRQn H_procclk H_A[3:1]
21 sys_clk or video clock VCC_IO VCC_IO 62 63
sys_clk H_sel[0] H_sel[1]
MCE050
Fig 29. Host interface connection.
8.6 SAD08 mode
Here the reading and writing is always done on 8-bit. From pin mapping it can be seen that the byte indication is done via bit A(0) which is mapped on H_DQ(15) of the SAA7893HL. The internal SAA7893HL communication stays on 16-bit. Therefore, the host interface block `translates' the 8 bits external communication to the 16 bits internal. To save physical pins on the SAA7893HL device, the data bus and 4 address bits are used to write the 12 MSB address bits, hereafter called `the base address', into the SAA7893HL device. Therefore, to access an address inside the SAA7893HL first this 12 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host.
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8.6.1
Writing base address
indication of an access to the base address
H_CSn
H_RWn
H_A_sel
H_A[6:1]
A(6:1)
A(6:1)
H_DQ[15]
LSB write/read
MSB write/read
H_DQ[7:0]
A(22:15)
D(7:0)
D(15:8)
H_DQ[11:8]
A(14:11)
A(10:7)
A(10:7)
MCE051
write base address Fur_base = A(22:11)
write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(10:1)
Fig 30. Base address writing.
In Figure 30 the writing of the base address and a Hword to the host is given in SAD08 mode. First, the 12 bits base address is written indicated by H_A_sel line. The SAA7893HL samples the base address on H_DQ(7:0) and H_DQ(11:8). After that the normal write operation is performed as explained in Section 8.6.2. 8.6.2 Writing to the SAA7893HL A write to address N of 16 bits to the SAA7893HL will be translated to two byte accesses. First the LSB byte is written to address N [so A(0) = logic 0] and stored in cache. Then the MSB byte is written to address N+1 [so A(0) = logic 1]. When the SAA7893HL receives a write command at an odd address [A(0) = logic 1] always 16 bits are internally written whereby the Hword is composed of LSB byte in cache and the MSB byte received at present write command. The SAA7893HL can be set to big and little endian, whereby the described situation is the power-on state. Byte read or write operations are not supported in SAD08 mode.
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sys_clk th H_CSn
tsu
H_DQ[11:8] H_A[7:0] th H_RWn td(as) H_DQ[13]
address
H_DQ[7:0] td(ds) H_DQ[14]
data
td H_WAIT M clock cycles
MBL641
Fig 31. Timing diagram SAD08 write to SAA7893HL. Table 21: Symbol tsu th td(as) td(ds) M td Timing numbers of SAD08 write Parameter set-up time from H_CSn, H_RWn and H_DQ(13) to sys_clk hold time from clk to H_CSn, H_RWn and H_DQ(13) delay from H_CSn to negative slope of H_DQ(13) delay from H_CSn to negative slope of H_DQ(14) and data number of clock cycles delay from clk to DSACKn dependent on access type and traffic on PI-bus Conditions Min 5 5 4 2 Max 1 2 15 12 Unit ns ns sys_clk sys_clk sys_clk ns
8.6.3
Reading from the SAA7893HL When the LSB is read [A(0) = logic 0], the host interface will read an Hword on the address location A(22:1). The LSB byte is set on the output bus and the read MSB byte is stored internally. When a read action is now started whereby the MSB byte is selected to read [A(0) = logic 1] the stored byte is available on the output independent on the other address bits A(22:1).
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sys_clk th tsu H_CSn
H_DQ[11:8] H_A[7:0] th H_RWn
address
H_DQ[13]
H_DQ[7:0] tdat H_DQ[14] td H_WAIT N clock cycles
data
MBL623
Fig 32. Timing diagram SAD08 read from the SAA7893HL. Table 22: Symbol tsu th N td tdat Timing numbers of SAD08 read Parameter set-up time from H_CSn, H_RWn and H_DQ[13] to sys_clk hold time from clk to H_CSn, H_RWn and H_DQ[13] number of clock cycles delay from clk to H_WAIT data available before H_WAIT is asserted dependent on access type and traffic on PI-bus. Conditions Min 5 5 5 2 20 12 0 Max Unit ns ns sys_clk ns ns
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Super audio media player
8.6.4
Host interface connection
SAD08 mode
CPU_RW CE2n VCC_IO 10 k CPU_WAIT XIO_ADDR(11) XIO_ADDR(10:7)
SAA7893HL
26 24 H_RWn H_CSn
27 123 7, 8, 9, 11 124, 125, 126, 127, 128, 1
H_WAIT H_A_sel H_DQ[11:8]
XIO_ADDR(6:1) XIO_ADDR(0) DS AS 2 3 5 12, 13, 14, 15, 16, 22, 23, 25 XIO_DATA(7:0) PCI_CLK IRQ_x GND_IO VCC_IO GND_IO 21 28 18 62 63
H_A[6:1] H_DQ[15] H_DQ[14] H_DQ[13]
H_DQ[7:0] sys_clk H_IRQn H_procclk H_sel[0] H_sel[1]
MCE052
Fig 33. Host interface connection.
8.7 Interrupt
The interrupt output is a LOW level interrupt which must be connected to the interrupt input of the DVD host.
9. Front-end interface
First the SACD sector structure is explained and how to connect the SAA7893HL in the different modes. For these different modes the interface timing figures will be given. The supported sector format interface is sketched in Figure 34.
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Byte 0 to 11 HEADER 12
Byte 12 to 2059 MAIN DATA 2048 stored in VBR sector format
Byte 2060 to 2063 EDC 4
Byte 0 INFORMATION ID[31...24]
Byte 1 to 3 NUMBER ID[23...0]
Byte 4 to 5 IED
Byte 6 to 11 CPSI
MBL616
Fig 34. SACD sector format.
The SAA7893HL supports a data input bit rate of maximal 40 Mbits/s. The connections to the SAA7893HL in the different front-end modes are given in Table 23.
Table 23: Connection of different front-end interfaces Type IN IN IN IN IN IN IN O I2S_mode I2S_err I2S_sync I2S_wclk I2S_bclk I2S_data n.c.[1] n.c.[1] n.c. FEC n.c.[1] OUT_SYNC OUT_DVALID OUT_CLK OUT_DATA0 n.c.[1] n.c.[1] n.c. Parallel mode SERR SYNC SENB SDCLK MPEG(0) MPEG(7:1) UDE_req REQ
SAA7893HL name B_FLAG B_SYNC B_WCLK B_BCLK B_DATA Be_dat(7:1) UDE_req Data_req
[1]
The n.c. input pins must be connected to VCC or GND.
9.1 I2S-bus interface
9.1.1 Input timing In Figure 35 the functional input timing is given. Note that B_SYNC, B_FLAG are sampled simultaneously with D11. Since B_FLAG indicates the error in a byte, it is also sampled simultaneously with D3. The sampling moment during D11 for the high byte (D15 to D8), sampling moment D3 for the low byte (D7 to D0).
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I2S-bus half word B_DATA D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
B_BCLK
B_WCLK
B_SYNC
B_FLAG
MBL617
Fig 35. Front-end input timing.
When the B_SYNC signal is set to logic 1 between bit position D15 and D11 the SAA7893HL accepts this word as the start of a sector. The SAA7893HL does not perform EDC checking on the main data, but is dependent on the B_FLAG. A sector is set to erroneous if B_FLAG is set to logic 1. 9.1.2 Interface timing
B_BCLK
B_SYNC B_FLAG B_WCLK B_DATA
MBL624
tsu
th
Fig 36. Timing in I2S-bus interface. Table 24: Symbol tsu th Timing in I2S-bus interface Parameter set-up time to rising edge of the clock hold time after rising edge of the clock Min 5 5 Unit ns ns
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9.1.3
Interface connection
I2S-BUS front-end IC I2S_clk I2S_wclk I2S_sync I2S_err I2S_dat 46 44 43 42 45 49-55 open 47 48
SAA7893HL
B_BCLK B_WCLK B_SYNC B_FLAG B_DATA
Be_dat(7:1) UDE_req Data_req
MCE053
Not used input pins must be connected to VCC or GND.
Fig 37. Front-end interface connection.
9.2 UDE data interface
In the SA-MP the synchronous parallel mode is supported. There are three types of parallel data transfer modes supported:
* Synchronous mode (see Section 9.2.1) * Asynchronous mode:
- Handshake to enable data transfer - Handshake for every byte transfer.
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9.2.1
Parallel mode
tclk(h)
tclk(l)
B_BCLK th Data_req tsu B_WCLK
th
B_FLAG tsu B_SYNC
Sa_2059
Sa_2060
Sa_2061
Sa_2062
Sa_2063
Empty
Empty
Empty
Empty
Sb_0
Sb_1
Sb_2
Sb_3
Sb_4
Sb_5
Be_dat(7:0)
MCE054
Fig 38. Timing diagram for UDE interface with level sync mode.
Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable. The UDE transmitter must react on the Data_req signal within 5 B_BCLK cycles. The SAA7893HL samples the data on the positive slope of B_BCLK when the B_WCLK signal is active. When B_FLAG signal is active for one byte of the sector, the total sector will be treated as erroneous. The maximum clock frequency of B_BCLK is 20 MHz. The Data_req line generated by the SAA7893HL is synchronized to the internal sys_clk signal. Therefore, the Data_req line is asynchronous with respect to BCLK line.
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B_BCLK th Data_req tsu B_WCLK
th
B_FLAG tsu
B_SYNC
Sa_2059
Sa_2060
Sa_2061
Sa_2062
Sa_2063
Empty
Empty
Empty
Empty
Sb_0
Sb_1
Sb_2
Sb_3
Sb_4
Sb_5
Be_dat(7:0)
MCE055
Fig 39. Timing diagram for UDE interface with sync edged triggered mode.
Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable.
Table 25: Symbol tclk(h)(l) tsu th to Timing in synchronous parallel mode Parameter HIGH/LOW time of the B_BCLK signal set-up time to rising edge of the clock hold time after rising edge of the clock output delay from the clock Conditions maximum clock frequency of B_BCLK is 20 MHz data/control must be stable during tsu before positive slope of B_BCLK Min 20 10 Max 15 Unit ns ns ns ns
5 data/control must be kept at least during th after positive slope of B_BCLK 2
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9.2.2
Interface connection
UDE front-end IC sdclk senb sync serr 46 44 43 42 45 data 49-55 48 47
SAA7893HL
B_BCLK B_WCLK B_SYNC B_FLAG B_DATA Be_dat(7:1) Data_req UDE_req
req
DVD back-end IC sdclk with UDE
req senb sync serr data
MCE056
Fig 40. Front-end interface connection.
9.3 FEC interface
This is a serial interface for communication to a special front-end IC.
bclk/ ser_bclk
be_dat(0)/ ser_data
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
bit 10
bit 11
bit 12
bit 13
bit 14
bit 15
bit 16
wclk/ ser_valid
sync/ ser_sync
MBL619
Fig 41. FEC interface.
The timing diagram of the FEC interface is given in Figure 41. The first bit of a sector is indicated by the sync signal; this is the MSB bit of the first byte of the header. The sector error indication is in FEC mode indicated by two extra bytes at the end of the sector. This means that the sector length is increased to 2066 bytes. The indication of errors is as follows: FF = error; 00 = no error.
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9.3.1
Timing
B_BCLK
B_SYNC B_FLAG B_WCLK B_DATA
MBL624
tsu
th
Fig 42. Timing in FEC interface. Table 26: Symbol tsu th Timing in FEC interface Parameter set-up time to rising edge of the clock hold time after rising edge of the clock Min 10 5 Unit ns ns
9.3.2
Interface connection
FEC front-end IC ser_clk ser_valid ser_sync GND_IO ser_dat 46 44 43 42 45 49-55 open 47 48
SAA7893HL
B_BCLK B_WCLK B_SYNC B_FLAG B_DATA
Be_dat(7:1) UDE_req Data_req
MCE057
Fig 43. Front-end interface connection.
10. HF input
10.1 General
On every SACD disc a PSP signal must be recorded. The player is only allowed to play a disc if a valid PSP signal is detected. This PSP key is recorded via a special mechanism in the EFM signal on disc. The EFM+ signal must be fed to the SAA7893HL as shown in Figure 44.
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+1.8 V VDDA Agcinp 100 nF Adcrefl 12 k biasin VSSA
MBL620
10 nF EFM+
Fig 44. Connection of EFM+ input.
The detection of the PSP key is dependent of the polarity of the EFM+ signal. The SA-MP settings are that a pit on the disc must have a higher output voltage than the land. The EFM+ input signal has no timing requirements with respect to the digital input of the front-end interface of the SAA7893HL. The SAA7893HL supports also an inversion of the EFM+ signal.
10.2 HF input specification
The AGC circuit must be able to handle the following signal characteristics of the HF input signal.
Table 27: HF Input range Bandwidth HF signal characteristics Value 0.2 to 0.8 V (p-p) 9 MHz Remark HF input voltage front-end running on maximum speed needed for SACD
The HF is AC-coupled via a capacitor of 10 nF to pin Agcinp. The internal resistance of pin Agcinp is 1 M.
Table 28: Pin name Agcinp biasin Adcrefl VSSA VDDA Signal connections Description HF output from pickup unit connected via a 10 nF couple capacitor bias current; connect a 12 k resistor to VSS (ground) reference voltage for internal resistor trap; decouple with 100 nF to VSS (ground) analog ground 1.8 V analog power supply
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10.3 HF-input application diagram
+1.8 V 100 nF
4.7 F 32
EFM+ (0.2-0.8 V)
10 nF
35
VDDA Agcinp
100 nF
SAA7893HL
36 Adcrefl
12 k
34
biasin VSSA 33
MCE058
Fig 45. EFM input interface connection.
11. Audio interfaces
11.1 Audio input interface
The PCM-I2S audio input signals can be either directly couple, without any processing to the DSD_PCM output lines, or further processed inside the SAA7893HL. When directly coupled, only a combinatorial delay must be taken into account; no dependency on any clock signal (see Section 11.1.1). The input signal characteristics, when audio processing must be performed, are given in Section 11.1.2. 11.1.1 Audio input directly coupled When no processing is done inside the SAA7893HL with respect to the I2S-PCM input stream, this input stream is sent via a multiplexer to the I2S-bus output paths. So no clocking is done on this signal, meaning that also no locked audio clock needs to be present.
input pin
td(as)
output pin
MBL627
Fig 46. Delay from input to output pin. Table 29: Symbol td(as) Timing numbers in PCM audio Parameter asynchronous delay Min 8 Typ 13 Max 18 Unit ns
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11.1.2
Audio input `with processing'
right channel right surround LFE PCM_wclk_in 16/24/32/48 clock cycles tsu th PCM_dclk_in th tsu PCM_LeRi_in PCM_LsRs_in PCM_CeLf_in MSB 1 2 3 22 LSB MSB
left channel left surround center
1
2
3
MBL628
24 data bits
Fig 47. Audio I2S-bus input timing. Table 30: Symbol tsu Timing numbers in PCM audio Parameter set-up time to rising edge to the pcm_dclk_in signal hold time after rising edge of the pcm_dclk_in signal Conditions PCM-I2S Min Unit ns in mode, the data is always outputted on 8 the negative edge of the bit clock; so here data is sampled on positive edge of the clock in PCM-I2S mode, the data is always outputted on 5 the negative edge of the bit clock; so here data is sampled on positive edge of the clock
th
ns
11.1.3
Interface connection
audio clock 256/384/512/768 x fs DVD back-end IC aud_clk_in I2S_clk I2S_wclk I2S_leri I2S_Celfe I2S_Isrs 29 30 31 40 39 41
SAA7893HL
aud_clk PCM_dclk_in PCM_wclk_in PCM_LeRi_in PCM_CeLf_in PCM_LsRs_in
MCE059
Fig 48. Audio I2S-PCM input interface connection.
11.2 Audio output interface
The 6-channel outputs can be either DSD format or PCM-I2S format. The connections are given in Table 31.
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The SAA7893HL has 12 output lines: 8 lines are allocated for connection to a 6-channel DAC and 4 are for connection to a 2-channel DAC or a 75 Hz reference signal. The DSD data on the MCH output lines are outputted 6412 clocks after the positive edge of the 75 Hz signal, if no additional post-processing is done.
SA-MP
DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11
MBL621
to 6-channel DAC
to 2-channel DAC
Fig 49. SA-MP output line allocation.
The SA-MP delivers extra flexibility when connecting to different DAC types, which can be: DSD only, PCM only or multi standard (DSD + PCM)]. In Table 31 the signal allocation is given for the 6-channel output in DSD and in PCM-I2S mode.
Table 31: Connection to a 6-channel DAC Pin Mode = DSD number 108 109 110 111 113 114 115 116 left channel right channel center channel LFE channel left surround right surround DSD clock or 0 or 1 DSD clock or 0 or 1 Mode = PCM Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock PCM data/word clock PCM data/word clock
Output line DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7
In Table 32 the signal allocation is given for the DSD/PCM signals to be connected to the stereo DAC.
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Connection to a 4-channel DAC Pin Mode = DSD number 117 120 119 121 DSD clock 0 or 1 left channel right channel Mode = PCM PCM data/word clock PCM data/word clock Lf + Rf; 0 or 1 Lf + Rf; 0 or 1 Mode = 75 Hz 0 or 1 0 or 1 75 Hz 0 or 1
Table 32:
Output line DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11
Both tables show that DSD has a fixed allocation while PCM outputs are selectable. The I2S-bus bit stream, generated by the SAA7893HL decimation filter, is in the Philips format as can be seen in the timing diagrams. The number of data bits is always 24.
Table 33: Serial bit clock frequency I2S output `wclk' frequency 2fs 4fs 384fs 2fs 4fs 512fs 768fs 2fs 4fs 2fs 4fs DCLK (data bit) frequency 128fs 256fs 128fs 384fs 128fs 256fs 128fs 256fs no symmetrical bit clock 48 clocks for a word identification Remark
Audio input clock 256fs
The wclk identification is always active for 32 clocks for each left and right sample, except when the input clock is 384fs and the output sample frequency is 4fs; then the wclk is 48 samples active. 11.2.1 DSD output
aud_clk
td(o) dsd_clk (= 64fs)
dsd_pcm-data
SAMPLE N
SAMPLE N + 1
MBL629
Fig 50. Audio I2S-bus output timing.
Remark: in this example timing of the aud_clk is 256 x fs and DSD clock phase is set to logic 0. If phase is set to logic 1, the dsd_clk signal will be inverted.
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Timing numbers in DSD audio Parameter output delay time with respect to the audio clock Min 4 Max 20 Unit ns
Table 34: Symbol td(o)
11.2.2
I2S-PCM generated by the SAA7893HL In Figure 51 and Figure 52 the timing diagrams are given when the internal PCM generator of the SAA7893HL generates the I2S-PCM output signals.
right channel right surround LFE pcm_wclk_out twclk 32 pcm_dclk_out clock cycles
left channel left surround center
pcm_dclk_out
tdata pcm_LeRi_out pcm_LsRs_out pcm_CeLf_out MSB 1 2 3 22 LSB MSB 1 2 3
MBL630
24 data bits
Fig 51. Audio I2S-bus output timing in Philips format.
left channel left surround center
right channel right surround LFE
twclk 32 clock cycles
tdata MSB 1 2 3 22 LSB MSB 1 2 3
MBL631
24 data bits
Fig 52. Audio I2S-bus output timing in left justified format. Table 35: Symbol twclk tdata Timing numbers for PCM-I2S output Parameter pcm_wclk_out timing with respect to negative edge of pcm_dclk_out pcm_data_out timing with respect to negative edge of pcm_dclk_out Min -10 -10 Max +10 +10 Unit ns ns
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11.3 Audio output application diagrams
11.3.1 Hybrid DAC connection
SAA7893HL
DSD_PCM_0 all slew rate controlled 109 DSD_PCM_1 output pins (no serial 110 resistors needed) DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 111 113 114 115 116 108
dsd_left/ i2s_lfrf sdata_ifrf dsd_right/ '0' dsd_centre/ i2s_celfe dsd_lfe/ '0' dsd_left_sur/ i2s_lsrs dsd_right_sur/ '0' dsd_clk/ i2s_dclk '0'/ i2s_wclk dsd_clk/ i2s_dclk '0'/ i2s_wclk dsd_left_mix/ i2s_lmrm dsd_right_mix/ '0' M_x sdata_celfe M_x sdata_Isrs M_x sclk wclk
hybrid MCA DAC
mclk
DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11 29
117 120 119 121
sclk wclk sdata_Ifrf M_x
hybrid stereo DAC
aud_clk
mclk
MCE060
audio clock
Fig 53. Hybrid DAC interface connection.
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11.3.2
DSD DAC connection
SAA7893HL
DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 108 109 110 111 113 114 115 116
dsd_left dsd_right dsd_centre dsd_lfe dsd_left_sur dsd_right_sur
DSD MCA DAC dsd_left dsd_right dsd_centre dsd_lfe dsd_ls dsd_rs
dsd_clk sclk n.c. dsd_clk mclk
DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11 29
117 120 119 121
dsd_clk
DSD stereo DAC
n.c. dsd_left_mix dsd_right_mix dsd_right audio clock mclk
MCE061
dsd_left
aud_clk
Fig 54. DSD DAC interface connection.
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11.3.3
PCM DAC connection
SAA7893HL
DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 108 109 110 111 113 114 115 116
i2s_lfrf
PCM MCA DAC sdata_lfrf
n.c. i2s_celfe sdata_celfe
n.c. i2s_lsrs sdata_lsrs
n.c. i2s_dclk sclk i2s_wclk wclk mclk
DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11 29
117 120 119 121
i2s_dclk i2s_wclk i2s_lmrm
sclk wclk sdata_lfrf
PCM stereo DAC
aud_clk
n.c. audio clock
mclk
MCE062
Fig 55. PCM DAC interface connection.
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12. SDRAM interface
12.1 Writing
clk td D_clk tcmd D_RASn D_CASn D_Wen nop active write taddr D_ADDR[13:0] XX address address tdqm D_UDQM D_LDQM upper/lower byte tdata D_DQ[15:0] ZZZZ data ZZZZ
MBL632
precharge
XX
Fig 56. SDRAM interface writing. Table 36: Symbol td tcmd taddr tdqm tdata Timing numbers of SDRAM interface writing Parameter delay from clk to control signals delay from clk to address lines delay from clk to D_UDQM and D_LDQM signals delay from clk to data output signals Conditions Min 3 1 1 1 1 Max 9 15 15 12 12 Unit ns ns ns ns ns delay from clk to D_clk of SDRAM interface D_clk is clock of SDRAM
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12.2 Reading
clk td D_clk tcmd D_RASn D_CASn D_Wen nop active read taddr D_ADDR[13:0] address address tdqm D_UDQM D_LDQM upper/lower byte tsu D_DQ[15:0] th nop nop nop precharge
data to SAA7893HL
MBL634
Fig 57. SDRAM interface reading. Table 37: Symbol td tcmd taddr tdqm tsu th Timing numbers of SDRAM interface reading Parameter delay from clk to D_clk of SDRAM interface delay from clk to control signals delay from clk to address lines delay from clk to D_UDQM and D_LDQM signals set-up time of data to clk hold time of data from clk Conditions D_clk is clock of SDRAM Min 3 1 1 1 3 3 Max 9 15 15 12 Unit ns ns ns ns ns ns
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12.3 Interface connection
+3.3 V
SAA7893HL
D_DQ[15:0] D_ADDR[11:0] D_ADDR[12] D_ADDR[13] D_RASn D_CASn D_Wen D_clk D_UDQM D_LDQM 78 75 81 82 80 86 88 89
64 Mbit SDRAM CKE DQ(15:0) A(11:0) BA0 BA1 RAS_ CAS_ WE_ CLK DQMH DQML CS_
MCE063
Fig 58. SDRAM interface connection.
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13. Power supply connections
SAA7893HL
10 4.7 F 100 nF 100 nF 4 37 100 nF 38 58 100 nF 17 76 100 nF 69 92 100 nF 83 106 100 nF 99 118 100 nF 100 MHz coil 4.7 F 3.3 to 1.8 V CONVERTOR (LF18CD) 112 VCC_IO1 GND_IO1 VCC_IO7 GND_IO7 VCC_IO2 GND_IO2 VCC_IO3 GND_IO3 VCC_IO4 GND_IO4 VCC_IO5 GND_IO5 VCC_IO6 GND_IO6
3.3 V
19 4.7 F 100 nF 100 nF 20 85 100 nF 84 32 4.7 F 100 nF 100 nF 33
VCC_Core1 GND_Core1 VCC_Core2 GND_Core2 VDDA VSSA
MCE064
100 MHz coil 4.7 F
3.3 to 1.8 V CONVERTOR (LF18CD)
Fig 59. Power supply connections.
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Product data
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Super audio media player
14. Software API
14.1 API provided by SA-MP
Table 38: Name Playback API NAV_AreaSwitch NAV_PlayTrack NAV_PlayAtTimecode NAV_Stop NAV_Pause NAV_ResumePlay NAV_NextTrack NAV_PreviousTrack NAV_Repeat NAV_RepeatAB NAV_Shuffle NAV_IntroScan NAV_ForwardScan NAV_BackwardScan NAV_SetPlaySequence NAV_SetProgramList NAV_GetState NAV_GetPlayList Post-processing API APM_SetSpeakers APM_SetInputMode APM_SetOutputMode APM_Set6chDownMix APM_Set2chDownMix APM_SetBassFilters APM_SetAttenuation APM_SetDelay APM_SetFilterMode APM_SetPcmUpsampling APM_SetPIO Text and Data API SDI_SetAvailableCharSets SDI_SetLanguagePreference SDI_GetAlbumInfo SDI_GetAlbumText
9397 750 10925
API provided by SA-MP Description Switch SACD Area Start playing at the index of the track Start playing at the given time Stop playback Pause playback Resume playback at normal speed Continue with next track Continue with previous track Set the repeat mode for playback Set the repeat AB mode Play tracks in random order Play only intro part of each track Start scanning forward - fast playback with burst sound Start scanning backward - fast playback with burst sound Set play sequence mode Set program list Returns navigator states Returns navigator play list Select speaker configuration Select between DSD or PCM as APM input Select APM output mode (DSD or PCM) Set the downmix of six-channel output stream Set the downmix of two-channel output stream Select the bass management frequency and slope Set attenuation of an output channel Set delay of a channel of output stream Set Sigma Delta modulator filter mode Set the PCM upsampling mode Set the DAC PIO pins Set a list of character sets, application can handle Set a list of preferred languages Retrieve information about the album of active disc Retrieve album text items
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API provided by SA-MP...continued Description Retrieve number of indices for specified track Retrieve information about the active disc Retrieve disc text items Retrieve area text items Retrieve information about the specified track Retrieve track text items Select the front-end interface attached to SA-MP Configure the DAC pins Configure the audio clock for different input stream modes Configure the SDRAM attached to the SAA7893HL Return the pointer to SA-MP interrupt handler Configure the DSD clock polarity Inform SA-MP about the system clock Configure the burst length for fast play Initialize SA-MP Terminate SA-MP Activate SA-MP Reactivate SA-MP Deactivate SA-MP SACD disc recognition
Table 38: Name
SDI_GetNumberOfIndices SDI_GetDiscInfo SDI_GetDiscText SDI_GetAreaText SDI_GetTrackInfo SDI_GetTrackText System configuration API SDM_SetBeType SDM_SetDacPinnning SDM_SetAudioClock SDM_SetMemoryConfig SDM_GetHandler SDM_SetDsdClockPolarity SDM_SetSystemClock SDM_SetBurstLength General API SAMP_Init SAMP_Term SAMP_Activate SAMP_Reactivate SAMP_Deactivate SAMP_SACDDiscReq
14.2 API required by SA-MP
Software to be provided by the DVD host:
* For the front-end: Seek, GetDataArea, TransferRate (optional) * For the operating system: Tasks, Interrupts, Semaphores, Mailboxes, Timers.
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15. Limiting values
Table 39: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. Symbol VCC_Core VCC_IO VDDA VI Tamb Tstg Tj
[1]
Parameter digital core supply voltage IO pins supply voltage analog supply voltage DC input voltage ambient temperature storage temperature junction temperature
Min -0.5 -0.5 -0.5 -0.5 0 -25 -150
Max +2.1 +3.8 +2.1 +5.5 70 +125 +150
Unit V V V V C C C
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may effect device reliability.
16. Characteristics
Table 40: Symbol VCC_Core P VDDA P VCC_IO P VIH VIL VOH VOL Ci Co ILI Ii(n) Characteristics Parameter digital core supply voltage power dissipation analog supply voltage power dissipation during disc recognition only I/O pins supply voltage power dissipation during disc recognition only HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input capacitance output capacitance input leakage current input current on any pin except supplies Min 1.65 90 1.65 3.0 2.0 Typ 1.8 110 1.8 40 3.3 70 Max 1.95 150 1.95 60 3.6 100 Unit V mW V mW V mW
Power supply: VCC_Core (digital core supply voltage)
Power supply: VDDA (analog supply voltage)
Power supply: VCC_IO (I/O pins supply voltage)
Digital inputs and outputs VCC_IO + 0.5 V 0.8 0.4 10 10 10 10 V V V pF pF A mA
VCC_IO - 0.4 -
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17. Package outline
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SOT425-1
c
y X
A 102 103 65 64 ZE
e E HE A A2 A 1
(A 3) Lp L detail X
wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 0o
o
22.15 16.15 21.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
Fig 60. LQFP128 (SOT425-1) package outline.
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18. Soldering
18.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
18.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferably be kept:
* below 220 C for all the BGA packages and packages with a thickness 2.5mm
and packages with a thickness <2.5 mm and a volume 350 mm3 so called thick/large packages called small/thin packages.
* below 235 C for packages with a thickness <2.5 mm and a volume <350 mm3 so 18.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
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* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
18.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
18.5 Package related soldering information
Table 41: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] Reflow[2] suitable suitable
suitable not recommended[4][5] not recommended[6]
suitable suitable suitable
[3]
[4] [5] [6]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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19. Revision history
Table 42: Rev Date 02 20030226 Revision history CPCN Description Product data (9397 750 10925) Modifications:
* * * * *
01 20021014 -
The value of the capacitor to pin Adcrefl in Figure 44 is changed from 10 nF to 100 nF The system clock definitions are added in Section 7.5.1 The audio clock definitions are added in Section 7.5.2 A remark is added at the end of Section 8.2. A note is added to Table 11.
Product data (9397 750 10341)
9397 750 10925
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20. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
21. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
23. Trademarks
Dolby -- Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation.
22. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 10925
Fax: +31 40 27 24825
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Product data
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SAA7893HL
Super audio media player
Contents
1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 HW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System configuration . . . . . . . . . . . . . . . . . . . . 4 SACD playback. . . . . . . . . . . . . . . . . . . . . . . . . 4 Audio postprocessing . . . . . . . . . . . . . . . . . . . . 4 SACD data and text . . . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . 11 Front-end interface . . . . . . . . . . . . . . . . . . . . . 11 Audio interface . . . . . . . . . . . . . . . . . . . . . . . . 12 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . 12 Clock and reset input . . . . . . . . . . . . . . . . . . . 12 Test inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General description. . . . . . . . . . . . . . . . . . . . . 14 SAD16_01/02 mode . . . . . . . . . . . . . . . . . . . . 15 SAD16_03 mode . . . . . . . . . . . . . . . . . . . . . . 19 MAD16_01 mode . . . . . . . . . . . . . . . . . . . . . . 25 MAD16_02 mode . . . . . . . . . . . . . . . . . . . . . . 30 SAD08 mode . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Front-end interface . . . . . . . . . . . . . . . . . . . . . 37 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . . 38 UDE data interface . . . . . . . . . . . . . . . . . . . . . 40 FEC interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 HF input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HF input specification . . . . . . . . . . . . . . . . . . . 45 HF-input application diagram . . . . . . . . . . . . . 46 Audio interfaces. . . . . . . . . . . . . . . . . . . . . . . . 46 Audio input interface . . . . . . . . . . . . . . . . . . . . 46 Audio output interface . . . . . . . . . . . . . . . . . . . 47 Audio output application diagrams . . . . . . . . . 51 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . 54 12.1 12.2 12.3 13 14 14.1 14.2 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface connection . . . . . . . . . . . . . . . . . . . . Power supply connections . . . . . . . . . . . . . . . Software API . . . . . . . . . . . . . . . . . . . . . . . . . . API provided by SA-MP . . . . . . . . . . . . . . . . . API required by SA-MP . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 55 56 57 58 58 59 60 60 61 62 62 62 62 63 63 64 65 65 65 65
(c) Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 February 2003 Document order number: 9397 750 10925

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