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December 1998
ML6696* 100BASE-X Fiber Physical Layer
GENERAL DESCRIPTION
The ML6696 implements the complete physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the MII (Media Independent Interface) for interface to upper-layer silicon. The ML6696 integrates the data quantizer and the LED driver, allowing the use of low cost optical PMD components. The ML6696 includes 4B/5B encoder/decoder, 125MHz clock recovery/clock generation, LED driver, and a data quantizer. The device also offers a power down mode which results in total power consumption of less than 20mA. The ML6696 is suitable for the current 100BASE-FX IEEE 803.2u standard defined using 1300nm optics, as well as for the proposed 100BASE-SX standard defined using lower cost 820nm optics
FEATURES
s s s s s s s
100BASE-FX physical layer with MII Optimal 100BASE-SX solution (draft standard) Integrated data quantizer (post-amplifier) Integrated LED driver 125MHz clock generation and recovery 4B/5B encoding/decoding Power-down mode
* Some Packages Are Obsolete
BLOCK DIAGRAM
CLKREF TXCLK CLOCK SYNTHESIZER
TXER TXEN TXD3 TXD2 TXD1 TXD0 MDC MDIO COL CRS CARRIER & COLLISION LOGIC MII SERIAL MANAGEMENT INTERFACE PCS TRANSMIT STATE MACHINE AND 4B/5B ENCODER
IOUT SERIALIZER NRZ TO NRZI ENCODER IOUT LED DRIVER RTSET
ECLK INITIALIZATION INTERFACE EDIN EDOUT
RXCLK RXER RXDV RXD3 RXD2 RXD1 RXD0 CAPB CAPDC PCS RECEIVE STATE MACHINE AND 4B/5B DECODER
DESERIALIZER
CLOCK & DATA RECOVERY NRZI TO NRZ ENCODER
DATA QUANTIZER (POST AMPLIFIER)
VIN+ VIN- LINK100
1
ML6696
PIN CONFIGURATION
ML6696 52-Pin PLCC (Q52)
TXEN TXD0 TXD1 TXD2 TXD3 AGND1 CLKREF AVCC1 EDIN ECLK EDOUT AVCC2 AGND2
7 6 5 4 3 2 1 52 51 50 49 48 47 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 NC NC CAPDC CAPB AGND4B
46 45 44 43 42 41 40 39 38 37 36 35 34
IOUT IOUT AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A LINK100 AVCC4B AVCC4B VIN+ VIN-
TOP VIEW
ML6696 64-Pin TQFP (H64-10)
AGND1 AGND2 AGND2 AGND2 EDOUT CLKREF AVCC1 EDIN AVCC2 TXD0 TXD1 TXD2 TXD3 TXEN TXER ECLK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TXCLK RXD3 DGND1 DGND1 DGND1 RXD2 DVCC1 RXD1 DGND2 DGND2 DGND2 RXD0 RXCLK CRS COL DGND3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 IOUT IOUT IOUT IOUT AGND3 AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A LINK100 AVCC4B AVCC4B VIN+ VIN-
DGND3
DVCC2
RXDV
RXER
DGND4
DVCC5
MDC
MDIO
DGND5
DGND5
NC
NC
CAPB
AGND4B
TOP VIEW
2
AGND4B
CAPDC
ML6696
PIN DESCRIPTION
PIN NAME
(Pin Number in Parentheses is for PLCC Version)
PIN NAME FUNCTION
FUNCTION
1 (9)
TXCLK
Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of this clock. Receive data TTL output. Output is valid on RXCLK's rising edge. Digital ground Receive data TTL output. Output is valid on RXCLK's rising edge. Digital positive power supply
16, 17 (20) DGND3 18 (21) RXDV
Digital ground Receive data valid TTL output. This output is high when the ML6696 is receiving a data packet. RXDV is valid on RXCLK's rising edge. Digital positive power supply Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER is valid on RXCLK's rising edge. MII Serial Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6696's MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz. MII Serial Management Interface data TTL input/output. Serial data are written to and read from the management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Output data is valid on MDC's rising edge Digital ground Digital positive power supply Digital ground No connect Data quantizer offset-correction loop, offset-storage capacitor input pin. The capacitor tied between this pin and AVCC stores the amplified data quantizer offset voltage and also sets the dominant pole in the offset-correction loop. A 0.1F surface mount is recommended.
2 (10)
RXD3
19 (22) DVCC2 20 (23) RXER
3, 4, 5, (11) DGND1 6 (12) 7 (13) 8 (14) RXD2 DVCC1 RXD1
21 (24) MDC Receive data TTL output. Output is valid on RXCLK's rising edge. Digital ground Receive data TTL output. Output is valid on RXCLK's rising edge. Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at VIN+/-. Receive data are clocked out at RXD<3:0> on the falling edges of this clock, and should be sampled on rising edges. RXCLK is phasealigned to CLKREF in the absence of a 100BASE-FX signal at VIN+/-. Carrier Sense TTL output. CRS goes high in the presence of nonidle signals at VIN+/-, or when the ML6696 is transmitting. CRS goes low when there is no transmit activity and receive is idle. In repeater or full-duplex mode, CRS goes high in the presence of nonidle signals at VIN+/- only. Collision Detected TTL output. COL goes high upon detection of a collision on the network, and remains high as long as the collision condition persists. COL is low when the ML6696 operates in full-duplex, repeater, or loopback modes. 22 (25) MDIO
9, 10, 11 (15) DGND2 12 (16) RXD0 13 (17) RXCLK
23 (26) DGND4 24 (27) DVCC5 25, 26 (28) DGND5 27, 28 (29, 30) NC 29 (31) CAPDC
14 (18) CRS
15 (19) COL
3
ML6696
PIN DESCRIPTION
PIN NAME
(Pin Number in Parentheses is for PLCC Version) (Continued)
PIN NAME FUNCTION
FUNCTION
30 (32) CAPB
Data quantizer input bias bypass capacitor input. The capacitor tied between this pin and AVCC filters the quantizer's internal input bias reference. A 0.1F surface-mount capacitor is recommended. Analog ground Receive quantizer negative input. This input should be tied to AVCCQ through an AC coupling capacitor. (0.01F recommended) Receive quantizer positive input. This input receives 100BASE-FX signals from the network optical receiver through an AC coupling capacitor. (0.01F recommended). Analog positive power supply 100BASE-FX link activity opendrain output. LINK100 pulls low when there is 100BASE-FX activity at VIN+/-. This output is capable of sinking sufficient current to directly drive a status LED in series with a current limiting resistor. Analog ground
47, 48 (46) IOUT
Transmit LED output. This opencollector current output drives NRZI waveforms into a network LED. Analog ground Analog positive power supply Initialization Interface data out CMOS input. With EDIN low at power up, EDOUT has no function. With EDIN floating at power up, EDOUT is the serial data input for configuration data from an EEPROM. With EDIN high at power up, EDOUT is the input for configuration data from an external microcontroller. (Table 1) Initialization Interface clock CMOS input/output. With EDIN low at power up, ECLK is inactive. With EDIN floating at power up, ECLK is the ML6696's clock output for timing the configuration data from an external EEPROM. With EDIN high at power up, ECLK is the clock input for timing configuration data from an external microcontroller. (Table 1) Initialization Interface mode select and EEPROM interface data in CMOS input/output. EDIN selects one of three possible interface modes at power up. See the Initialization Interface section for more information. (Table 1) Analog positive power supply Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal TX PLL clock synthesizer and logic. This pin should be driven by an external 25MHz clock at TTL levels. Analog ground Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK.
31, 32 (33) AGND4B 33 (34) V IN-
49, 50, 51 (47) AGND2 52 (48) AVCC2 53 (49) EDOUT
34 (35) V IN+
35, 36 (36, 37) AVCC4B 37 (38) LINK100
54 (50) ECLK
38 (39) AGND4A 39 (40) AVCC4A 40 (41) AVCC3B 41 (42) AVCC3A 42 (43) RTSET
55 (51) EDIN Analog positive power supply Analog positive power supply Analog positive power supply Transmit level bias resistor. For 100BASE-FX, an external 2.32kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current that gives a nominal output "on" current of 75mA at IOUT. Analog ground 58 (2) Transmit LED output. This pin connects through an external 15W resistor to AVCC when the part is used to drive a network LED. 59 (3) AGND1 TXD3 56 (52) AVCC1 57 (1) CLKREF
43, 44 (44) AGND3 45, 46 (45) IOUT
4
ML6696
PIN DESCRIPTION
PIN NAME
(Pin Number in Parentheses is for PLCC Version) (Continued)
PIN NAME FUNCTION
FUNCTION
60 (4)
TXD2
Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK.
63 (7)
TXEN
Transmit enable TTL input. Driving this input high indicates to the ML6696 that transmit data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK. Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit an H symbol (00100). When TXEN is low, TXER has no effect.
61 (5)
TXD1
64 (8)
TXER
62 (6)
TXD0
5
ML6696
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range ............................ -0.3V to 6V Input Voltage Range Digital Inputs ........................................... -0.3V to VCC VIN+, VIN-, CLKREF, CAPB, CAPDC ........ -0.3V to VCC Output Current IOUT, IOUT ........................................................ 90mA All Other Outputs ............................................... 10mA Junction Temperature .................................... 0C to 125C Storage Temperature ................................. -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (qJA) TQFP ............................................................... 52C/W PLCC ............................................................... 40C/W
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C RTSET .......................................................... 2.32kW 1% VCC Supply Voltage .............................. ........... 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other.
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V 5%, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TTL INPUTS (TXD<3:0>, CLKREF, MDC, MDIO, TXEN, TXER) VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400A IIH = 100A VIN = 0.4V VIN = 2.4V -0.3 2.0 -200 100 0.8 VCC+0.3 V V A A
TTL OUTPUTS (RXD<3:0>, RXCLK, RXDV, RXER, CRS, COL, MDIO, TXCLK) VOL VOH Output Low Voltage Output High Voltage IOL = 4mA IOH = -4mA 2.4 0.4 V V
CMOS INPUTS (EDIN, EDOUT, ECLK) V ILC V IHC Input Low Voltage Input High Voltage 0.8 VCC 0.1 VCC 0.9 VCC 0.2 VCC V V
CMOS OUTPUTS (ECLK) VOLC V OHC Output Low Voltage Output High Voltage IOL = 2mA IOL = -2mA V
V
RECEIVER (VIN+, VIN-) V ICM VID RIDR V SDA AHYST Input Common-Mode Voltage Differential Input Voltage Range Differential Input Resistance Signal Detect Assertion Threshold Input Hysteresis Peak-to-Peak Non-idle Signal Level at VIN+/VCC = 5V 3.5 500 8 1.5 2.5 1600 1000 12 2 V mVP-P W mVP-P dB
6
ML6696
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER TRANSMITTER (IOUT, IOUT) ILEDH ILEDL IRT IOUT High Output Current Low Output Current RTSET Input Current RTSET = 2.32kW 1% RTSET = 2.32kW 1% RTSET = 2.32kW 1% 486 540 67.5 75 82.5 0.1 594 mA mA A
(Continued)
CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY CURRENT ICC I CCPD Supply Current, 100BASE-FX, Transmitting Supply Current, Power-Down Mode Current into All VCC Pins Current into All VCC Pins 200 295 20 mA mA
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V 5%, TA = Operating Temperature Range (Note 1)
SYMBOL TRANSMITTER tCLK tTXP tTR/F t TDC RECEIVER tRXDC tRXDR Receive Bit Delay (CRS) Receive Bit Delay (RXDV) Note 3 Note 4 15.5 25.5 bit times bit times CLKREF - TXCLK Delay Transmit Bit Delay IOUT Rise /Fall Time IOUT Output Duty Cycle Disotrtion Note 2 Note 3 Note 3 -0.5 5 11 10.5 2 0.5 ns bit times ns ns PARAMETER CONDITIONS MIN TYP MAX UNITS
MII INTERFACE XNTOL t TPWH t TPWL tRPWH tRPWL t TPS t TPH tRCS tRCH tRPCR tRPCF CLKREF Input Clock Frequency Tolerance TXCLK Pulse Width High TXCLK Pulse Width Low RXCLK Pulse Width High RXCLK Pulse Width Low Setup Time, TXD<3:0> Data Valid to TXCLK Rising Edge Hold time, TXD<3:0> Data Valid After TXCLK Rising Edge Time That RXD<3:0> Data are Valid Before RXCLK Rising Edge Time That RXD<3:0> Data are Valid After RXCLK Rising Edge RXCLK 10%-90% Rise Time RXCLK 90%-10% Fall Time Note 5 Note 5 Note 6, 7 Note 6, 7 25MHz Frequency -50 14 14 14 14 5 0 10 10 6 6 50 ppm ns ns ns ns ns ns ns ns ns ns
7
ML6696
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER MII MANAGEMENT INTERFACE (MDC, MDIO) tSPWS tSPWH tSPRS tSPRH tCPER t CPW Write Setup Time, MDIO Data Valid to MDC Rising Edge (1.4V Point) Write Hold Time, MDIO Data Valid After MDC Rising Edge (1.4V Point) Read Setup Time, MDIO Data Valid to MDC Rising Edge (1.4V Point) Read Hold Time, MDIO Data Valid After MDC Rising Edge (1.4V Point) Period of MDC Pulsewidth of MDC Positive or Negative Pulses 10 10 100 0 400 160 ns ns ns ns ns ns
(Continued)
CONDITIONS MIN TYP MAX UNITS
EEPROM INTERFACE (ECLK, EDIN, EDOUT) t PW1 t PW2 tPER1 t DV1 tPER2 t PW3 t PW4 tS1 t H1 ECLK Positive Pulsewidth ECLK Negative Pulsewidth ECLK Period EDOUT Data Valid Time After ECLK Rising Edge ECLK Period ECLK Positive Pulsewidth ECLK Negative Pulsewidth ECLK Data Setup Time ECLK Data Hold Time EDIN Floating (EEPROM Mode) EDIN Floating (EEPROM Mode) EDIN Floating (EEPROM Mode) EDIN Floating (EEPROM Mode) EDIN High (Microcontroller Mode) EDIN High (Microcontroller Mode) EDIN High (Microcontroller Mode) EDIN High (Microcontroller Mode) EDIN High (Microcontroller Mode) 5000 2000 2000 10 10 900 900 1800 900 ns ns ns ns ns ns ns ns ns
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI. Note 3: From first bit of J at the MDI, to CRS. Note 4: From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high. Note 5: Measured between the time that TXD0-3 transition above or below the region 0.8V-2.0V, and the time that TXCLK rises above 0.8V. Note 6: Measured between the time that RXD0-3 transition above or below the region 0.8V-2.0V, and the time that RXCLK rises above 0.8V. Note 7: Measured using a 15pF load to ground.
8
ML6696
TXCLKIN tTPWH tTPWL
TXCLK
TXD<3:0> TXER TXEN tTPS tTPH
Figure 1. MII Transmit Timing
tRPCR RXCLK
tRPCF
RXD<3:0> RXER RXDV tRCS tRCH
Figure 2. MII Receive Timing
MDC
MDIO
tSPWS
tSPWH
Figure 3. MII Management Interface Write Timing
9
ML6696
tCPER
MDC tSPRS tSPRH tCPW tCPW
MDIO
Figure 4. MII Management Interface Read Timing
tPW1 ECLK (DRIVEN BY ML6696) 01 02 03 04 05 06
tPW2 07 08 09
tPER1 10 11 12 13 26
EDIN (DRIVEN BY ML6696)
SB 1
OP1 1
OP0 0
A5 0
A4 0
A3 0
A2 0
A1 0
A0 0
EDOUT (DRIVEN BY EEPROM)
D0
D1 tDV1
D2
D3
D14
D15
16 BITS DATA ADDRESS
Figure 5. EEPROM Interface Timing
tPW3 01 ECLK (INPUT TO ML6696) tS1 EDOUT (INPUT TO ML6696) 02
tPER2 16
tPW4
H
Figure 6. MII Management Interface Read Timing
10
ML6696
FUNCTIONAL DESCRIPTION
FIBER OPTIC TRANSMITTER The on-chip transmit PLL converts a 25MHz TTL-level clock at CLKREF to an internal 125MHz bit clock. TXCLK from the ML6696 clocks transmit data from the MAC into the ML6696's TXD<3:0> input pins upon assertion of TXEN. Data from the TXD<3:0> inputs are 5-bit encoded and converted from parallel to serial form at the 125MHz clock rate. The ML6696 drives corresponding NRZI data out from its LED driver. The LED driver at IOUT is a current mode switch which develops the output light by sinking current through the network LED into IOUT. RTSET's value determines the output current: RTSET = . 125V 140W IOUT (1) ML6696 PHY MANAGEMENT FUNCTIONS The ML6696 has management functions controlled by the register locations given in Table 3 (page 12). There are two 16-bit management registers, with several unused locations. Register 0 is the basic control register (read/ write). Register 1 is the basic status register (read-only). The ML6696 powers on with all management register bits set to their default values. The ML6696's status and control register addresses and functions match those described for the MII in IEEE 802.3u section 22. IEEE 802.3u specifies the management data frame structure in section 22.2.4.4. See IEEE 802.3u section 22.2.4 for a discussion of MII management functions and status/control register definitions. INITIALIZATION INTERFACE The ML6696 has an Initialization Interface to allow register programming that is not supported by the MII Management Interface. The intitialization data is loaded at power-up and cannot be changed afterwards. The pin EDIN selects one of three possible programming modes. The Initialization Register bit assignment is shown in Table 2. EEPROM PROGRAMMING With EDIN floating (set to a high impedance), the ML6696 reads the 16 configuration bits from an external serial EEPROM (93LC46 or similar) using the industrystandard 3-wire serial I/O protocol. After power up, the ML6696 automatically generates the address at EDIN and the clock at ECLK to read out the 16 configuration bits. The EEPROM generates the configuration bit stream at EDOUT, synchronized with ECLK. Interface timing is shown in Figure 5. It is important to note that the ML6696 expects LSBs first, whereas the 93LC46 shifts MSBs out first. Therefore, the data pattern must be reversed before programming it into the EEPROM. MICROCONTROLLER PROGRAMMING With EDIN high, the ML6696 expects the 16 configuration bits transfered directly at EDOUT, synchronized with the first 16 clock rising edges provided externally at ECLK after power-up. This mode is useful with a small microcontroller; one controller can program several ML6696 parts by selectively toggling their ECLK pins. Interface timing is shown in Figure 6. ML6696 HARD-WIRED DEFAULT With EDIN low, the ML6692 responds to MII PHYAD 00000 only. "ISODIS" bit and "REPEATER" bit are 0.
where IOUT is the desired output current. Driving TXEN low will cause the ML6696's transmitter to enter the idle state and output 62.5MHz idle signal. Driving TXER high when TXEN is high causes the H symbol (00100) to appear in the transmitted data stream. The media access controller asserts TXER synchronously with TXCLK's rising edge, and the H symbol appears in place of valid symbols in the current frame. FIBER OPTIC RECEIVER The data quantizer accepts data at the VIN+/- pins that is above the internally-set 10mVpp threshold (typical). The receive PLL extracts clock from the quantizer's output, providing jitter attenuation, and clocks the signal through the serial-to-parallel converter. The resulting 5-bit symbols are aligned and decoded, and appear at RXD<3:0>. The ML6696 asserts RXDV when it's ready to present properly decoded receive data at RXD<3:0>. The extracted clock appears at RXCLK. The receiver strips out 62.5MHz idle between data packets. The receiver will assert RXER high if it detects errors in the receive data or idle stream. COLLISION AND CRS COL goes high to indicate simultaneous 100BASE-FX receive and transmit activity (a collision). CRS goes high whenever there is either receive or transmit activity in default mode, or only when there is receive activity in repeater or full-duplex mode. CLOCK INPUT The ML6696 requires an accurate 25MHz reference at CLKREF for internal clock generation (50ppm, see parameter XNTOL).
11
ML6696
FUNCTION OF RELATED PINS EDIN Floating (EEPROM ADDR) High Low MODE EEPROM Microcontroller Hardwired ECLK EDOUT ECLK (Output clock to EEPROM) EDOUT (Input data from EEPROM) ECLK EDOUT (Input clock from Microcontroller) (Input data from Microcontroller) No Effect No Effect Table 1. ML6696 Pin Function
BIT(S) i.15 i.14 i.13 i.12 i.11 i.10 - i.8 i.7 i.6 i.5 - i.0
NAME PHY A4 PHY A3 PHY A2 PHY A1 PHY A0 ISODIS REPEATER
DESCRIPTION PHY address bit 4 PHY address bit 3 PHY address bit 2 PHY address bit 1 PHY address bit 0 Not Used Isolate bit disable (bit 0.10) Repeater mode: when set to 1, CRS is only asserted when receiving non-idle signal at IN+/-, and ML6696 is forced to half duplex mode. Not Used Table 2. Initialization Interface Register
DEFAULT 0 0 0 0 0 0 0
12
ML6696
BIT(S) 1.14 1.13 1.12-1.3 1.2 1.1 - 1.0 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6 - 0.0 Duplex mode Collision Test Power down Isolate NAME 100BASE-X Full Duplex 100BASE-X Half Duplex Link Status DESCRIPTION 1=Full duplex 100BASE-X capability 0=No full duplex 100BASE-X capability 1=Half duplex 100BASE-X capability 0=No half duplex 100BASE-X capability Not used 1=One and only one PHY-specific link is up 0=Link is down Not used 1=Reset registers 0 and 1 to default values 0=Normal operation 1=PMD loopback mode 0=Normal operation 1=100Mb/s 0=10Mb/s Not used 1=Power down 0=Normal operation 1=Electrically isolate the ML6696 from MII 0=Normal operation Not used 1=Full duplex select 0=Half duplex select 1=Enable COL signal test 0=Normal operation Not Used R/W RO RO RO RO,LL RO R/W, SC R/W R/W RO R/W R/W RO R/W R/W RO DEFAULT i.6 1 0 0 0 0 0 1 0 0 i.7 0 i.6 0 0
Reset Loopback Manual Speed Select
Table 3. Management Register Function Bit Locations (Registers 0, 1)
13
ML6696
C3 0.1F DVCC 5V VCC U2 EC1400SJ-TS-25MHz 25MHz OSC 1 4 NC VCC 2 3 GND OUT AVCC DVCC U6 93LC46B 1 CS VCC 2 SK NC 3 DI NC 4 D0 DGND 8 7 6 5
P1 MII CONNECTOR 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC CRS COL TXD3 TXD2 TXD1 TXD0 TXEN TXCK TXER RXER RXCK RXDV RXD0 RXD1 RXD2 RXD3 MDC MDIO VCC 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
C9 0.1F
C10 0.1F
C13 0.1F
R6 15 C6, 0.1F C29, 0.001F C26, 10F
TXEN TXD0 TXD1 TXD2 TXD3 AGND1 CLKREF AVCC1 EDIN ECLK EDOUT AVCC2 AGND2
AGND
R7, 3k U4* 1 NC CATHODE 4 NC NC 5 NC ANODE1 8 NC ANODE2 AVCCQ D1 LED VCC
C17 0.1F
DGND
DVCC
5V VCC
TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 C16 0.1F
U3 ML6696CQ
IOUT IOUT AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A LINK100 AVCC4B AVCC4B VIN+ VIN- C30 0.01F
R8*
C12 0.1F AGND C13 0.1F
3 7 2 6 AVCC
R1 500
RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 NC NC CAPDC CAPB AGND4B
C14 0.1F C31 0.01F
DVCC
C15 0.1F
C4 0.1F
AGNDQ C5 0.1F AVCCQ
U5* 1 2 NC ASIGOUT 4 3 NC GND 5 7 NC GND 8 6 NC VCC AGNDQ
DVCC D3 FX_RCVLED D2 FX_TXLED
DVCC D4 14 13 12 11 10 9 8 U1 74HC04 1234567 R4 100k
0.1F
D5 C2 22nF R5 100k C2 22nF AVCCQ
DVCC
R4 470 FB4
R4 470
C25 10F
C28 0.01F
C22 0.1F
C20 0.1F FB3 FB1
C8 0.1F
AVCC C24 10F AGND
U4* 850nm 1300nm HFBR-1414 HFBR-1312T
U5* HFBR-2416 HFBR-2316T
R8* 2.87kW 2.32kW
C25 10F DGND
C28 0.01F
C22 0.1F
C20 0.1F FB2
C8 0.1F
AVCCQ C24 10F AGNDQ
Figure 7. ML6696 Typical Application Schematic
14
ML6696
PHYSICAL DIMENSIONS
inches (millimeters)
Package: Q52 52-Pin PLCC
0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22) 14
PIN 1 ID 0.750 - 0.754 0.785 - 0.795 (19.05 - 19.15) (19.94 - 20.19) 0.600 BSC (15.24 BSC) 0.690 - 0.730 (17.53 - 18.54)
40
27 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
Package: H64-10 64-Pin (10 x 10 x 1mm) TQFP
0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 49 0 - 8 0.003 - 0.008 (0.09 - 0.20)
1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC)
33 17 0.020 BSC (0.50 BSC) 0.007 - 0.011 (0.17 - 0.27) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05)
0.018 - 0.030 (0.45 - 0.75)
SEATING PLANE
15
ML6696
ORDERING INFORMATION
PART NUMBER ML6696CH (Obsolete) ML6696CQ TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 64-Pin TQFP (H64-10) 52-Pin PLCC (Q52)
(c) Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
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DS6696-01

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