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KS7306
GENERAL DESCRIPTION
DIGITAL CAMERA PROCESSOR
100-QFP-1414 KS7306 is a CCD digital signal processor. The electronic video signal that passed the color filter array(CFA) pattern of CCD is put to the process of dual correlation sampling and then converted to digital video signal by A/D converter. Taking the digital video signal so processed as an input, KS7306 performs luminance and chroma signal process and finally outputs signals encoded to NTSC/PAL broadcast standards, and generates detection signals for AE/AF/AWB.
ORDERING INFORMATION FEATURES
* * * * * * * * * * * * *
Device KS7306 Package 100-QFP-1414
Operating Temperature
0 ~ 70 C
Offers 10 bit input digital signal processing. Carries built-in 2H line memory.(10bit 1024) Performs Y signal processing. Performs C signal processing. Carries an encorder capable to NTSC/PAL dual form application. Carries built-in Y/C 2-channal DA converter. Carries built-in AE/AF/AWB detection system. Provides micom parallel interface. Micom capable to control variable parameters. Offers digital effects interfacing Suites Hi8/Normal CCD application. Suites 470K,520K,570K and 620K CCD controlled EIS system application. Supports 16:9 aspect wide TV (full mode) application.
APPLICATIONS
CCD camera ( camcorder, CCTV, digital still camera, etc.).
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PIN CONFIGURATION
DIGITAL CAMERA PROCESSOR
DZCSYNCI
DZCBLKI
VDDPO
VSSPO
DZBFII
TST2
VSSI
YO7
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 DZCBLKO
UVIO3 76 UVIO2 77 UVIO1 78 UVIO0 79 VDDI 80 UVO3 81 UVO2 82 UVO1 83 UVO0 84 VSSI 85 CD9 86 CD8 87 CD7 88 CD6 89 VDDPO 90 CD5 91 CD4 92 CD3 93 CD2 94 VSSPO 95 CD1 96 CD0 97 FSC4 98 CBLK 99 CSYNC 100 1 BF 2 LALT 3 ID 4 HD 5 VDDI 6 VD 7 LHLD 8 PCLK 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDPO VSSPO PBLK WRN NEC AS MD7 MD6 MD5 MD4 MD3 MD2 MD1 VSSI VSKIP RDN MD0
TST1 49 DZBFO 48 DZCSYNCO 47 UVCK 46 XCK 45 TST4 44 INDIR 43 VSSA 42 VDDA 41 AC 40 VREF 39 IREF 38 BCAP 37 AY 36 VDDA 35 VSSA 34 BFO 33 FSC 32 CSYNCO 31 AFZONE 30 TST3 29 VSYNC 28 HSYNC 27 HCON 26 RSTN
YO0
TEST
NTSC/PAL Encoder
VDDI
YO1
YO2
YO3
YO4
YO5
YO6
YI2
YI6
YI1
YI3
YI4
YI0
YI5
YI7
D/A C-Processor Y-Processor D/A
Line Memory
Pre-Processor
Optical Detector
Timing Interface
MICOM Interface
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PIN DESCRIPTION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol BF LALT ID HD VDDI VD LHLD PCLK PBLK VSSI NEC AS VSKIP WRN VDDPO RDN MD7 MD6 MD5 VSSPO MD4 MD3 MD2 MD1 MD0 RSTN HCON HSYNC VSYNC TST3 AFZONE CSYNCO FSC BFO VSSA I/O I I I I P I I I I G I I I I P I I/O I/O I/O G I/O I/O I/O I/O I/O I I O O O O O O O AG Burst Flag
DIGITAL CAMERA PROCESSOR
Description Line Alternation for PAL System Line Identifer Horizontal Driving Pulse Power Supply for Internal Logic Vetical Driving Pulse Line Hold Signal System Clock Pre-Blanking Pulse Ground for Internal Logic Ext. Micom select (NEC/SAM 8*) Address Strobe for Micom I/F Vertical Skip Pulse Write Enable (Active Low) for Micom I/F Power Supply for Input & Output PAD Read Enable (Active Low) for Micom I/F Micom Address & Data Port 7 Micom Address & Data Port 6 Micom Address & Data Port 5 Ground for Input & Output Pad Micom Address & Data Port 4 Micom Address & Data Port 3 Micom Address & Data Port 2 Micom Address & Data Port 1 Micom Address & Data Port 0 System Reset (Active Low) Horizontal Sync. Signal (S1,S2 Control) Horizontal Sync. Signal Vertical Sync. Signal Test Output 3 Auto Focus Window Zone Pulse Composite Sync. Output (Processor Delay Matched Signal) Color Subcarrier Signal Burst Flag Output (Processor Delay Matched Signal) Analog Ground
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(Continued) NO. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol VDDA AY BCAP IREF VREF AC VDDA VSSA INDIR TST4 XCK UVCK DZCSYNCO DZBFO DZCBLKO TST1 DZCBLKI DZBFI DZCSYNCI VDDI TST2 YI7 YI6 YI5 VSSI YI4 YI3 YI2 YI1 VDDPO YI0 YO7 YO6 TO5 VSSPO YO4 YO3 I/O AP O I I I O AP AG I O I O I/O I/O I/O I/O I/O I/O I/O P I/O I I I G I I I I P I O O O G O O Analog Power
DIGITAL CAMERA PROCESSOR
Description D/A Converted Luminance Signal Bypass Capacitor Port for D/A Converter Current Source Reference Port D/A Converter Voltage Source Reference Port D/A Converter D/A converted Chroma Signal Analog Power Analog Ground Input Mode Select for I/O Bidirectional Pin Test Output 4 External Clock for Multimedia PC R-Y / B-Y Identifier
Delay Matched Composite Sync. Output for Digital Zoom or Test I/O Delay Matched Burst Flag Output for Digital Zoom or Test I/O Delay Matched Composite Blank Output for Digital Zoom or Test I/O
Test I/O
Delay Matched Composite Blank input for Digital Zoom or Test I/O Delay Matched Burst Flag input for Digital Zoom or Test I/O Delay Matched Composite Sync. input for Digital Zoom or Test I/O
Power Supply for Internal Logic Test I/O Digital Zoom Processed Luminance Input 7 Digital Zoom Processed Luminance Input 6 Digital Zoom Processed Luminance Input 5 Ground for Internal Logic Digital Zoom Processed Luminance Input 4 Digital Zoom Processed Luminance Input 3 Digital Zoom Processed Luminance Input 2 Digital Zoom Processed Luminance Input 1 Power Supply for Input / Output Pad Digital Zoom Processed Luminance Input 0 Luminance Output 7 for Digital Zoom Luminance Output 6 for Digital Zoom Luminance Output 5 for Digital Zoom Ground for Input & Output Pad Luminance Output 4 for Digital Zoom Luminance Output 3 for Digital Zoom
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(Continued) NO. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol YO2 YO1 YO0 UVIO3 UVIO2 UVIO1 UVIO0 VDDI UVO3 UVO2 UVO1 UVO0 VSSI CD9 CD8 CD7 CD6 VDDPO CD5 CD4 CD3 CD2 VSSPO CD1 CD0 FSC4 CBLK CSYNC I/O O O O I/O I/O I/O I/O P O O O O G I I I I P I I I I G I I I I I
DIGITAL CAMERA PROCESSOR
Description Luminance Output 2 for Digital Zoom Luminance Output 1 for Digital Zoom Luminance Output 0 for Digital Zoom Digital Zoom Processed Chroma Input 3/4:2:2 Chroma Output 7 Digital Zoom Processed Chroma Input 2/4:2:2 Chroma Output 6 Digital Zoom Processed Chroma Input 1/4:2:2 Chroma Output 5 Digital Zoom Processed Chroma Input 0/4:2:2 Chroma Output 4 Power for Internal Logic Chroma Output 3 for Digital Zoom / 4:2:2 Chroma Output 3 Chroma Output 2 for Digital Zoom / 4:2:2 Chroma Output 2 Chroma Output 1 for Digital Zoom / 4:2:2 Chroma Output 1 Chroma Output 0 for Digital Zoom / 4:2:2 Chroma Output 0 Ground for Iternal Logic CCD Data Input 9 Precessed ADC or FCM CCD Data Input 8 Precessed ADC or FCM CCD Data Input 7 Precessed ADC or FCM CCD Data Input 6 Precessed ADC or FCM Power Supply for Input & Output Pad CCD Data Input 5 Precessed ADC or FCM CCD Data Input 4 Precessed ADC or FCM CCD Data Input 3 Precessed ADC or FCM CCD Data Input 2 Precessed ADC or FCM Ground for Input & Output Pad CCD Data Input 1 Precessed ADC or FCM CCD Data Input 0 Precessed ADC or FCM Color Subcarrier x 4 Composite Blank Signal Composte Sync. Signal
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ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Teminal input Voltage Power Dissipation Operating Temperature Storage Temperature Latch-Up Current Symbol VDD VI PD TORR TSTG ILU
DIGITAL CAMERA PROCESSOR
Value -0.3 to 7 -0.3 to VDD +0.3 700 0 ~ +70 -40 ~ +125 100
Unit V V mW
C C
mA
ELECTRICAL CHARACTERISTICS
DC Characteristics Operating Voltage Input Voltage output Voltage Operating Current Maximum Input Leakage Current AC Characteristics Input Data Setup Time Input Data Hold Time Symbol TSU THD Test Condition VDD = 55%, Ta = 0 ~70C VDD = 55%, Ta = 0 ~70C Min 5 5 Typ. Max 50 Unit nsec nsec Symbol VDD VIH VIL VOH VOL IDD IIH IIL Test Condition Ta = 25C Ta = 25C Ta = 25C IOH = -1mA IOL = 1mA VDD = 5V VI = 0~VDD VI = 0~VDD Min 4.75 0.7VDD 2.4 -10 -10 Typ 5.0 140 Max 5.25 0.3VDD 0.4 160 10 10 Unit V V V V V mA A A
PCLK THD TSU
CD9~0
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MICOM INTERFACE
1. NEC MICOM INTERFACE
DIGITAL CAMERA PROCESSOR
Characteristics Address setup time Address hold time AS pulse width RDN pulse width WRN pulse width Data delay from RDN,WRN Data hold time
Symbol Tast That Tasw Trdw Twrw Td Tdh
Min 15 35 35 400 400 0
Typ -
Max 100 -
Unit nsec nsec nsec nsec nsec nsec nsec
Tast
MD7~0
Tsaw
ADDR
Taht Td
DATA
Tdh
AS
Trdw
RDM
Twrw
READ Mode ( WRN = 1) WRITE Mode ( RDN = 1)
WRN
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KS7306
2. SAM8 MICOM INTERFACE
DIGITAL CAMERA PROCESSOR
Characteristics Address setup time Address hold time AS pulse width RDN pulse width WRN pulse width Data delay from RDN,WRN Data hold time
Symbol Tast That Tasw Trdw Twrw Td Tdh
Min 15 35 35 400 400 0
Typ -
Max 100 -
Unit nsec nsec nsec nsec nsec nsec nsec
Tast
MD7~0
Tsaw
ADDR
Taht Td
DATA
Tdh
AS
Trdw
RDM
READ Mode ( WRN = 1 ) WRITE Mode ( RDN = 1 )
WRN
Twrw
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SYSTEM DESCRIPTION
DIGITAL CAMERA PROCESSOR
The video data output from CCD go through CDS IC (KA7307) and become quantized by 10 bit ADC. For hand tremble correction in the CCD controlled gyro sensor method, the quatized video data are fed to FCM in which effective pixel section of the data gets corrected and extended, then the data are entered to the signal processor (KS7306) for YC coding so that the data are propely encoded to conform with NTSC/PAL broadcasting method. The encoded data is converted to analog signal by the built-in DAC and output Y.C signal finally. The camera embodies current video status detection function needed for AE/AF/AWB function as an automatic control provision of the camera system. The function of signal processing and video status detection is implemented by data communication with the micom through the parallel interfaces to allow setting of variable parameters, transmisson of detection signals, and reception of control signals that are necessary in the signal processing. The clock used in IC' s is supplied by a separate IC, the timining generator (KS7213). For the zooming, the Y,(R-Y)(B-Y) interface to the processing is provided. And the interface allows interfacing with IC' s for the option of other digital effects. The timing generator generates time pulse and video syncronizing signal required in all functional block of the camera system. The clock supports the vertical expansion mode especially required in CCD controlled gyro sensor and electronic zooming. Using the clock furnished by the clock generator, the digital zoom (KS7314) performs zooming by means of vertical interpolation of expanded CCD output and horizontal expansion and interpolation of the output. In this camera system, IC' s used for FCM, gyro, microcontroller, and DZ functions respectively are the ones required only in the system that employs CCD controlled gyro sensor and electronic zooming for optional funtions while a system pursuing electronic zooming alone requires employment of DZ IC only to achieve the purpose. The CCDs of 510H (NTSC/PAL) and 760H (NTSC/PAL) allow a range of system configurations that support 470K, 520K, and 620K (wobble correction CCD) pixels. The figure below illustrates the camera system.
A/D; Analog to Digital CCD; Charge Coupled Device FCM; Frquency Converting Memory DZ; Digital Camera Process DCP; Digital Camera Process TG; Timing Generator CCD CDS KA7307 A/D 10bit FCM KS7308 DCP KS7306 Y C Gyro uCOM DZ KS7314

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