View AD9411_419572.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

10-Bit, 170/200 MSPS 3.3 V A/D Converter AD9411
FEATURES
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (-0.5 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (-0.5 dBFS) Excellent linearity: DNL = 0.15 LSB (typical) INL = 0.25 LSB (typical) LVDS output levels 700 MHz full-power analog bandwidth On-chip reference and track-and-hold Power dissipation = 1.25 W typical @ 200 MSPS 1.5 V input voltage range 3.3 V supply operation Output data format option Clock duty cycle stabilizer Pin compatible to LVDS mode AD9430
FUNCTIONAL BLOCK DIAGRAM
SENSE VREF AGND DRGND DRVDD AVDD
SCALABLE REFERENCE
AD9411
VIN+ VIN-
TRACK AND HOLD
ADC 10 10-BIT PIPELINE / CORE
LVDS OUTPUTS
DATA, OVERRANGE IN LVDS
CLK+ CLK-
CLOCK MANAGEMENT
LVDS TIMING
DCO+ DCO-
04530-0-001
APPLICATIONS
Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization
S1
S5
Figure 1.
GENERAL DESCRIPTION
The AD9411 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 200 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The ADC requires a 3.3 V power supply and a differential sample clock for full performance operation. The digital outputs are LVDS compatible and support both twos complement and offset binary format. A data clock output is available to ease data capture. Fabricated on an advanced BiCMOS process, the AD9411 is available in a 100-lead surface-mount plastic package (e-PAD TQFP-100) specified over the industrial temperature range (-40C to +85C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. 2. 3. High performance. Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input. Low power. Consumes only 1.25 W @ 200 MSPS. Ease of use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold function provide flexibility in system design. Use of a single 3.3 V supply simplifies system power supply design. Out-of-range (OR). The OR output bit indicates when the input signal is beyond the selected input range.
4.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9411 TABLE OF CONTENTS
DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 Explanation of Test Levels ........................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology .................................................................................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 13 Application Notes ........................................................................... 18 Clock Input.................................................................................. 18 Analog Input ............................................................................... 18 LVDS Outputs............................................................................. 19 Clock Outputs (DCO+, DCO-)............................................... 19 Voltage Reference ....................................................................... 19 Noise Power Ratio Testing (NPR)............................................ 19 Evaluation Board ............................................................................ 21 Power Connector........................................................................ 21 Analog Inputs ............................................................................. 21 Gain.............................................................................................. 21 Clock ............................................................................................ 21 Voltage Reference ....................................................................... 21 Data Format Select ..................................................................... 21 Data Outputs............................................................................... 21 Clock XTAL................................................................................. 21 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
7/04--Data Sheet Changed from Rev. 0 to Rev. A Added 200 MSPS Grade ....................................................Universal Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 Rev 0 : Initial Version
Rev. A | Page 2 of 28
AD9411 DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, internal reference, full scale = 1.536 V, unless otherwise noted. Table 1.
AD9411-170 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Out (VREF) REFERENCE Reference Out (VREF) Output Current1 IVREF Input Current2 ISENSE Input Current ANALOG INPUTS (VIN+, VIN-)3 Differential Input Voltage Range (S5 = GND) Differential Input Voltage Range (S5 = AVDD) Input Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLY (LVDS Mode) AVDD DRVDD Supply Currents IANALOG (AVDD = 3.3 V)4 IDIGITAL (DRVDD = 3.3 V) Power Dissipation Power Supply Rejection
2 4 4
AD9411-200 Max Min Typ 12 Max Unit Bits
Temp
Test Level
Min
Typ 12
Full 25C 25C 25C Full 25C Full Full Full Full
VI I I I VI I VI V V V
Guaranteed -3 -5 -0.5 0.15 -0.6 0.25 -0.8 0.5 -1 0.5 58 0.02 +0.12/ -0.24 1.15 1.235
+3 +5 +0.5 +0.6 +0.8 +1
Guaranteed -3 -5 -0.5 0.15 -0.6 0.25 -0.8 0.5 -1 0.5 58 0.02 +0.12/ -0.24
+3 +5 +0.5 +0.6 +0.8 +1
mV % FS LSB LSB LSB LSB V/C %/C mV/C
25C 25C 25C 25C Full Full Full Full 25C Full Full Full Full Full 25C
I IV I I V V VI VI V IV IV VI VI VI V
1.6 1.536 0.766 2.65 2.2 2.8 3 5 3.3 3.3 335 49 1.27 -7.5
1.3 3.0 20 5.0
1.15
1.235
1.6 1.536 0.766
1.3 3.0 20 5.0
V mA mA mA V V
2.9 3.8
2.65 2.2
2.8 3 5 3.3 3.3 385 49 1.43 -7.5
2.9 3.8
V k pF V V mA mA W mV/V
3.1 3.0
3.6 3.6 372 57 1.42
3.2 3.0
3.6 3.6 425 57 1.59
1 2
Internal reference mode; SENSE = floats. External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference. 3 S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified 4 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, -0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the Typical Performance Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.
Rev. A | Page 3 of 28
AD9411 AC SPECIFICATIONS1
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, fIN = -0.5 dBFS, internal reference, full scale = 1.536 V, unless otherwise noted. Table 2.
AD9411-170 Parameter SNR Analog Input @ -0.5 dBFS 10 MHz 70 MHz 100 MHz 240 MHz SINAD Analog Input @ -0.5 dBFS 10 MHz 70 MHz 100 MHz 240 MHz EFFECTIVE NUMBER OF BITS (ENOB) 10 MHz 70 MHz 100 MHz 240 MHz WORST HARMONIC (Second or Third) Analog Input @ -0.5 dBFS 10 MHz 10 MHz 70 MHz 100 MHz 240 MHz WORST HARMONIC (Fourth or Higher) Analog Input @ -0.5 dBFS 10 MHz 10 MHz 70 MHz 100 MHz 240 MHz TWO-TONE IMD2 F1, F2 @ -7 dBFS ANALOG INPUT BANDWIDTH Temp Test Level Min Typ Max Min AD9411-200 Typ Max Unit
25C 25C 25C 25C
I I V V
59 59
60.2 60.1 60 59.1
59 59
60.2 60.1 60 59.1
dB dB dB dB
25C 25C 25C 25C 25C 25C 25C 25C
I I V V I I V V
58.5 58.5
60 60 59.5 57.5 9.8 9.8 9.7 9.3
58.5 58.5
60 60 59.5 57.5 9.8 9.8 9.7 9.3
dB dB dB dB Bits Bits Bits Bits
9.5 9.5
9.5 9.5
25C 25C 25C 25C
I I V V
-80 -80 -74 -69
-73 -73
-80 -80 -74 -69
-70 -70
dBc dBc dBc dBc
25C 25C 25C 25C 25C 25C
I I V V V V
-82 -82 -76 -70 70 700
-75 -75
-82 -82 -76 -70 70 700
-75 -75
dBc dBc dBc dBc dBc MHz
1 2
All ac specifications tested by driving CLK+ and CLK- differentially. F1 = 30.5 MHz, F2 = 31 MHz.
Rev. A | Page 4 of 28
AD9411 DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, unless otherwise noted. Table 3.
Parameter CLOCK INPUTS (CLK+, CLK-)1 Differential Input Voltage2 Common-Mode Voltage3 Input Resistance Input Capacitance LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Input Resistance Input Capacitance LVDS LOGIC OUTPUTS4 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding Temp Test Level Min AD9411-170 Typ Max Min AD9411-200 Typ Max Unit
Full Full Full 25C Full Full Full Full 25C 25C Full Full
IV VI VI V IV IV VI VI V V VI VI
0.2 1.375 3.2
1.5 5.5 4
1.575 6.5
0.2 1.375 3.2
1.5 5.5 4
1.575 6.5
V V k pF V V A A k pF mV V
2.0 0.8 190 10 30 4 247 454 1.125 1.375 Twos Complement or Binary
2.0 0.8 190 10 30 4 247 454 1.125 1.375 Twos Complement or Binary
1 2
See the Equivalent Circuits section. All ac specifications tested by driving CLK+ and CLK- differentially, |(CLK+) - (CLK-)| > 200 mV. 3 Clock inputs' common mode can be externally set, such that 0.9 V < CLK < 2.6 V. 4 LVDS RTERM = 100 , LVDS output current set resistor (RSET) = 3.74 k (1% tolerance).
Rev. A | Page 5 of 28
AD9411 SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = -40C, TMAX = +85C, unless otherwise noted. Table 4.
Parameter (Conditions) Maximum Conversion Rate1 Minimum Conversion Rate CLK+ Pulse Width High (tEH) CLK+ Pulse Width Low (tEL) OUTPUT (LVDS Mode) Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tPD-tCPD) Latency Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ)
1 1 1
Temp Full Full Full Full Full Full 25C 25C Full Full Full 25C 25C 25C
Test Level VI V IV IV VI VI V V VI IV IV V V V
Min 170 2 2 2.0
AD9411-170 Typ
Max
Min 200
AD9411-200 Typ Max
Unit MSPS MSPS ns ns ns ns ns ns ns ns Cycles ns ps rms Cycles
40 12.5 12.5
2 2 2.0
40 12.5 12.5
1.8 0.2
3.2 0.5 0.5 2.7 0.5 14 1.2 0.25
4.3
3.8 0.8
1.8 0.2
3.2 0.5 0.5 2.7 0.5 14 1.2 0.25
4.3
3.8 0.8
Out-of-Range Recovery Time
1
1
1
All ac specifications tested by driving CLK+ and CLK- differentially.
EXPLANATION OF TEST LEVELS
I. 100% production tested. II. 100% production tested at 25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
N-1 AIN N N+1
tEL tEH
1/fS CLK+ CLK-
tPD
DATA OUT N-14 N-13 14 CYCLES DCO+ DCO- N N+1
tCPD
Figure 2. LVDS Timing Diagram
Rev. A | Page 6 of 28
04530-0-002
AD9411 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD, DRVDD Analog Inputs Digital Inputs REFIN Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature JA1
1
Rating 4V -0.5 V to AVDD +0.5 V -0.5 V to DRVDD +0.5 V -0.5 V to AVDD +0.5 V 20 mA -55C to +125C -65C to +150C 150C 150C 25C/W, 32C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside of those indicated in the operation section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
Typical JA = 32C/W (heat slug not soldered); typical JA = 25C/W (heat slug soldered) for multilayer board in still air with solid ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 7 of 28
AD9411 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRGND DVRDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
OR+
OR-
D9+
D8+
D7+
77
D9-
D8-
78
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
76
D7-
S5 DNC AGND AGND AVDD S1 LVDSBIAS AVDD AGND
1 2 3 4 5 6 7 8 9
75 74 73 72 71 70 69 68 67 66 65
DRVDD DRGND D6+ D6- D5+ D5- D4+ D4- DRGND D3+ D3- DCO+ DCO- DRVDD DRGND D2+ D2- D1+ D1- D0+ D0- DRVDD DRGND DNC DNC
SENSE 10 VREF 11 AGND 12 AGND 13 AVDD 14 AVDD 15 AGND 16 AGND 17 AVDD 18 AVDD 19 AGND 20 VIN+ 21 VIN- 22 AGND 23 AVDD 24 AGND 25
AD9411
TOP VIEW (Not to Scale)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
AGND 26
AVDD 27
AVDD 28
AVDD 29
AGND 30
AGND 31
AGND 32
AVDD 33
AVDD 34
AGND 35
CLK+ 36
CLK- 37
AGND 38
AVDD 39
AVDD 40
AGND 41
DNC 42
DNC 43
DNC 44
DNC 45
DNC 46
DRVDD 47
DRGND 48
DNC 49
DNC 50
Figure 3. TQFP/EP Pinout
Rev. A | Page 8 of 28
04530-0-003
AD9411
Table 6. Pin Function Descriptions
Pin No. 1 2, 42-46,49-52 3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 6 7 10 11 21 22 36 37 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85 Mnemonic S5 DNC AGND AVDD S1 LVDSBIAS SENSE VREF VIN+ VIN- CLK+ CLK- DRVDD DRGND D0+ D1- D1+ D2- D2+ DCO- DCO+ D3- D3+ D4- D4+ D5- D5+ D6- D6+ D7- D7+ D8- D8+ D9- D9+ OR- OR+ Function Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential; GND sets FS = 1.536 V p-p differential. Do Not Connect. Analog Ground. AGND and DRGND should be tied together to a common ground plane. 3.3 V Analog Supply. Data Format Select. GND = binary; AVDD = twos complement. Set Pin for LVDS Output Current. Place a 3.74 k resistor terminated to ground. Reference Mode Select Pin. Float for internal reference operation. 1.235 V Reference Input/Output. Function depends on SENSE. Analog Input. True. Analog Input. Complement. Clock Input. True (LVPECL levels). Clock Input. Complement (LVPECL levels). 3.3 V Digital Output Supply (3.0 V to 3.6 V). Digital Output Ground. AGND and DRGND should be tied together to a common ground plane. D0 True Output Bit. D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. Data Clock Output. Complement. Data Clock Output. True. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. Overrange Complement Output Bit. Overrange True Output Bit.
Rev. A | Page 9 of 28
AD9411 TERMINOLOGY
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (-40 dBFS) signal when the adjacent interfering channel is driven by a fullscale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. Peak-to-peak differential is computed by rotating the input's phase 180 and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the clock pulse should be left in the Logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in the low state. Refer to the timing implications of changing tENCH in the Application Notes, Clock Input section. At a given clock rate, these specifications define an acceptable CLOCK duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation:
PowerFULLSCALE
V 2 FULLSCALE RMS = 10 log Z INPUT 0.001

Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Minimum Conversion Rate The CLOCK rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The CLOCK rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK- and the time when all output data bits are within valid logic levels.
SNRMEASURED - 1.76 dB ENOB = 6.02
Rev. A | Page 10 of 28
AD9411
Noise (for Any Range within the ADC) Calculated as follows:
- SNRdBc - Signal dBFS FS V NOISE = Z x 0.001 x 10 dBM 10
Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. Transient Response Time
where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics)
The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale).
The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Rev. A | Page 11 of 28
AD9411 EQUIVALENT CIRCUITS
AVDD
K
12k CLK+ 150 150 12k CLK-
FULL SCALE 0.1F VREF A1
1V
10k 10k
200
04530-0-004
1k DISABLE A1
SENSE
VDD
AVDD 3.5k 3.5k
Figure 7. VREF, SENSE I/O
DRVDD
VIN+ 20k 20k
VIN-
04530-0-005
V+ DX- V-
V- DX+ V+
04530-0-008
Figure 5. Analog Inputs
VDD
Figure 8. Data Outputs
S1,S5 30k
Figure 6. S1 to S5 Inputs
04530-0-006
Rev. A | Page 12 of 28
04530-0-007
Figure 4. Clock Inputs
AD9411 TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 -40 -50 SNR = 60.1dB SINAD = 59.9dB H2 = -91.3dBc H3 = -75.2dBc SFDR = 75.3dBc
0 -10 -20 -30 -40 -50
SNR = 59.7dB SINAD = 59.5dB H2 = -83.6dBc H3 = -72.6dBc SFDR = 72.5dBc
dB
dB
-60 -70 -80 -90 -100 -110
04530-0-009
-60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 MHz 60 70 80 90 100
-120 0 10 20 30 40 MHz 50 60 70 80
Figure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ -0.5 dBFS
0 -10 -20 -30 -40 -50 SNR = 59.8dB SINAD = 59.8dB H2 = -91.9dBc H3 = -80.6dBc SFDR = 73.2dBc
Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ -0.5 dBFS
0 -10 -20 -30 -40 -50
SNR = 59.5dB SINAD = 59.4dB H2 = -82.5dBc H3 = -72.8dBc SFDR = 72.7dBc
dB
dB
-60 -70 -80 -90 -100 -110
04530-0-010
-60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 MHz 60 70 80 90 100
-120 0 10 20 30 40 MHz 50 60 70 80
Figure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ -0.5 dBFS
0 -10 -20 -30 -40 -50 SNR = 59.2dB SINAD = 59.1dB H2 = -70.1dBc H3 = -87.0dBc SFDR = 69.8dBc
Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ -0.5 dBFS
0 -10 -20 -30 -40 -50
SNR = 50.6dB SINAD = 43.8dB H2 = -44.8dBc H3 = -67.4dBc SFDR = 43.6dBc
dB
dB
-60 -70 -80 -90 -100 -110
04530-0-011
-60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 MHz 60 70 80 90 100
-120 0 10 20 30 40 MHz 50 60 70 80
Figure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ -0.5 dBFS, Single-Ended Input, 0.76 V Input Range
Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ -0.5 dBFS, Single-Ended Drive, 1.5 V Input Range
Rev. A | Page 13 of 28
04530-A-003
04530-A-002
04530-A-001
AD9411
100
0 -10 SFDR = 71.5dBc
90
-20 -30
80 THIRD SFDR dB 70 SECOND
dB
04530-0-015
-40 -50 -60 -70
60
-80 -90
50
-100 -110
0
50
100
150
200 AIN (MHz)
250
300
350
400
0
10
20
30
40 MHz
50
60
70
80
Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency @ 170 MSPS
100 0
Figure 18. Two-Tone Intermodulation Distortion (30.5 MHz and 31.0 MHz; fS = 170 MSPS)
90
SECOND
-20
80
-40
(dB)
THIRD SFDR
(dB)
70
-60
SFDR = 78.8dBc
60
-80
50
-100
04530-A-006
40 0 50 100 150 200 (MHz) 250 300 350 400
-120 0 10 20 30 40 50 (MHz) 60 70 80 90 100
Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency @ 200 MSPS
61 59 57 SNR_200 55 SINAD_170 65 SNR_170 80
Figure 19. Two-Tone Intermodulation Distortion (69.3 MHz and 70.3 MHz; fS = 200 MSPS)
SFDR_170 75 70 SFDR_200 SINAD_170
(dB)
(dB)
53 51 49 47
04530-A-007
60 55 50 45 40 0 50 100 (MSPS) 150 200 250
04530-A-008
SINAD_200
SINAD_200
45 0 50 100 150 200 250 (MHz) 300 350 400 450
Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS, AIN @ -0.5 dBFS Full Scale = 1.536 V
Figure 20. SINAD and SFDR vs. Clock Rate (AIN = 10.3 MHz @ -0.5 dBFS) 170/200 grade
Rev. A | Page 14 of 28
04530-A-004
04530-0-019
40
-120
AD9411
450 90 ANALOG SUPPLY CURRENT 80 70 60 50 OUTPUT SUPPLY CURRENT 40 30 20 10 0 240
80
IAVDD ANALOG SUPPLY CURRENT (mA)
400 350 300 250 200 150 100 50 0 100
IDRVDD OUTPUT SUPPLY CURRENT (mA)
75 SFDR 70
(dB)
65 SNR 60 SINAD 55
04530-2-023
120
140
160
180
200
220
50 20
ENCODE (MSPS)
30 40 50 60 70 SAMPLE CLOCK POSITIVE DUTY CYCLE
80
Figure 21. IAVDD and IDRVDD vs. Clock Rate, 170 MSPS Grade, CLOAD = 5 pF (AIN = 10.3 MHz @ -0.5 dBFS)
450 90
Figure 24. SINAD and SFDR vs. Clock Pulse Width High (AIN = 10.3 MHz @ -0.5 dBFS, 200 MSPS)
1.4
IDRVDD OUTPUT SUPPLY CURRENT (mA)
IAVDD ANALOG SUPPLY CURRENT (mA)
400 350 300 250 200 OUTPUT SUPPLY CURRENT 150 100 50 0 100
80 70 60 50 40 30 20 10 0 240
1.2 RO = 13 TYP 1.0
ANALOG SUPPLY CURRENT
VREF (V)
0.8
0.6 0.4
0.2
04530-A-009
0 0 1 2 3 4 ILOAD (mA) 5 6 7 8
120
140
160 180 200 SAMPLE RATE (MSPS)
220
Figure 22. IAVDD and IDRVDD vs. Clock Rate, 200 MSPS Grade, CLOAD = 5 pF (AIN = 10.3 MHz @ -0.5 dBFS)
75 73 71 69
70 80
Figure 25. VREFOUT vs. ILOAD (Both Speed Grades)
SFDR
75
SFDR
67 dB
(dB)
65 63 61 59 57
04530-0-025
65
SNR
60 SINAD
SINAD
55
55 20
30
40
50
60
70
80
90
50 0.5
0.7
0.9 VREF (V)
1.1
1.3
1.5
ENCODE POSITIVE DUTY CYCLE (%)
Figure 23. SINAD and SFDR vs. Clock Pulse Width High (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS)
Figure 26. Sinad, SFDR vs. VREF in External Reference Mode (AIN = 70 MHz @ -0.5 dBFS, 200 MSPS)
Rev. A | Page 15 of 28
04530-A-011
04530-A-016
04530-A-010
AD9411
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5
04530-0-028
90 85 80 75
dB
% GAIN ERROR USING EXT REF
GAIN ERROR (%)
SFDR 70 65 SNR 60 SINAD 55
04530-0-030 04530-0-033 04530-0-032
-2.0 -50
-30
-10
10
30
50
70
90
50 -50
-30
-10
10
30
50
70
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 27. Full-Scale Gain Error vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170/200 MSPS)
60 AVDD = 3.6V
1.00 0.75
Figure 30. SNR, SINAD, and SFDR vs. Temperature (AIN = 10.3 MHz @ -0.5 dBFS, 170 MSPS)
59
0.50
AVDD = 3.3V 58
(dB)
LSB
04530-A-012
AVDD = 3.15V
0.25 0
57 AVDD = 3.0V 56
-0.25 -0.50 -0.75
55 -40
-20
0
20 40 TEMPERATURE (C)
60
80
-1.00 0 100 200 300 400 500 CODE 600 700 800 900 1000
Figure 28. SINAD vs. Temperature and AVDD (AIN = 10.3 MHz @ -0.5 dBFS, 200 MSPS)
1.250
1.0 0.8
Figure 31. Typical INL Plot (AIN = 10.3 MHz @ -0.5 dBFS, 170/200 MSPS)
1.245
0.6 0.4
VREFOUT (V)
1.240
0.2
LSB
1.235 1.230
04530-0-029
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 100 200 300 400 500 CODE 600 700 800 900 1000
1.225 2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
AVDD (V)
Figure 29. VREF Output Voltage vs. AVDD (Both Speed Grades)
Figure 32. Typical DNL Plot (AIN = 10.3 MHz @ -0.5 dBFS) 170/200 MSPS
Rev. A | Page 16 of 28
AD9411
110 100 90 80 70 -40 -20 SFDR -dBFS 0 NPR = 51 dB CLK = 200MSPS NOTCH AT 18.5MHz
dB
60 50 40 30 20 10
04530-0-034
80dB REFERENCE LINE SFDR -dBc
dB
-60
-80
-100
0 -90
-120 0 5 10 15 20 MHz 25 30 35 40
-80
-70
-60
-50
-40
-30
-20
-10
0
ANALOG INPUT LEVEL (dBFS)
Figure 33. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS
90 80 70 60 SFDR -dBFS 50 SFDR -dBc 4.0 4.5
Figure 36. Noise Power Ratio Plot (200 MSPS Grade)
ns
dB
3.5 TPD
40 30 70dB REFERENCE LINE 20 10
04530-0-036 04530-0-037
3.0 TCPD
04530-A-013
0 -70
-60
-50 -40 -30 -20 ANALOG INPUT LEVEL (dBFS)
-10
0
2.5 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 34. SFDR vs. AIN Input Level 70 MHz, AIN @ 200 MSPS
0 NPR = 51.2dB ENCODE = 170MSPS NOTCH @ 18.15MHz
Figure 37. Propagation Delay vs. Temperature (Both Speed Grades)
900 800 VOS 700 600
1.4 1.3 1.2 1.1 1.0 0.9 VOD 0.8 0.7 0.6 0.5 0 2 4 6 8 10 12 14 RSET (k)
-20 -40
NOISE LEVEL (dB)
-60
VDIF (mV)
500 400 300 200
-80 -100
-120 -140 0 10 20 MHz 30 40
04530-0-035
100 0
Figure 35. Noise Power Ratio Plot (170 MSPS Grade)
Figure 38. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS (Both Speed Grades)
Rev. A | Page 17 of 28
VOS (V)
04530-A-005
AD9411 APPLICATION NOTES
The AD9411 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 10-bit core. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output's logic levels are LVDS (ANSI-644) compatible. Table 7. Output Select Coding1
S1 (Data Format
Select)
CLOCK INPUT
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For this reason, considerable care has been taken in the design of the clock inputs of the AD9411, and the user is advised to give careful thought to the clock source. The AD9411 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLK+ and optimizes timing internally. This allows a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz nominally. The time constant associated with the loop should be considered in applications where the clock rate changes dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase before valid data is available. This circuit is always on and cannot be disabled by the user. The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs, as illustrated in Figure 39. Note that for this low voltage PECL device, the ac coupling is optional.
0.1F PECL GATE CLK- 0.1F
04530-A-017
1 0 X X
1
S5 (Full-Scale Select)2 X X 1 0
Mode Twos Complement Offset Binary Full Scale = 0.768 V Full Scale = 1.536 V
X = Don't Care.
2
S5 full-scale adjust (refer to the Analog Input section).
ANALOG INPUT
The analog input to the AD9411 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN- should match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal. A wideband transformer, such as Mini-Circuits' ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 2.8 V (refer to the Equivalent Circuits section). Note that the input common-mode can be overdriven by approximately +/-150 mV around the self-bias point, as shown in Figure 42. Special care was taken in the design of the analog input section of the AD9411 to prevent damage and corruption of data when the input is overdriven. The nominal differential input range is approximately 1.5 V p-p ~ (768 mV x 2). Note that the best performance is achieved with S5 = 0 (full-scale = 1.5). See Figure 40 and Figure 41.
AD9411
CLK+
S5 = GND
510
510
VIN+
Figure 39. Driving Clock Inputs with LVEL16
768mV 2.8V
2.8V
VIN- DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s
04530-0-041
Figure 40. Differential Analog Input Range
Rev. A | Page 18 of 28
AD9411
S5 = AVDD
VIN+
providing a low skew clocking solution (see Figure 2). The onchip clock buffers should not drive more than 5 pF of capacitance to limit switching transient effects on performance. The output clocks are LVDS signals requiring 100 differential termination at receiver.
2.8V
768mV 2.8V VIN- = 2.8V
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the AD9411 (VREF). The analog input full-scale range is linearly proportional to the voltage at VREF. Note that an external reference can be used by connecting the SENSE pin to VDD (disabling internal reference) and driving VREF with the external reference source. No appreciable degradation in performance occurs when VREF is adjusted 5%. A 0.1 F capacitor to ground is recommended at the VREF pin in internal and external reference applications. Float the SENSE pin for internal reference operation.
Figure 41. Single-Ended Analog Input Range
61
SINAD
60
59
04530-0-042
K
FULL SCALE S5 = 0 S5 = 1 K = 1.24 K = 0.62 VREF A1
dB
58
0.1F
57
1V 200
EXTERNAL 1.23V REFERENCE
56 2.0
2.2
2.4 2.6 2.8 3.0 ANALOG INPUT COMMON MODE (V)
3.2
04530-A-014
1k DISABLE A1
SENSE 3.3V
04530-0-043
Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage, (Ain = -.5 dBfs Differential Drive, S5 = 0)
VDD
LVDS OUTPUTS
The off-chip drivers provide LVDS compatible output levels. A 3.74 k RSET resistor placed at Pin 7 (LVDSBIAS) to ground sets the LVDS output current. The RSET resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 x IRSET). A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a 100 termination resistor as close to the receiver as possible. It is recommended to keep the trace lengths < 4 inches and to keep differential output trace lengths as equal as possible.
Figure 43. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return path of cable systems where the signals are typically QAM signals with a "noise-like" frequency spectrum. NPR performance of the AD9411 was characterized in the lab yielding an effective NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB backoff. The rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an FFT. This test requires sufficiently long record lengths to guarantee a large number of samples inside the notch. A highorder band-stop filter that provides the required notch depth for testing is also needed.
CLOCK OUTPUTS (DCO+, DCO-)
The input clock is buffered on-chip and available off-chip at DCO+ and DCO-. These clocks can facilitate latching off-chip,
Rev. A | Page 19 of 28
AD9411
3.3V + +
3.3V +
3.3V
SIGNAL GENERATOR REFIN
AVDD GND DRVDD GND BAND-PASS FILTER ANALOG J4
VDL GND
AD9411 EVALUATION BOARD
10MHz REFOUT SIGNAL GENERATOR CLOCK J5
DATA CAPTURE AND PROCESSING
04530-0-044
Figure 44. Evaluation Board Connections
Rev. A | Page 20 of 28
AD9411 EVALUATION BOARD
The AD9411 evaluation board offers an easy way to test the AD9411 in LVDS mode. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, latches, and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P23. The board has several different modes of operation and is shipped in the following configurations: * * * Offset binary Internal voltage reference Full-scale adjust = low
GAIN
Full scale is set at E17-E19, E17-E18 sets S5 low, full scale = 1.5 V differential; E17-E19 sets S5 high, full scale = 0.75 V differential. Best performance is obtained at 1.5 V full scale.
CLOCK
The clock input is terminated to ground through 50 resistor at SMB connector J5. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for optimum performance. J5 input should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper E47. E47-E45 powers the buffer from AVDD; E47-E46 powers the buffer from VCLK/V_XTAL.
POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). Table 8. Power Connector, LVDS Mode
AVDD1 3.3 V DRVDD1 3.3 V VDL1 3.3 V VCLK/V_XTAL EXT_VREF2
1 2
VOLTAGE REFERENCE
The AD9411 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when Jumpers E24-E27 and E25-E26 are left open. The full scale can be increased by placing an optional resistor (R3). The required value varies with the process and needs to be tuned for the specific application. Full scale can similarly be reduced by placing R4; tuning is required here as well. An external reference can be used by shorting the SENSE pin to 3.3 V (place Jumper E26-E25). Jumper E27-E24 connects the ADC VREF pin to the EXT_VREF pin at the power connector.
Analog Supply for ADC (350 mA) Output Supply for ADC (50 mA) Supply for Support Logic Supply for Clock Buffer/Optional XTAL Optional External Reference Input
AVDD, DRVDD, and VDL are the minimum required power connections. LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper.
ANALOG INPUTS
The evaluation board accepts a 1.3 V p-p analog input signal centered at ground at SMB connector J4. This signal is terminated to ground through 50 by R16. The input can be alternatively terminated at the T1 transformer secondary by R13 and R14. T1 is a wideband RF transformer that provides a single-ended-to-differential conversion, allowing the ADC to be driven differentially, which minimizes even-order harmonics. An optional second transformer, T2, can be placed following T1 if desired. This provides some performance advantage (~1 dB to 2 dB) for high analog input frequencies (>100 MHz). If T2 is placed, cut the two shorting traces at the pads. The analog signal can be low-pass filtered by R41, C12 and R42, C13 at the ADC input. The footprint for transformer T2 can be modified to accept a wideband differential amplifier (AD8351) for low frequency applications where gain is required. See the PCB schematic for more information.
DATA FORMAT SELECT
Data format select (DFS) sets the output data format of the ADC. Setting DFS (E1-E2) low sets the output format to be offset binary; setting DFS high (E1-E3) sets the output to twos complement.
DATA OUTPUTS
The ADC LVDS digital outputs are routed directly to the connector at the card edge. Resistor pads placed at the output connector allow for termination if the connector receiving logic lack the differential termination for the data bits and DCO. Each output trace pair should be terminated differentially at the far end of the line with a single 100 ohm resistor.
CLOCK XTAL
An optional XTAL oscillator can be placed on the board to serve as a clock source for the PCB. Power to the XTAL is through the VCLK/VXTAL pin at the power connector. If an oscillator is used, ensure proper termination for best results. The board was tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84.
Rev. A | Page 21 of 28
AD9411
Table 9. Evaluation Board Bill of Material--AD9411 PCB
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 26 27 28 29 1 1 1 1 T1, T2* U2 U9 U1 U3 RF Transformer RF Amp Optional XTAL AD9411 MC100LVEL16 Quantity 33 4 4 1 2 2 2 2 1 16 1 3 2 2 2 2 2 2 6 5 2 1 2 2 Reference Designator C1, C3*, C4-C11, C15-C17, C18*, C19-C32, C35, C36, C39*, C40*, C58-C62 C33*, C34*, C37*, C38* C63-C66 C2* C12*, C13* J4, J5 P21, P22 P21, P22 P23 R1, R6-R12*, R15*, R31-R37* R2 R5, R16, R27 R17, R18 R19, R20 R29, R30 R41, R42 R3, R4 R13, R14 R22*, R23*, R24*, R25*, R26*, R28* R38*, R39*, R40*, R45*, R47* R43*, R44* R46* R48*, R49* R50*, R51* Device Capacitor Capacitor Capacitor Capacitor Capacitor Jacks Power Connectors--Top Power Connectors--Posts 40-Pin Right Angle Connector Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Package 0603 0402 TAJD 0603 0603 SMB 25.602.5453.0 Wieland Z5.531.3425.0 Wieland Digi-Key S2131-20-ND 0402 0603 0603 0603 0603 0603 0603 0603 0603 0603 0402 0402 0402 0402 0402 Mini Circuits ADT1-1WT AD8351 JN00158 or VF561 TQFP-100 SO8NB 100 3.7 k 50 510 150 1 k 25 3.8 k 25 100 25 10 k 1.2 k 0 1 k CAPL Value 0.1 F 0.1 F 10 F 10 pF 20 pF
* C2, C3, C12, C13, C18, C33, C34, C37, C38, C39, C40, R1, R6-R12, R15, R22-R26, R28, R31-R40, R43-R51 and T2 not placed.
Rev. A | Page 22 of 28
R1 100
DORB
D11 R6 100 D11B
D10 D10B
D9 D9B
H4
MTHOLE6 MTHOLE6
DOR
GROUND PAD UNDER PART GND
P16
P1
GND
H2
MTHOLE6
1
GND
R7 100
P3
VDL
GND
MTHOLE6
3
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
DRVDD
GND
P2
H3
2
VREF
R8 100
P21
PTM1CRO4
P4
GND H1
4
P1
1
D9- 80
D8- 78
D9+ 81
D8+ 79
AVDD 99
AVDD 98
AVDD 95 AVDD 94
AVDD 90
AVDD 89
AGND 100
AGND 97
AGND 96
AGND 93
AGND 92
AGND 91
AVDD 88
AGND 87
DVRDD 83
P22
PTM1CRO4
P4
1
4
VCC
S5 DRVDD 75 DRGND 74 D6+ 73 D6- 72 D5+ 71 D5- 70 D4+ 69 D4- 68 DRGND 67 D3+ 66 D3- 65 DC0+ 64 DC0- 63 DNC S4 AGND S2 S1 LVDSBIAS AVDD AGND SENSE VREF AGND AGND AVDD AVDD AGND AGND AVDD AVDD GND AIN AINB AGND AVDD AGND
VCC E17 GND E19
E18
2 3 4 5 6
AGND 86
DRGND 82
P3
3
GND
OR+ 85
OR- 84
D7+ 77
D7- 76
P2
2
DRVDD
DRVDD GND
R29 GND 1k
R30 1k
D8
R12 100
D8B
VCC
E1
E2
7
VCC E3
GND
GND
D7 R11 100 D7B
GND
R2 3.8k
8 9 10 11
VCC
VCC E25 E26
E27 VREF E24
GND
R3 GND 3.8k
R4 3.8k
D6 R10 100 D6B
GND
12 13 14 15 16 17 18 19 20 21 22
D5 R9 100 D5B
DRVDD 62 DRGND 61 D2+ 60 D2- 59 D1+ 58 D1- 57 D0+ 56 D0- 55 DRVDD 54 DRGND 53 DNC 52 DNC 51
GND
C1 0.1F
U1 AD9411
VCC
DRVDD
GND
DR R37 100 DRB
VCC
26 AGND
27 AVDD
28 AVDD
29 AVDD
30 AGND
31 AGND
32 AGND
33 AVDD
34 AVDD
35 AGND
36 CLK+
37 CLK-
38 AGND
39 AVDD
40 AVDD
41 AGND
42 DNC
43 DNC
44 DNC
45 DNC
46 DNC
47 DRVDD
48 DRGND
49 DNC
C6 0.1F
R13 25
50 DNC
VCC
VCC
VCC
VCC
VCC
~ENC
DRVDD
C30 0.1F
GND
GND
GND
GND
GND
GND
GND
VCC
Figure 45. Evaluation Board Schematic
GND
GND
D4
Rev. A | Page 23 of 28
GND
R33 100
D4B
VCC
VCC
C12 20pF
GND
GND
D3 R32 100 D3B
40 P40
38 P38
36 P36
34 P34
32 P32
30 P30
28 P28
26 P26
24 P24
T2 OPTIONAL AMPINB R41 C15 25 0.1F
P39 39
T1
T2
GND
23 24 25
P37 37
ADT1-1WT
ADT1-1WT
VCC
GND ANALOG R16 J4 50
4 2
1 5 NC 3
PRI SEC
4 GND 2 6 C7 0.1F
1 5 NC 3
GND R14 25
PRI SEC
6 C11 0.1F
C3 0.1F C2 10pF
GND
C13 20pF
GND
D2 R31 100 GND DRVDD DRB GND D2B GND D1 D11B R15 100 D10B D1B D9B
GND
AMPIN
AMP
R42 GND 25
D0
E46
E47
E45
10EL16
22 P22
VCC
VDL
R36 100
D0B
R5 50
20 P20
18 P18
D8B D7B D6B D5B D4B D3B
D1F
GND
C36 0.1F
GND DR P35 35 GND P33 33 D11 P31 31 D10 P29 29 D9 P27 27 D8 P25 25 D7 P23 23 D6 P21 21 D5 P19 19 D4 P17 17 D3
GND
16 P16
P15 15
J5
2 3 4
C5 0.1F U3
8
R35 100
7 6
14 P14
P13 13
ENCODE
ELOUT ELOUTB
C10 0.1F
C9 0.1F
D1FB
D2F
C4 0.1F
12 P12
P11 11
R34 100
D2FB
C8 0.1F
10 P10
8 P8
6 P6
P9 9 P7 7 P5 5
GND
R27 50
R17 510
R18 510
VCC D Q DN QN VBB VEE 5
GND
R20 510
GND
R19 510
GND
GND
D2B D1B D0B D1FB D2FB DORB
CONNECTOR
D2 D1 D0 D1F D2F DOR
4 P4
P3 3
GND 2 P2
P1 1
GND
AD9411
04530-A-015
AD9411
VCC + C64 10F C16 0.1F C17 0.1F C19 0.1F C21 0.1F C20 0.1F C23 0.1F C22 0.1F C25 0.1F C24 0.1F C27 0.1F C26 0.1F C29 0.1F C28 0.1F C31 0.1F C32 0.1F C35 0.1F
GND
DRVDD
+ C65 10F
VDL C61 0.1F C62 0.1F C60 0.1F C59 0.1F C58 0.1F GND
+ C66 10F
VREF C18 0.1F GND
+ C63 10F
GND TO USE VF561 CRYSTAL GND VDL R28 100
1 2
JN00158 E/D NC GND U9 GND VDL R24 100 P5 R26 100 VCC OUTPUTB OUTPUT
6 5 4
VDL
R23 100 P4 R25 100
R22 100
GND
3
GND
Figure 46. Evaluation Board Schematic (continued)
R51 1k VDL
R50 1k GND VDL
POWER DOWN USE R43 OR R44 VDL GND GND
C38 0.1F
C37 0.1F GND
GND
R43 10k
R44 10k
1
U2 AD8351 PWUP VOCM 10 VPOS 9 OPHI 8 OPLO
7
R47 25k
R38 25k
C33 0.1F
R39 25k
RGP1 INHI 3 INLO
2 4 5
R49 0
C39 0.1F AMPINB
AMP IN AMP
C34 0.1F
R40 25k R45 25k
RPG2
COMM 6
GND
R48 0
C40 0.1F AMPIN
04530-0-053
R46 1.2k
Figure 47. Evaluation Board Schematic (continued)
Rev. A | Page 24 of 28
04530-0-046
AD9411
Figure 48. PCB Top Side Silkscreen
Figure 50. PCB Ground Layer
04530-0-048
Figure 49. PCB Top Side Copper Routing
Figure 51. PCB Split Power Plane
Rev. A | Page 25 of 28
04530-0-050
04530-0-049
AD9411
Figure 52. PCB Bottom Side Copper Routing
04530-0-051
Figure 53. PCB Bottom Side Silkscreen
Rev. A | Page 26 of 28
04530-0-052
AD9411 OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE
1.20 MAX
100 1
16.00 SQ 14.00 SQ
76 75 76 75 100 1
TOP VIEW
(PINS DOWN)
CONDUCTIVE HEAT SINK 25 26 51 50 51 50 26 25
0.20 0.09 7 3.5 0
1.05 1.00 0.95
6.50 NOM
0.50 BSC
0.27 0.22 0.17
0.15 0.05
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 54. 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP] (SV-100) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9411BSV-170 AD9411BSV-200 AD9411/PCB Temperature Range -40C to +85C -40C to +85C Package Description TQFP/EP TQFP/EP EVALUATION BOARD Package Option SV-100 SV-100
Rev. A | Page 27 of 28
AD9411 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04530-0-7/04(A)
Rev. A | Page 28 of 28

▲Up To Search▲

Price & Availability of AD9411

	To Download AD9411 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .