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PRELIMINARY TECHNICAL DATA
a
16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port AD7709
GENERAL DESCRIPTION
Preliminary Technical Data
FEATURES 16-BIT SINGLE CHANNEL SIGMA DELTA-ADC Factory Calibrated (field calibration not required) Output settles in one conversion cycle (single conver sion mode) Programmable Gain Front End 16-bit No Missing Codes 13-bit Pk-Pk Resolution @ 20Hz, 20mV Range 16-bit Pk-PK Resolution @ 20Hz, 2.56V Range INTERFACE Three-Wire Serial SPITM, QSPITM, MICROWIRETM and DSP Compatible Schmitt Trigger on SCLK POWER Specified for Single 3V and 5V operation Normal : 2mA @ 3V Powerdown : 20uA (32kHz Crystal Running) On-Chip Functions Rail-to-Rail Input Buffer and PGA Switchable Reference Inputs 3 Configurable Current Sources Low Side Power Swtches Digital I/O Port APPLICATIONS Industrial Process Control Instrumentation Pressure Transducers Portable Instrumentation
IOUT 1
The AD7709 is a complete analog front-end for low frequency measurement applications. The AD7709 contains a 16-bit sigma delta ADC with PGA and can be configured as 2 fully-differential input channels or 4 pseudo-differential input channels. Inputs signal ranges from 20mV to 2.56V can be directly converted using the AD7709. These signals can be converted directly from a transducer without the need for signal conditioning. Other on-chip features include three software configurable current sources, switchable reference inputs, low side power switches and a 4-bit digital I/O port. The device operates from a 32kHz crystal with an onboard PLL generating the required internal operating frequency. The output data rate from the part is software programmable. The pk-pk resolution from the part varies with the programmed gain and output data rate. The part operates from a single +3V or +5V supply. When operating from +3V supplies, the power dissipation for the part is XmW. The AD7709 are housed in a 24pin SOIC and TSSOP packages.
FUNCTIONAL BLOCK DIAGRAM
VDD REFIN2(+) REFIN1(+) REFIN2(-) REFIN1(-) XTAL1 XTAL2
I1
I2
I3
OSC. & PLL
IOUT 2 DOUT AIN1 AIN2 AIN3 / P3 AIN4 / P4 AINCOM MUX BUF PGA
16-BIT - ADC
SERIAL INTERFACE & CONTROL LOGIC
DIN SCLK CS RDY RESET
AD7709
VDD I/O PORT
GND
PWRGND
SW1/P1 SW2/P2
(R) SPIand QSPI are a Registered Trademark of Motorola Inc. (R) MICROWIRE is a Registered Trademark of National Semiconductor Corp. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 otherwise under any patent or patent rights of Analog Devices.
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AD7709-SPECIFICATIONS1
PARAMETER Output Update Rate
PRELIMINARY TECHNICAL DATA
(VDD = +3V or +5.0V , REFIN(+) = +2.5V; REFIN(-) = 0V; XTAL1/XTAL2 = 32 kHz Crystal; All specifications TMIN to TMAX unless otherwise noted.)
Units Hz min. Hz max. bits min. bits pk-pk bits pk-pk Test Conditions B Grade 5.4 105 16 13 16
0.021Hz (0.732msec.) increments
No Missing Codes Resolution
+20mV range, 20Hz Update Rate +2.56V range, 20Hz Update Rate
Output Noise and Update Rates Integral Nonlinearity Offset Error Offset Error Drift Vs Temp Offset Error Drift Vs Time Gain Error Gain Error Drift Vs Temp Gain Error Drift Vs Time Power Supply Rejection(PSR) Common Mode Rejection(CMR) On AIN On AIN On REFIN On REFIN Analog Input Current DC Bias Current DC Bias Current Drift DC Offset Current DC Offset Current Drift
See Tables Below in ADC Description 15 ppm of FSR max. TBD 10 nV/C typ. TBD nV/1000 Hours typ. TBD 1 ppm/Ctyp. TBD ppm/1000 Hours typ. 90 dB min. Input Range = 20mV 90 dB min. Input Range = 2.56V 90 90 90 90 1 TBD TBD TBD dB dB dB dB nA nA nA nA min. min. min. min. max. typ. typ. typ. At At At At DC, DC, DC, DC, Range Range Range Range = = = = 20mV 2.56V 20mV 2.56V
REFERENCE INPUTS (REFIN1& REFIN2) Normal Mode 50Hz/60Hz Rejection 60 Reference DC Input Current TBD REFIN(+) to REFIN(-) Voltage +2.5V REFIN(+) to REFIN(-) Range +1 VDD REFIN Common Mode Range GND-30mV VDD+30mV REFIN Common Mode 50/60Hz Rejection TBD ANALOG INPUTS Normal Mode 50Hz/60Hz Rejection Common Mode 50/60Hz Rejection Differential Input Voltage Ranges REFIN/GAIN
dB min. A typ. nom. REFIN referes to both REFIN1 and REFIN2 V min. V max. V min. V max. dB min.
60 90 90
dB min. dB min. dB min. V nom.
50/60Hz 1Hz , 20Hz Update Rate 50/60Hz 1Hz, Range = 20mV 50/60Hz 1Hz, Range = 2.5V REFIN refers to both REFIN1 and REFIN2. REFIN=REFIN(+ )-REFIN(-) GAIN=1to 128.
Pseudo-Differential Input Voltage Ranges 0V to REFIN/GAIN V nom. Full-scale Range Matching 5 uV typ. Absolute Ain Voltage Limits Buffered Inputs GND+50mV V min. VDD-50mV V max Unbuffered Inputs GND-30mV Vmin V DD+30mV Vmax
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PRELIMINARY TECHNICAL DATA AD7709
PARAMETER LOGIC INPUTS All Inputs Except SCLK and XTAL1 VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) VT(+) VT(-) VT(+)- VT(-) VT(+) VT(-) VT(+)-VT(-) XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage Input Currents Input Capacitance LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage Floating State Leakage Current Floating State Output Capacitance Data Output Coding EXCITATION CURRENT SOURCES I1 and I2 Output Current I3 Output Current Initial Tolerance at 25C Drift Initial Current Matching at 25C Drift Matching Line Regulation (VDD) Load Regulation Output Compliance Low-Side Power Switches (SW1 and SW2) Ron Allowable Current SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span START From From From UP TIME Power-On Idle Mode Power-Down Mode B Grade Units Test Conditions
0.8 0.4 2.0 1.4/3 0.8/1.4 0.4/0.85 0.95/2.5 0.4/1.1 0.4/0.85 0.8 3.5 0.4 2.5 10 10 VDD- 0.6 0.4 4 0.4 10 10 Binary Offset Binary 200 25 10 20 1 1 TBD TBD AVDD-0.5 5 7 20 1.05 X FS -1.05 X FS 0.8 X FS 2.1 X FS 500 1 1 500
V max. V max. V min. V V V V V V min/V min/V min/V min/V min/V min/V max max max max max max
VDD = 5V VDD = 3V VDD = 3V or 5V VDD VDD VDD VDD VDD VDD = = = = = = 5V 5V 5V 3V 3V 3V
V max. V min. V max. V min. A max. pF typ. V min. V max. V min. V max. uA max. pF typ.
VDD = 5V VDD = 5V VDD = 3V VDD = 3V VIN = 0V or VDD All Digital Inputs VDD VDD VDD VDD = = = = 3V, 3V, 5V, 5V, ISOURCE ISINK = ISOURCE ISINK = = 100A 100A = 200A 1.6mA
Unipolar Mode Bipolar Mode A nom. A nom. % typ. ppm/C typ. % ppm/C typ. nA/V max. nA/V max. V max. typ typ mA max V V V V max. min. min. max.
Matching between I1 and I2 VDD = 5V10%
VDD = 5V VDD = 3V Per Switch
msec typ. msec. typ. msec. typ. msec. typ.
Osc. powered down
POWER REQUIREMENTS Power Supply Voltages VDD - GND
2.7/3.6 4.5/5.5 -3-
V min/max V min/max
VDD = 3V nom. VDD = 5V nom.
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PRELIMINARY TECHNICAL DATA AD7709
PARAMETER Power Supply Currents VDD Current (Normal Mode) VDD Current (Normal Mode) VDD Current (Idle Mode) VDD Current (Idle Mode) VDD Current (Power-Down Mode) VDD Current (Power-Down Mode)
NOTES 1 Temperature Range -40 C to +85C
2 3 4
B Grade TBD TBD TBD TBD 20 30
Units mA mA mA mA A max. A max.
Test Conditions VDD =3V VDD =5V VDD =3V VDD =5V VDD =3V, 32.768kHz Osc. Running VDD =5V, 32.768kHz Osc. Running
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PRELIMINARY TECHNICAL DATA AD7709
ABSOLUTE MAXIMUM RATINGS
(TA = +25C unless otherwise noted)
1
V DD to GND.............................................-0.3V to +7V Analog Input Voltage to GND...........-0.3V to VDD +0.3V Reference Input Voltage to GND.......-0.3V to VDD +0.3V AIN/REFIN Current (Indefinite)...........................30mA Digital Input Voltage to GND...........-0.3V to VDD +0.3V Digital Output Voltage to GND........-0.3V to VDD +0.3V PWRGND to GND...............................-0.3V to +0.3V Operating Temperature Range..................-40C to 85C Storage Temperature Range....................-65C to 150C Junction Temperature........................................+150C PACKAGE Power Dissipation........................TBD mW JA Thermal Impedance..................................90C/W Lead Temperature, Soldering Vapor Phase (60sec)..................................+215C Infrared (15 sec).......................................+220C
1
OUTLINE DIMENSIONS 24-lead plastic SOIC (R-24)
0.614 1 (15.60 ) 0.598 5 (15.20 )
24 13
1
12
PIN 1
0.104 3 (2.65) 0.092 6 (2.35)
0.419 3 (10.65 )
0.393 7 (10.00 )
0.299 2 (7.60)
0.291 4 (7.40)
0.029 1 (0.74) 0.009 8 (0.25)
x 45
0.011 8 (0.30) 0.004 0 (0.10)
0.050 0 (1.2 7) BSC
8 0 SEA TIN G 0.012 5 (0.32) 0.013 8 (0.35) PLAN E 0.009 1 (0.23) 0.019 2 (0.49)
0.050 0 (1.27) 0.015 7 (0.40)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
24-lead plastic TSSOP (RU-24)
24-lead plastic TSSOP (RU-24)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model AD7709BR AD7709BRU
Temperature Range -40C to +85C -40C to +85C
Package Description SOIC TSSOP
Package Drawing Option R-24 RU-24
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PRELIMINARY TECHNICAL DATA AD7709 TIMING CHARACTERISTICS1, 2 (V
Parameter t1 t2 Read Operation t3 t4 t54 t5A4, 5 t6 t7 t8 t96 t10 Write Operation t11 t12 t13 t14 t15 t16
DD = +3V 10% or VDD = +5V 10%;GND = 0 V:XTAL = 32.768kHz; Input Logic 0 = 0 V, Logic 1 = VDD
unless otherwise noted)
Limit at TMIN, TMAX (B Version) 32.768 50 0 0 0 60 80 0 60 80 100 100 0 10 80 100 0 30 25 100 100 0 Units kHz typ ns min ns min ns min ns ns ns ns ns ns ns ns ns min max max min max max min min min Conditions/Comments Crystal Oscillator Frequency. RESET Pulse Width RDY to CS Setup Time CS Falling Edge to SCLK Active Edge Setup Time 3 SCLK Active Edge to Data Valid Delay3 VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V CS Falling Edge to Data Valid Delay3 VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V SCLK High Pulse Width SCLK Low Pulse Width CS Rising Edge to SCLK Inactive Edge Hold Time 3 Bus Relinquish Time after SCLK Inactive Edge3 SCLK Active Edge to RDY High3,
7
ns min ns max ns max ns min ns ns ns ns ns min min min min min
CS Falling Edge to SCLK Active Edge Setup Time 3 Data Valid to SCLK Edge Setup Time Data Valid to SCLK Edge Hold Time SCLK High Pulse Width SCLK Low Pulse Width CS Rising Edge to SCLK Edge Hold Time
NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figures 1 and 2. 3 SCLK active edge is falling edge of SCLK. 4 These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to thenextoutputupdate.
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PRELIMINARY TECHNICAL DATA AD7709
CS
t 11
S CL K
t 14
t 16
t 12 t 13
D IN
t 15
MSB
LSB
Figure 1. Write Cycle Timing Diagram
RDY
t3
CS
t 10
t4
S CLK
t6
t8
t5 t 5A
DO UT
t7
t6 t9
M SB
LSB
Figure 2. Read Cycle Timing Diagram
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PRELIMINARY TECHNICAL DATA AD7709
PIN CONFIGURATION
IO UT 1 IO UT 2
1 2 24 23
X TAL1 X TAL2 VD D G ND DIN DO UT DRDY CS S CL K RE S E T P 1/S W 1 P W RGN D
R E F IN 1(+ ) 3 R E F IN 1(-) 4 AIN1 5 AIN 2 6 AIN3/P 3 7 AIN4/P 4 8 AINCO M
9
A D 7709
22 21 20
TO P V IE W (No t to S cale) 19
18 17 16 15 14 13
R E F IN 2(+ ) 10 R E F IN 2(-) 11 P 2/S W 2 12
Pin Function Description Pin No
1
Mnemonic
IOUT1
Function
Output for internal excitation current sources. A single current source or any combination of the internal current sources I1,I2 and I3 can be switched to this output. Output for internal excitation current sources. A single current source or any combination of the internal current sources I1,I2 and I3 can be switched to this output. Positive reference input. REFIN(+) can lie anywhere between VDD and GND. The nominal reference voltage (REFIN(+)-REFIN(-)) is 2.5V but the part is functional with a reference range from 1V to VDD. Negative reference input. This reference input can lie anywhere between GND and VDD-1V. Analog Input Channel 1. Programmable-gain analog input which can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully-differential input pair when used with AIN2. (see Communications Register section) Analog Input Channel 2. Programmable-gain analog input which can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully-differential input pair when used with AIN1. (see Communications Register section) Analog Input Channel 3 or Digital Port Bit. Programmable-gain analog input which can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully-differential input pair when used with AIN4. The second function of this bit is as a general purpose digital input bit. Analog Input Channel 4 or digital port bit. Programmable-gain analog input which can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3. The second function of this bit is as a general purpose digital input bit. All analog inputs are referenced to this input when configured in pseudo-differential input mode. Positive reference input. REFIN2(+) can lie anywhere between VDD and GND. The nominal reference voltage (REFIN2(+)-REFIN2(-)) is 2.5V but the part is functional with a reference range from 1V to VDD. -8- REV. PrA January 2001
2
IOUT2
3
REFIN1(+)
4 5
REFIN1(-) AIN1
6
AIN2
7
AIN3/P3
8
AIN4/P4
9 10
AINCOM REFIN2(+)
PRELIMINARY TECHNICAL DATA AD7709
11 12 13 14 15 16 REFIN2(-) P2/SW2 PWRGND P1/SW1 RESET SCLK Negative reference input. This reference input can lie anywhere between GND and VDD-1V. P2 can act as a general purpose Input/Output bit referenced between VDD and GND or as a low-side power switch to PWRGND.. Ground point for the low-side power switches SW2 and SW1. PWRGND must be tied to GND. P1 can act as a general purpose Output bit referenced between VDD and GND or as a low-side power switch to PWRGND. Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-up internally to DVDD. Serial clock input for data transfers to and from the ADC. The SCLK has a schmitt triggered input making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be noncontinuous clock with the information being transmitted to or from the AD7709 in smaller batches of data. Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the AD7709 in systems with more than one device on the serial bus or as a frame synchronisation signal in communicating with the device. CS can be hardwired low allowing the AD7709 to be operated in three-wire mode with SCLK, DIN and DOUT used to interface with the device. RDY is a logic low status output from the AD7709. RDY is low if the ADC has valid data in its data register. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update indicating to the user that a read operation should not be initiated. Serial data output with serial data being read from the output shift register of the ADC. The output shift register can contain data from any of the on-chip data, calibration or control registers. Serial Data Input with serial data being written to the input shift register on the AD7709. Data in this shift register is transferred to the control registers within the ADC depending on the selection bits of the Communications register. Ground Reference point for the AD7709. Supply voltage, 3V or 5V nominal. Output from the 32kHz crystal oscillator inverter. Input to the 32kHz crystal oscillator inverter.
17
CS
18
RDY
19
DOUT
20
DIN
21 22 23 24
GND VDD XTAL2 XTAL1
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PRELIMINARY TECHNICAL DATA AD7709
ADC CIRCUIT INFORMATION
Overview The AD7709 incorporates an analog multiplexer with a Sigma-Delta ADC, on-chip programmable gain amplifier and digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure transducer or temperature measurement applications. The AD7709 offers 16-bit resolution. The AD7709 can be configured as 2 fully differential input channels or as 4 pseudo differential input channels referenced to AINCOM. The channel is buffered and can be programmed for one of 8 input ranges from +20mV to +2.56V. Buffering the input channel means that the part can handle significant source impedances on the analog input and that R, C filtering (for noise rejection or RFI reduction) can be placed on the analog inputs if required. These input channels are intended to convert signals directly from sensors without the need for external signal conditioning. Other functions contained on-chip that augment the operation of the ADC include software configurable current sources, switchable reference inputs and low side power switches. The ADC employs a sigma-delta conversion technique to realize up to 16-bits of no missing codes performance. The sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable low pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35Hz (186.77mS) to 105.03Hz (9.52mS). A Chopping scheme is also employed to minimize ADC channel offset errors. A block diagram of the ADC input channel is shown in Figure 3 below.
f chop
Analog Input Mux Buffer PGA
fin
f mod
f chop
f adc
S-D MOD0 XOR
(
1 8 x SF
)
3
3 x (8 x SF)
3
1 -- 2
Digital Output
Sinc
Filter A
in
+ V os
A in - V os
Figure 3. AD7709 ADC Channel Block Diagram
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PRELIMINARY TECHNICAL DATA AD7709
ADC NOISE PERFORMANCE
Tables I and II below show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5LSB) for some typical output update rates . The numbers are typical and generated at a differential input voltage of 0V. The output update rate is selected via the SF7-SF0 bits in the Filter Register. It is important to note that the peakto-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit.The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independant of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source.The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak to peak resolution is now based on half the signal range which effectively means loosing 1 bit of resolution. Table I. Typical Output RMS Noise vs. Input Range and Update Rate for AD7709 Output RMS Noise in V SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 Input Range 160mV 320mV 640mV 1.24V 1.75 0.65 0.37 3.50 0.65 0.37 4.50 0.95 0.51 6.70 1.40 0.82
20mV 1.50 0.60 0.35
40mV 1.50 0.65 0.35
80mV 1.60 0.65 0.37
2.56V 11.75 2.30 1.25
Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7709 Peak-to-Peak Resolution in Bits SF Word 13 69 255 Data Update Rate (Hz) 105.3 19.79 5.35 20mV 12 13 14 40mV 13 14 15 80mV 14 15 16 Input Range 160mV 320mV 640mV 1.24V 15 16 16 15 16 16 15.5 16 16 16 16 16 2.56V 16 16 16
AD7709 ON-CHIP REGISTERS
Both the AD7709 is controlled and configured via 4 on-chip registers as shown in figure 4 and described in more detail in the following section. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state unless otherwise stated.
DIN DIN
C om m u nic atio n s R eg i ster W E N R /W STB Y O SC P D 0 0 A1 A0
DOUT
DOUT
Statu s Register DIN REG ISTE R SEL EC T DEC ODER
DOUT DIN DOUT
C onfiguration Register(24-Bits)
Filter Register
DOUT
ADC Data Register
Figure 4. AD7709 On-Chip Registers
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PRELIMINARY TECHNICAL DATA AD7709
Communications Register- ( A1, A0= 0,0): The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table III outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. CR7 WEN ( 0 ) CR6 R/W(0) CR5 STBY(0) CR4 OSCPD (0) CR3 0 (0) CR2 0(0) CR1 A1(0) CR0 A(0)
Table III. Communications Register Bit Designations Bit Bit Location Mnemonic Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register. A zero in this bit location indicates that the next operation will be a write to a specified register. A one in this position indicates that the next operation will be a read from the designated register. Standby bit indication. Set when its required to put the AD7709 in low power mode. Clear to power up the AD7709. Oscillator Power Down Bit. If this bit is set, then placing the AD7709 in standby mode will stop the crystal oscillator reducing the power drawn by these parts to a minimum. The oscillator will require 500ms to begin oscillating when the ADC is taken out of standby mode. If this bit is cleared the oscillator is not shut off when the ADC is put into standby mode and will not require the 500ms start-up time when the ADC is taken out of standby. This bit must be programmed with a logic 0 for correct operation. This bit must be programmed with a logic 0 for correct operation. Register Address Bits. These address bits are used to address the AD7709's registers and are outlined in table IV.
CR6
R/W
CR5
STBY
CR4
OSCPD
CR3 CR2 CR1-CR0
0 0 A1-A0
Table IV. AD7709 Register Selection Table A1 0 0 0 1 1 A0 0 0 1 0 1 Register Communications register during a write operation. Status Register register during a read operation. Configuration Register Filter register ADC Data Register
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PRELIMINARY TECHNICAL DATA AD7709
Status Register - (A1,A0=0,0; Power-On-Reset = 00Hex): The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communications Register selecting the next operation to be a read and load bits A1-A0 with 0,0. Table V outlines the bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
SR7 RDY(0)
SR6 0(0)
SR5 0(0)
SR4 0(0)
SR3 ERR (0)
SR2 0(0)
SR1 STBY(0)
SR0 LOCK(0)
Table V. Status Register Bit Designations Bit Bit Location Mnemonic Description SR7 RDY Ready bit for the ADC Set when data is transferred to the ADC data register. The RDY bit is cleared automatically a period of time before the data register is updated with a new conversion result or after the ADC data register has been read. Bit is automatically cleared. Reserved for future use This bit is automatically cleared. Reserved for future use This bit is automatically cleared. Reserved for future use ADC Error Bit. This qualifying bit is set at the same at the RDY bit. When Set it indicates that the result written to the ADC data register has been clamped to all zeros or all ones. Error sources include Overrange and loss of lock. This bit is Cleared at the same time as the RDY bit. This bit is automatically cleared. Reserved for future use Standby bit indication. When Set it indicates that the AD7709 is in low power mode. Cleared when the ADC is powerd up. PLL lock status bit. This bit is SET if the PLL has locked onto the 32kHz crystal oscillator clock. The ADC will not start conversion till this bit has been set. If the LOCK bit subsequently goes low the ERR bit will be set.
SR6 SR5 SR4 SR3
0 0 0 ERR
SR2 SR1
0 STBY
SR0
LOCK
Configuration Register(CONFIG) :(A1,A0 = 0,1; Power-On-Reset = 000000Hex) The CONFIG Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to select the input channel and configure the input range, excitation current sources and I/O port.Table XIII outlines the bit designations for this register. CONFIG24 through CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register. CONFIG24 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. A write to the CONFIG register has immediate effect and does not reset the the ADCs. Thus , if a current source is switched while the ADC is converting the user will have to wait for the fullsettling time of the sinc^3 filter before getting a fully settled output. This equates to 4 outputs.
REV. PrA
January 2001
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PRELIMINARY TECHNICAL DATA AD7709
CONFIG23 PSW1(0) CONFIG15 P4DIG(0) CONFIG7 CONFIG22 CONFIG21 CONFIG20 PSW2(0) I3EN1 (0) I3EN1(0) CONFIG19 CONFIG18 I2EN1(0) I2EN0(0) CONFIG17 I1EN1(0) CONFIG9 P2DAT(0) CONFIG1 RN1(0) CONFIG16 I1EN0(0) CONFIG8 P1DAT(0) CONFIG0 RN0(0)
CONFIG14 CONFIG13 CONFIG12 P3DIG(0) CONFIG6 P2EN(0) CONFIG5 CH1(0) P1EN(0) CONFIG4 CH0(0)
CONFIG11 CONFIG10 P4DAT(0) CONFIG3 UNI(0) P3DAT(0) CONFIG2 RN2(0)
REFSEL(0) CH2(0)
Table VI. Configuration Register Bit Designations Bit Location CONFIG23 Bit Mnemonic PSW1 Description Power Switch 1 Control bit. Set by user to enable Power switch P1 to PWRGND. Cleared by user to enable use as a standard I/O pin. When ADC is in standby mode the power switches are open. Power Switch 2 Control bit. Set by user to enable Power switch P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When ADC is in standby mode the power switches are open. Current Source Enable Bits. Used in conjunction with bit I3EN0 to determine the function of current source I3 Current Source Enable Bits. Used in conjunction of current source I3 I3EN1 I3EN0 Function 0 0 Current Source OFF 0 1 Current Source Routed 1 0 Current Source Routed 1 1 Current Source Routed with bit I3EN1 to determine the function
CONFIG22
PSW2
CONFIG21 CONFIG20
I3EN1 I3EN0
to IOUT1 pin. to IOUT2 pin. to GND
CONFIG19 CONFIG18
I2EN1 I2EN0
Current Source Enable Bits. Used in conjunction with bit I2EN0 to determine the function of current source I2 Current Source Enable Bits. Used in conjunction of current source I2 I2EN1 I2EN0 Function 0 0 Current Source OFF 0 1 Current Source Routed 1 0 Current Source Routed 1 1 Current Source Routed with bit I2EN1 to determine the function
to IOUT1 pin. to IOUT2 pin. to GND
CONFIG17 CONFIG16
I1EN1 I1EN0
Current Source Enable Bits. Used in conjunction with bit I1EN0 to determine the function of current source I3 Current Source Enable Bits. Used in conjunction of current source I3 I1EN1 I1EN0 Function 0 0 Current Source OFF 0 1 Current Source Routed 1 0 Current Source Routed 1 1 Current Source Routed with bit I1EN1 to determine the function
to IOUT1 pin. to IOUT2 pin. to GND
CONFIG15
P4DIG
Digital Input Enable Set by user to enable P4 as a digital input Cleared by user to configure as pin P4/AIN4 as analog input.
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REV. PrA
January 2001
PRELIMINARY TECHNICAL DATA AD7709
CONFIG14 P3DIG Digital Input Enable Set by user to enable P3 as a digital input Cleared by user to configure as pin P3/AIN3 as analog input. The default configuration is analog input. P2 digital output enable bit. Set by user to enable P2 as a regular digital output pin. Cleared by user to tristate P2 output. PSW2 takes presedance over P2EN. P1 digital output enable bit. Set by user to enable P1 as a regular digital output pin. Cleared by user to tristate P1 output. PSW1 takes presedance over P1EN. Digital input port data bit. P4DAT is read only and will return a 0 if P4DIG=0. If P4 is enabled as a digital input then the read back value indicates the status of pin P4. Digital input port data bit. P3DAT is read only and will return a 0 if P3DIG=0. If P3 is enabled as a digital input then the read back value indicates the status of pin P3. Digital output port data bit. P2 is digital output only. When the port is active as an output (P2EN=1), then the value written to the this data bit appears at the output port. Reading P2DAT will return what was last written to the P2DAT bit on the AD7709. Digital output port data bit. P1 is digital output only. When the port is active as an output (P1EN=1), then the value written to the this data bit appears at the output port. Reading P1DAT will return what was last written to the P1DAT bit on the AD7709. ADC reference input select. Cleared by user to select REFIN1(+) and REFIN1(-) as the ADC reference. Set by user to select REFIN2(+) and REFIN2(-) as the ADC reference. ADC Input Channel Selection bit. Used in conjunction with CH1 and CH0 as shown in the analog input selection table. ADC Input Channel Selection bit. Used in conjunction with CH2 and CH0 as shown in the analog input selection table. ADC Input Channel Selection bit. Used in conjunction with CH2 and CH2 as shown in the analog input selection table. CH1 0 0 1 1 0 0 1 CH0 0 1 0 1 0 1 0 Positive Input AIN1 AIN2 AIN3 AIN4 AIN1 AIN3 AINCOM Negative Input AINCOM AINCOM AINCOM AINCOM AIN2 AIN4 AINCOM Buffer Positive Positive Positive Positive Positive Positive Positive
CONFIG13
P2EN
CONFIG12
P1EN
CONFIG11 CONFIG10 CONFIG9
P4DAT P3DAT P2DAT
CONFIG8
P1DAT
CONFIG7
REFSEL
CONFIG6 CONFIG5 CONFIG4
CH2 CH1 CH0
CH2 0 0 0 0 1 1 1
Analog Input Analog Input Analog Input Analog Input and Negative Analog Inputs and Negative Analog Inputs and Negative Analog Inputs
The final column indicates if the analog inputs are buffered or unbuffered. This determines the common mode input range on each input. If the input is unbuffered (AINCOM) the common mode input includes GND. CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit. Set by user to enable unipolar operation with straight binary output coding i.e. zero differential input will result in 0000hex output and a fullscale differential input will result in FFFF Hex output. Cleared by user to enable pseudo bipolar operation and offset binary coding, negative fullscale differential input will result in an output code of 0000 Hex, zero differential input will result in an output code of 8000Hex and a positive fullscale differential input will result in an output code of FFFF Hex.
REV. PrA
January 2001
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PRELIMINARY TECHNICAL DATA AD7709
CONFIG2 CONFIG1 CONFIG0 RN2 RN1 RN0 RN2 0 0 0 0 1 1 1 1 Used in conjunction with RN1 and RN0 to select the analog input range. Used in conjunction with RN2 and RN0 to select the analog input range. Used in conjunction with RN2 and RN1 to select the analog input range. RN1 0 0 1 1 0 0 1 1 RN0 0 1 0 1 0 1 0 1 Selected Main ADC Input Range (Vref=2.5V) 20mV 40mV 80mV 160mV 320mV 640mV 1.28V 2.56V
Filter Register:(A1,A0=1,0; Power-On-Reset = 00Hex) The Filter Register is an 8-bit register from which data can either be read or to which data can be written. This register determines the amount of averaging performed by the sinc filter. Table VII outlines the bit designations for the Filter Register. FR7 through FR0 indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and thus the output update rate for the ADCs. The filter register cannot be written to by the user while the ADC is active. The update rate is used for the ADC is calculated as follows :
fadc
Where : fadc = fmod = SF = FR6 SF6(1)
=1 X 3
1 X 8.SF
fmod
ADC Output Update Rate Modulator Clock Frequency= 32.768KHz (Main and Aux ADC) Decimal Value written to SF Register FR5 SF5(0) FR4 SF4(0) FR3 SF3(0) FR2 SF2(1) FR1 SF1(0) FR0 SF0(1)
FR7 SF7(0)
Table VII. Filter Register Bit Designations The allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (fadc) and time (tadc) are shown in table XII below. It should also be noted that both ADC input channels are chopped to minimise offset errors. This means that the time for a single conversion or the time to the first conversion result is 2 X tadc.
SF(dec) 13 69 255
SF(hex) 0D 45 FF
fadc (Hz) 105.3 19.79 5.35
tadc (ms) 9.52 50.34 186.77
Table XII. Update Rate Vs SF Word.
ADC Data Result Register (DATA):(A1,A0=1,1; Power-On-Reset = 000000Hex) The conversion result for the selected ADC channel is stored in the ADC data register (DATA). This register is 16-bits wide. This is a read only register. On completion of a read from this register the RDY bit in the status register is cleared.
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REV. PrA
January 2001
PRELIMINARY TECHNICAL DATA AD7709
CONFIGURING THE AD7709
On the AD7709 there are only four user accessable registers and these are configured via the serial interface. Communication with any of these registers is initiated by firstly writing to the Communications Register. The AD7709 starts converting after a power up without the requiring any register to be written to. The defaults conditions are used and the AD7709 operates at a 20Hz update rate offering 50 and 60Hz rejection. Figure 5 outlines a flow diagram of the sequence used to configure the registers on the AD7709 following a power-up. The flowchart shows two methods of determining when its valid to read the data register. The first method is hardware polling of the RDY pin and the second method involves software interrogation of bits in the status and mode registers. The flowchart details all the necessary programming steps required to initialize the ADC and read data from the selected ADC channel following a power-on or reset.The steps can be broken down as follows: 1. Configure and initialize the microcontroller or microprocessor serial port. 2. Initialize the AD7709 by configuring the following registers: a)FILTER registers which determines the update rate. The AD7709 must be put into standby mode before writing to the filter register. b) CONFIGURATION register to select the input channel to be converted, its input range and reference. This register is also used to configure the internal current sources, power switches and I/O port. Both of these operations consist of a write to the communications register to specify the next operation as a write to a specified register. Data is then written to this register. When each sequence is complete the ADC defaults to waiting for another write to the communications register to specify the next operation. 3) When configuration is complete the user needs to determine when its valid to read the data from the data register. This is accomplished by either polling the RDY pin (hardware polling) or by interrogating the bits in the STATUS register (software polling). Both are shown in the following flowchart.
START
HARDWARE POLLING
SOFTWARE POLLING
POWER-ON/RESET FOR AD7709
CONFIGURE & INITIALIZE
C/ P SERIAL PORT
POLL RDY PIN
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE STATUS REGISTER WRITE 40HEX TO COMMS REGISTER
WRITE TO COMMUNICATIONS REGISTER SELECTING NEXT OPERATION TO BE A WRITE TO THE FILTER REGISTER (WRITE 22HEX TO COMMS REG)
NO
RDY LOW?
READ STATUS REGISTER
WRITE TO FILTER REGISTER TO CONFIGURE THE REQUIRED UPDATE RATE.
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF THE DATA REGISTER (WRITE 43HEX TO COMMS REGISTER)
NO
RDY=1
YES
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE CONFIGURATION REGISTER (WRITE 01Hex TO COMMS REG)
READ16-BIT DATA RESULT
WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ OF THE DATA REGISTER. WRITE 43HEX TO COMMS REGISTER
WRITE TO CONFIGURATION REGISTER TO SELECT INPUT CHANNEL, INPUT RANGE AND REFERENCE. CURRENT SOURCES AND I/O PORT CAN ALSO BE CONFIGURED
ANOTHER READ?
YES
READ16-BIT DATA RESULT
NO
READ DATA FROM OUTPUT REGISTER
YES CHANNEL CHANGE
ANOTHER READ?
YES
NO
HARDWARE POLLING
SOFTWARE POLLING
NO
YES
CHANNEL CHANGE
NO
END
END
Figure 5. Flowchart for Configuring and reading from AD7709
REV. PrA January 2001 -17-

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