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ISL23711
Volatile Digitally Controlled Potentiometer (XDCPTM)
Data Sheet August 16, 2005 FN6127.0
Terminal Voltage 3V or 5V, 128 Taps I2C Serial Interface
The Intersil ISL23711 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, and a control section. The wiper position is controlled by an I2C interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. The wiper terminal can be connected to either end of the resistor array or at any one of the Tap Positions in between, providing 128 steps of resolution between RL and RH. The "position" of the wiper is determined by the value assigned to the volatile Wiper Register (WR). The WR can be directly written to and read from using standard I2C interface protocol. The device is available in either a 10k or 50k version. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: * Industrial and Automotive Control * Parameter and Bias Adjustments * Amplifier Bias and Control
Features
* I2C Serial Interface with Hardwire Slave Address Allows up to Four Devices * DCP Terminal Voltage, from V- to VCC * 127 Resistive Elements - Typical RTOTAL tempco 50ppm/C - Typical ratiometric tempco 4ppm/C - End to end resistance range 20% - Wiper resistance = 70 typ at VCC = 3.3V * Low Power CMOS - Standby current, 500nA max - Active current, 200A max - VCC = 2.7V to 5.5V - V- = -2.7V to -5.5V * RTOTAL Values = 10k, 50k * Volatile Wiper Storage * Package - 10 Ld MSOP * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
TEMP RANGE (C) -40 to +85 -40 to +85 ISL23711 (10 LD MSOP) TOP VIEW PACKAGE 10 Ld MSOP (Pb-Free) 10 Ld MSOP (Pb-Free) PKG. DWG. # M10.118 M10.118
Ordering Information
PART NUMBER (BRAND) ISL23711WIU10Z (AOE) (Notes 1, 2) ISL23711UIU10Z (AOD) (Notes 1, 2) NOTES: 1. Add "-T" suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. RESISTANCE OPTION () 10K 50K
SDA VGND A1 A0
1 2 3 4 5
10 9 8 7 6
SCL VCC RL RW RH
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL23711 Block Diagram
SDA VCC GND SCL 7-BIT WIPER REGISTER (VOLATILE) 127 126 SDA SCL INTERFACE AND CONTROL RW ONE OF 128 DECODER 2 VSIMPLE BLOCK DIAGRAM A1 A0 RECALL CONTROL CIRCUITRY SLAVE ADDRESS DECODE DETAILED BLOCK DIAGRAM 1 0 RL RW RH 125 124 RH
A1 A0
TRANSFER GATES
RESISTOR ARRAY
RL
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL SDA VGND A1 A0 RH RW RL VCC SCL drain active low outputs. Negative supply voltage for the potentiometer wiper control. Ground. Should be connected to a digital ground A1 and A0 are address select pins used to set the slave address for the I2C serial interface. A1 and A0 are address select pins used to set the slave address for the I2C serial interface. A fixed terminal for one end of the potentiometer resistor. The wiper terminal which is equivalent to the movable terminal of a potentiometer. A fixed terminal for one end of the potentiometer resistor. Positive logic supply voltage. Clock input for the I2C serial interface. DESCRIPTION Data I/O for I2C serial interface. It has an open drain output and may be wire ORed with other open
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Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SDA, SCL, A0, and A1 with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3 to VCC+0.3V Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC ESD Rating (MIL-STD-883, Method 3015.7 . . . . . . . . . . . . . . .>2kV
Thermal Information
Thermal Resistance (Typical, Note 3) MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA (C/W) 170
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (Note 1) 10 50 -20 VV- = -5.5V; VCC = +5.5V Wiper current = (VCC - V-)/RTOTAL 70 10/10/25 Voltage at pins; V- to VCC -1 0.1 1 +20 VCC 200 MAX UNIT k k % V pF A
PARAMETER RH to RL Resistance
RH to RL Resistance Tolerance VRH,VRL RW CH/CL/CW ILkgDCP RH, RL Terminal Voltage Wiper Resistance Potentiometer Capacitance (Note 13) Leakage on RH, RL, RW pins
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded) INL (Note 6) DNL (Note 5) ZSerror (Note 3) FSerror (Note 4) TCV (Notes 7, 13) Integral Non-linearity Differential Non-linearity Zero-scale Error W, U options W option U option Full-scale Error W option U option Ratiometric Temperature Coefficient DCP register set from 16 to 120d, T = -40C to +85C -1 -0.5 0 0 -4 -2 1 0.5 -1 -0.5 4 1 0.5 4 2 0 0 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) RDNL (Note 10) Roffset (Note 9) Integral Non-linearity Differential Non-linearity Offset DCP register set to 00 hex, W option DCP register set to 00 hex, U option TCR Resistance Temperature Coefficient (Notes 12, 13) DCP register set from 16 to 127d, T = -40C to +85C DCP register set between 20 hex and 7F hex. Monotonic over all tap positions -1 -0.5 0 0 2 0.5 50 1 0.5 5 2 MI (Note 8) MI (Note 8) MI (Note 8) MI (Note 8) ppm/C
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Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 IVISB PARAMETER VCC Supply Current, Volatile Write/Read TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Write states only) -100 MIN TYP (Note 1) MAX 200 -1 500 300 -500 -300 -10 1 2.5 -1 10 UNIT A A nA nA nA nA A s V
V- Supply Current, Volatile Write/Read fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Write states only) VCC Current (Standby) VCC = +5.5V, I2C Interface in Standby State VCC = +3.6V, I2C Interface in Standby State V- = -5.5V, I2C Interface in Standby State V- = -2.7V, I2C Interface in Standby State
IV-SB
V- Current (Standby)
ILkgDig tDCP (Note 13) Vpor
Leakage Current, at Pins SDA, SCL, A0, and A1 DCP Wiper Response Time Power-on Recall for VCC
Voltage at pin from GND to VCC SCL falling edge of last bit of DCP Data Byte to wiper change
SERIAL INTERFACE SPECS VIL VIH Hysteresis VOL Cpin (Note 14) fSCL tIN tAA tBUF A0, A1, SDA, and SCL Input Buffer LOW Voltage A0, A1, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA A0, A1, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is and SCL Inputs suppressed SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Input Data Hold Time STOP Condition Setup Time STOP Condition Setup Time SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge. Both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge. Both crossing 70% of VCC 1300 -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 50 900 0.3*VCC VCC+ 0.3 V V V V pF kHz ns ns ns
tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHD:STO
1300 600 600 600 100 0 600 600
ns ns ns ns ns ns ns ns
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tDH tR (Note 14) tF (Note 14) Cb (Note 14) Rpu (Note 14) tSU:A tHD:A PARAMETER Output Data Hold Time SDA, SCL, A0, A1 Rise Time SDA, SCL, A0, A1 Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip A0, A1 Setup Time A0, A1 Hold Time TEST CONDITIONS From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2~2.5k For Cb = 40pF, max is about 15~20k Before START condition After STOP condition MIN 0 20 + 0.1 * Cb 20 + 0.1 * Cb 10 1 250 250 400 TYP (Note 1) MAX UNIT ns ns ns pF k
600 600
ns ns
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0, A1 Pin Timing
START STOP
SCL
Clk 1
SDA IN tSU:A A0, A1
tHD:A
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NOTES: 1. Typical values are for TA = 25C and 5V supply voltage. 2. LSB: [V(RW)127 - V(RW)0] / 127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = (V(RW)0 - V-) / LSB. 4. FS error = [V(RW)127 - VCC] / LSB. 5. DNL = [V(RW)i - V(RW)i-1] / LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i - (i * LSB - V(RW)0) for i = 1 to 127. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 7. TC V = --------------------------------------------------------------------------------------------- x ---------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C for i = 16 to 120 decimal, Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 - R0| / 127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 9. Roffset = R0 / MI, when measuring between RW and RL. Roffset = R127 / MI, when measuring between RW and RH. 10. RDNL = (Ri - Ri-1) / MI, for i = 16 to 127. 11. RINL = [Ri - (MI * i) - R0] / MI, for i = 16 to 127. [ Max ( Ri ) - Min ( Ri ) ] 10 12. TC R = --------------------------------------------------------------- x ---------------[ Max ( Ri ) + Min ( Ri ) ] 2 125C for i = 16 to 127, Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. 14. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
6
Test Circuit
TEST POINT
RW Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. BUS INTERFACE PINS
FORCE CURRENT
RW
Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for the I2C interface. It receives device address, operation code, wiper register address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL.
RL
Equivalent Circuit
RTOTAL RH CH CW CL
SDA requires an external pull-up resistor, since it's an open drain output. Serial Clock (SCL) This input is the serial clock of the I2C serial interface.
RW
Device Address (A1-A0) The Address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the ISL23711. A maximum of 4 ISL23711 devices may occupy the I2C serial bus.
Pin Descriptions
Potentiometer Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL23711 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the I2C serial input and not the voltage potential on the terminal.
Principles of Operation
The ISL23711 is an integrated circuit incorporating one DCP with It's associated register, and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised
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ISL23711
of 127 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. indicating START and STOP conditions (See Figure 1). On power-up of the ISL23711 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL23711 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 1). All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 1). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 2). The ISL23711 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23711 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs, and the following two bits matching the logic values present at pins A1, and A0. The LSB is in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation. (See Table 1.)
TABLE 1. IDENTIFICATION BYTE FORMAT Logic values at pins A1, and A0 respectively 0 (MSB) 1 0 1 0 A1 A0 R/W (LSB)
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal is controlled by a 7-bit volatile Wiper Register (WR). When the WR contains all zeroes (00h), the wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR contains all ones (7Fh), the wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0 decimal) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL23711 is being powered up, the WR is reset to 20h (64 decimal), which locates the RW at the center between RL and RH. The WR can be read or written directly using the I2C serial interface as described in the following sections.
Memory Description
* A read operation to address 0 outputs the value of the volatile WR. * A write operation to address 0 only writes to the volatile WR.
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23711 responds with an ACK.
I2C Serial Interface
The ISL23711 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23711 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Read Operation
A Read operation is initiated by a master using the following sequence: a START, the Identification byte (slave address) with the R/W bit set to "1". At the moment of the first acknowledge by the ISL23711 (slave device), the mastertransmitter becomes a master receiver and receives the data byte from the slave-transmitter.The Master receives the data byte and issues a non-acknowledge (SDA is HIGH), then a STOP to terminate the read operation. Since the ISL 23711 has just one WR, it will transmit only one byte (see Figure 4).
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for 7
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ISL23711
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL23711
0 1 0 1 0 A1 A0 0 A C K
0000 0 000 A C K A C K
FIGURE 3. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A IDENTIFICATION R BYTE WITH T R/W=1
S T O P
SIGNAL AT SDA
0 1 0 1 0 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
DATA BYTE READ BY MASTER
FIGURE 4. READ SEQUENCE
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ISL23711 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
4X L L1
e E L
0.020 BSC 0.187 0.016 0.199 0.028
0.50 BSC 4.75 0.40 5.05 0.70
A
A2
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 10 0.003 0.003 5o 0o 15o 6o
0.95 REF 10 0.07 0.07 5o 0o
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6127.0 August 16, 2005

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