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ES4228/ES4227 Internet Set-Top Box Solution Product Brief
DESCRIPTION
The ES4228 MPEG video/audio decoder works as the central processing unit for Internet set-top box applications, while the ES4227 companion chip integrates all of the necessary discrete components for Internet set-top boxes. The high level of flexibility and versatility provided by the ES4228/ES4227 chipset makes it the most cost-effective, high-performance solution for the Internet set-top box market. The ES4228 includes a programmable internal RISC processor core that makes it adaptable for use in embedded systems applications such as set-top boxes. The ES4227 companion chip supplies proper video sync capabilities and performs NTSC- and PAL-based video encoding and decoding as necessary to provide broadcast quality video to the television screen. The ES4227 is a mixed-signal chip that includes a high quality NTSC/PAL encoder, two programmable 16-bit sigma-delta audio DACs, a PLL clock synthesizer, two microphone A/D converters, an I/O expansion port, and an echo/surround sound circuit. The ES4228 controls the ES4227 through a proprietary bus, the Device Serial Communication (DSC) bus. The ES4227 gets video input and audio input from the ES4228. Video format is 8bit YUV, and audio format is I2S. Command and register accesses are issued through the DSC interface from the ES4228 to the ES4227 through the DSC interface for accessing the internal registers of the ES4227. The DSC interface port is comprised of three interface signals, the strobe (DSC_S), data (DSC_D), and clock (DSC_C). The DSC port is selected when the DSC strobe goes high and latches the data at the rising edge of the clock. Each 16-bit DSC transfer is comprised of an address followed by data. The digital video encoder of the ES4227 uses three 9-bit video DACs to generate composite and S-video analog signals. One video DAC handles the composite video output, while the other two handle the S-video outputs. Color space conversions are provided to match the input data to the required output format, then the data is filtered to meet the selected video standards. The programmable audio DACs of the ES4227 offer differential audio outputs. These outputs ensure further noise reduction while providing a dual audio output with a signal-to-noise ratio better than 90 dB. The expansion I/O port is address-mapped to the ES4228. Four pins of the port can be configured as edgetriggered interrupts, supporting critical functions such as handling remote control and modem interrupt requests, DVD/ SVCD loader resets and modem board resets. The ES4228 is available in an industry-standard 208-pin Plastic Quad Flat Pack (PQFP) package, while the ES4227 is available in an industry-standard 100-pin PQFP package.
ES4228 FEATURES
* Single-chip MPEG-2 video/audio decoder and system
parser in 208-pin PQFP package.
* 640 x 480 NTSC and 640 x 576 PAL television video resolutions
supported.
* Software-configurable for Internet e-mail and web browser
functions.
* Karaoke, On-Screen Display (OSD), Playback Control (PBC)
for Video CD 2.0 and 3.0 and trick mode functions supported.
* VideoCD 1.1, 2.0, Interactive 3.0, Super VCD and Audio CD
compatible (SVCD and DVD configurations only).
* SmartScaleTM video scaling supports both X-axis and Y-axis * *
interpolationa and bidirectional NTSC to PAL and PAL to NTSC conversion. SmartZoom TMsupports 4X picture enlargement and reduction SmartStreamTM supports video bit stream error concealment.
ES4227 FEATURES
* Multi-standard TV encoder in 100-pin PQFP package supports
CCIR601 non-square operation, NTSC/PAL formats,
simultaneous composite and S-video output, and interlaced operation. Two programmable 16-bit sigma-delta audio DACs accept I2S format data, and provide dual audio output with SNR better than 90 dB. Dual microphone input and vocal assist hardware support provided. PLL clock synthesizer based on 27 MHz crystal input generates required clocks for video encoder, audio DAC, echo and surround sound, and video processor. Device Serial Communication (DSC) port for command issued/ register access. Digitally controlled echo with up to 130 ms delay.
* * * * *
SOFTWARE SUPPORT
* Software stack support for the POP3, SMTP and SNMP Internet
e-mail protocols defined by RFC 821, RFC 1157and RFC 2449.
* Software stack support provided for the HTTP Web browsing
protocol defined by RFC 1945, RFC 2068 and RFC 2616.
* Software stack support provided for the TCP/IP Internet
protocols defined by RFC 791 and RFC 793.
* Software stack support provided for RTP payload format for * *
MPEG-1/2 and H.261 video streaming protocols defined by RFC 2032, RFC 2038 and RFC 2250. Character generation and software support for English, Big 5/GB Chinese and Japanese fonts. Software support for infrared remote control and wireless keyboard.
ESS Technology, Inc.
SAM0378-053001
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ES4228/ES4227 PRODUCT BRIEF
ES4228 PINOUT
Figure 1 shows the ES4228 device pinout.
VCC NC VPP AUX0 AUX1 AUX2 VSS VCC AUX3 AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VCC VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VCC LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VCC NC NC LA0 LA1 LA2 LA3 VSS
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VSS NC NC NC NC NC NC NC VCC VSS NC NC NC NC NC HD15 HD14 VCC VSS HD13 HD12 HD11 HD10 HD9 HD8 HD7 VCC VSS HD6 HD5 HD4 HD3 HD2 HD1 HD0 VCC VSS HSYNC# VSYNC# PCLKQSCN PCLK2XSCN YUV7 YUV6 YUV5 VSS VCC YUV4 YUV3 YUV2 YUV1 YUV0 DCLK
ES4228 208-Pin PQFP Package
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
VCC VSS DSCK DQM DCS0# VCC VSS DCS1# DB15 DB14 DB13 DB12 VCC VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VCC DRAS2# DRAS1# DRAS0# DWE# DOE#/DSCK_EN DCAS# VCC VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VCC DMA5 DMA4 DMA3 DMA2 DMA1 DMA0
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SAM0378-053001
VCC LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VCC LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VCC TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL1 TSD/SEL_PLL0 VSS VCC SEL_PLL2 NC NC MCLK TBCK NC NC VSS VCC RSD RWS RBCK APLLCAP XIN XOUT VCC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 1 ES4228 Device Pinout
ESS Technology, Inc.
ES4228/ES4227 PRODUCT BRIEF
ES4228 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4228.
Table 1 ES4228 Pin Descriptions List Name
VCC LA[21:0]
Number
1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 23:19, 16:10, 7:2, 207:204 8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103, 112, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 24
I/O
I
Description
3.45 V power supply.
O I
Device address output.
VSS
Ground.
RESET# TDMDX
I O I
Reset input, active low. TDM transmit data. ROM Select.
RSEL
25
RSEL
0 1 I I I O O I O I
Selection
8-bit ROM 16-bit ROM
TDMDR TDMCLK TDMFS TDMTSC# TWS SEL_PLL1 TSD
28 29 30 31 32
TDM receive data. TDM clock input. TDM frame sync. TDM output enable, active low. Audio transmit frame sync. Refer to the description and matrix for SEL_PLL0 pin 33. Audio transmit serial data port. System and DSCK output clock frequency selection at reset time. The matrix below lists the available clock frequencies and their respecitve PLL bit settings.
SEL_PLL2
33 SEL_PLL0 0 0 0 0 1 1 1 1 I I/O I/O I I I I I O
SEL_PLL1 SEL_PLL0 Clock Output
0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VCO doesn't work. 27 MHz Bypass mode 54 MHz 121.5 MHz 81 MHz 94.5 MHz 108 MHz
SEL_PLL2 MCLK TBCK RSD RWS RBCK APLLCAP XIN XOUT
36 39 40 45 46 47 48 49 50
Refer to the description and matrix for SEL_PLL0 pin 33. Audio master clock for audio DAC. Audio transmit bit clock. Audio receive serial data. Audio receive frame sync. Audio receive bit clock. Analog PLL Capacitor. Crystal input. Crystal output.
ESS Technology, Inc.
SAM0378-053001
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ES4228/ES4227 PRODUCT BRIEF
Table 1 ES4228 Pin Descriptions List (Continued) Name
DMA[11:0] DCAS# DOE# DSCK_EN DWE# DRAS[2:0]# DB[15:0] DCS[1:0]# DQM DSCK DCLK YUV[7:0] PCLK2XSCN PCLKQSCN VSYNC# HSYNC# HD[15:0] VPP AUX[7:0] LOE# LCS[3:0]# LD[15:0] LWRLL# LWRHL# NC 71 74:72 96:93, 90:85 ,82:77 97, 100 101 102 105 115:113, 110:106 116 117 118 119 141:140, 137:131, 128:122 159 169:165, 162:160 170 176:173 197:194,191:185,182:178 198 199 37, 38, 41, 42, 146:142, 155:149, 158, 203:202
Number
66:61, 58:53 69 70
I/O
O O O O O O I/O O O O I O I/O I/O I/O I/O I/O I I/O O O I/O O O --
Description
DRAM address bus. DRAM column address strobe. DRAM output enable. DRAM system clock enable. DRAM write enable. DRAM row address strobe. DRAM data bus. SDRAM chip select [1:0]. Data input/output mask. DRAM system clock to SDRAM. Clock input (bypass/test mode). 8-bit YUV output. 2X pixel clock. Pixel clock. Vertical sync. Horizontal sync. Host data bus 5 V power supply. Auxiliary ports. EPROM device output enable. EPROM chip select [3:0]. EPROM device data bus. EPROM device low byte write enable. EPROM device high byte write enable. No connect.
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SAM0378-053001
ESS Technology, Inc.
ES4228/ES4227 PRODUCT BRIEF
ES4227 PINOUT
Figure 2 shows the ES4227 device pinout.
2XPCLK VREFM VCCAV VCCAV VSSAA VSSAV VSSAV VSSAV VSSAV
COMP
CDAC
VDAC
YDAC
XOUT
ACAP
RSET
DSC_D7 HSYNC# DSC_D6 VSYNC# DSC_D5 YUV7 YUV6 YUV5 YUV4 VCC VSS YUV3 DSC_D4 YUV2 DSC_D3 YUV1 DSC_D2 YUV0 DSC_D1 VSS
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VREF
PCLK
AUX3
AUX4
AUX5
AUX6
VCC
VCC
VCC
VSS
VSS
VSS
XIN
NC
50 49 48 47 46 45 44 43
MIC1 MIC2 AOL+ AOLAORAOR+ VCCAA VREFP VCM VSSAA AUX15/IR AUX14 AUX13 RBCK/SER_IN AUX12/C2PO AUX11/IRQ AUX10 RSD/SEL_PLL0 VCC VSS
ES4227
100-pin PQFP
42 41 40 39 38 37 36 35 34 33 32 31
100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TWS/SPLL_OUT
DSC_C
NC
RWS/SEL_PLL1
RESET#
RSTOUT#
VSS
VSS
DSC_S
DCLK/EXT_CLK
MCLK
DSC_D0
TBCK
AUX0
AUX1
AUX2
AUX7
AUX8
AUX9
VCC
VCC
VSS
TSD
NC
NC
NC
NC
NC
Figure 2 ES4227 Device Pinout
ESS Technology, Inc.
MUTE
SAM0378-053001
NC
5
ES4228/ES4227 PRODUCT BRIEF
ES4227 PIN DESCRIPTION
Table 2 lists the pin descriptions for the ES4227.
Table 2 ES4227 Pin Descriptions List
Name VSS VCC DSC_C AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 AUX8 AUX9 AUX10 AUX11 AUX12 AUX13 AUX14 AUX15 DSC_D[7:0] DSC_S DCLK EXT_CLK RESET# MUTE MCLK TWS SPLL_OUT TSD TBCK RWS 21 22 23 13 15 17 19 Number 1, 25:26, 31, 72, 75, 77, 91, 100 5, 16, 32, 66, 73, 78, 90 6 7 9 11 70 69 68 67 14 18 20 34 35 36 38 39 40 8, 81, 83, 85, 93, 95, 97, 99 10 12 I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I O I I O I I O I Definition Ground. 5.0V power supply. Clock for programming to access internal registers. General purpose I/O. General purpose I/O. General purpose I/O. CD loader reset. Modem DSP reset. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. General purpose I/O. Interrupt output to ES4228. CD loader C2PO. General purpose I/O. Interrupt input from Modem DSP. IR interrupt Input. Data for programming to access internal registers. Strobe for programming to access internal registers. Dual-purpose pin DCLK is the ES4228 clock. External clock input during bypass PLL mode. Reset. Audio mute. Audio master clock. Dual-purpose pin TWS is the transmit audio frame sync. SPLL_OUT is the select PLL output. Transmit audio data input. Transmit audio bit clock. Dual-purpose pin RWS is the receive audio frame sync. Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1
SEL_PLL1 0 0 1 1 24 2:4,27:30,76 O
SEL_PLL0 DCLK
0 1 0 1 Bypass PLL (input mode) 27 MHz (output mode) Default 32.4 MHz (output mode) 40.5 MHz (output mode)
RSTOUT# NC
Reset output (active-low). No connect. Do not connect to these pins.
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SAM0378-053001
ESS Technology, Inc.
ES4228/ES4227 PRODUCT BRIEF
Table 2 ES4227 Pin Descriptions List (Continued)
Name RSD 33 SEL_PLL0 RBCK SER_IN VSSAA VCM VREFP VCCAA AOR+, AORAOL-, AOL+ MIC2 MIC1 VREF VREFM RSET COMP VSSAV CDAC VCCAV YDAC VDAC ACAP XOUT XIN PCLK 2XPCLK HSYNC# VSYNC# YUV[7:0] 37 41,51 42 43 44 45, 46 47, 48 49 50 52 53 54 55 56:57, 62:63 58 59, 60 61 64 65 71 74 79 80 82 84 86:89, 92, 94, 96, 98 Number I/O O I O I Definition Dual-purpose pin. RSD is the receive audio data input. SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output. See the table for pin number 23. Dual-purpose pin. RBCK is the receive audio bit clock. SER_IN is the serial input DSC mode. 0 - Parallel DSC mode. 1 - Serial DSC mode. Audio Analog Ground. ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V. Bypass to analog ground with 47 F electrolytic in parallel with 0.1 F. DAC and ADC maximum reference. Bypass to VCMR with 10 F in parallel with 0.1 F. Analog VCC, 5 V. Right channel output. Left channel output. Microphone input 2. Microphone input 1. Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to analog ground with 0.1 F. DAC and ADC minimum reference. Bypass to VCMR with 10 F in parallel with 0.1 F. Full scale DAC current adjustment. Compensation pin. Video analog ground Modulated chrominance output. 5.0V video power supply. Y luminance data bus for screen video port. Composite video output. Audio CAP 27 MHz crystal output. 27 MHz crystal input. 13.5 MHz pixel clock. Doubled 27 MHz pixel clock. Horizontal sync. Vertical sync. YUV data bus for screen video port.
I I I I O O I I I I I I I O I O O I O I I/O I/O O O I
ESS Technology, Inc.
SAM0378-053001
7
ES4228/ES4227 PRODUCT BRIEF
SYSTEM BLOCK DIAGRAM
Figure 3 shows the ES4228/ES4227 chipset implemented in a sample system block diagram.
ROM or Flash ROM ES2898 Modem ES2828 MC'97 SDRAM DAA/Telephone Line Interface
CD Loader
ES4227 Companion Chip
Video
ES4228 MPEG Processor
Video Encoder Audio DACs PLL Interrupt Port
IR Input
Audio DSC
Front Panel / Keypad
I/O Expansion Echo/Surround Remote Control Mic Inputs
VCD/SVCD Option
Figure 3 ES4228/ES4227 System Block Diagram
ORDERING INFORMATION
Part Number ES4228 ES4227 Description MPEG Processor Video Encoder Companion Chip Package 208-pin PQFP 100-pin PQFP
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,384,169 and others, other patents pending.
MPEG is the Moving Picture Experts Group of the ISO/ IEC. References to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee draft ISO 11172 dated January 9, 1992. VideoDriveTM, SmartScaleTM, SmartZoomTM and SmartStreamTM are trademarks of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. H.261 refers to the International Standard described in recommendation H.261 of the CCITT Working Party 15-1. All other trademarks are trademarks of their respective companies and are used for identification purposes only. All other trademarks are owned by their respective holders and are used for identification purposes only.
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(c) 2000--2001 ESS Technology, Inc. All rights reserved.
SAM0378-053001

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