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preliminary
CY100 Companion IC with 5 V ADC
Eight channel 10 bit A / D converter with 5 V interface for 3.3 V or 2.5 V controllers for automotive, truck and 42 V applications
FEATURES
* * * * * * Eight channel 10 bit A / D converter Approved ISO interface , slew rate limitation, bidirectional serial interface driver according ISO 9141 Two small signal stages with diagnostics SPI interface All I / O - ports designed for 2.5 V to 3.6 V logic level Package : LQFP32
PIN DESCRIPTION
Pin Name
AREF GNDA VDD5A AN_IN0..7
RAM AD Converter
8 Channel
Reset
Function
Receiver output driver ISO 9141 Transmitter input driver ISO 9141 Input/output driver ISO 9141 UB-Reference for the ISO 9141 receiver Output small signal stage 1 Output small signal stage 2 Input small signal stage 1 Input small signal stage 2 Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 ( only half sample rate of the others channels ) Analog input 6 Analog input 7 CLK-input for the A-to-D Converter ( Necessary to enable the CY100 ) Interrupt-Output for the A-to-D Converter SPI slave-select signal Slave-Out signal ( SPI data output ) Slave-In signal ( SPI data input ) SPI serial clock input Analog reference voltage for the ADC Analog supply voltage 5 V Analog ground UBat Pin for ESD protection 5 V - digital supply 3.3 V / 2.5 V - supply for IO Digital-ground mainly for 'on chip' digital modules Digital-ground mainly for 'on chip' power modules like ISO, KSA and SPI Reset-input not used -> to be connected to ground
CLK
VDD5
INT
+ Logic
SI SO
SPI-Interface
SPI (for diagnosis) Reset
SCK SS
16 15 14 13 9 10 8 7 32 31 30 29 28 27 26 25 22 23 17 19 18 20 1 2 3 12 6 21 5 11 4 24
RX TX RT UB_REF A1 A2 E1 E2 AN_IN0 AN_IN1 AN_IN2 AN_IN3 AN_IN4 AN_IN5 AN_IN6 AN_IN7 CLK INT SS SO SI SCK AREF VDD5A GNDA UBat VDD5 VDDIO GND1 GND2 RST TST
E1
small signal stages
-1
Reset
ISO-Interface
UBREF RX
E2 A2 A1
2x
ISO9141 -1
TX RT
Reset
RST
TST
GNDL
GND2
VDDIO
UBat
1
(c)1/2004 All rights reserved by Robert Bosch GmbH including the right to file industrial property rights Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution. page 1
preliminary GENERAL DESCRIPTION
The CY100 is designed to assist a low voltage microcontroller in automotive applications. The eight channel 10 bit analog-to-digital converter ADC operates half-automatically with 5 V-inputs. Because of the possibility of slew rate limitation, the ISO interface can operate both in BSS and LIN applications. Two signal stages with diagnosis can be used to control small signal loads like light emitting diodes ( LEDs ). With the SPI interface the controller can communicate without real time conditions up to 2 Mbaud. Parameter
Input range Switched capacitance Resolution for the input range Conversion time for each channel ( f=2,5 MHz ) Maximum sample rate AREF = 5 V : Resolution, 0.1 V < AN_INx < 4.9 V Resolution, AN_INx 100 mV Resolution, AN_INx 4.9 V
Min
-0.3
Max
UVDD5A + 0.3 20 10 122 1 2 4 4
Unit
V pF Bit s kHz LSB LSB LSB
MAXIMUM RATINGS
Parameter
Voltage, RT Voltage, UBat, UB_REF Voltage, A1, A2 Voltage, VDD5, VDD5A, AREF Voltage, VDDIO Voltage, AN_INx, CLK, E1, E2, RST, SCK, SI, SS, TX Maximum Voltage, INT, RX, SO Frequency operating range Maximum SPI transfer rate Operating temperature Tj Thermal resistance ESD HBM, MIL883D 3015 100pF / 1.5k A1, A2, RT All other pins Maximum Maximum Maximum Maximum Maximum Maximum
Min
-15 -2 -0.6 -0.3 -0.3 -0.3 -0.3 2.5 -40 -4 -2
Max
60 60 60 6 4
Unit
V V V V V V
VDD5
MUX AN_IN0 Rmux Rmux Rmux
GNDA
UVDD5 + 0.3 UVDDIO V + 0.3 12 MHz 2 MBd 150 C 60 K/W +4 +2 kV kV
S&H
Rmux Rmux Rmux
Cs
VDD5
Rmux
Rin
Rmux AREF
ADC (10 Bit; SAR)
01 1 01 1 0101
AN_IN3
Cmax
offset channel
GNDA TTestm 3 TESTM3 GNDA
R
D on S
Rmux
digital offset compensation
A / D CONVERTER ( ADC )
The CY100 uses an 10 Bit SAR ( successive approximation register ) Converter with S & H ( sample and hold ) element. The total error ( gain, offset, nonlinearity ) is less than 2 LSB and less than 4 LSB near ground or AREF. The CY100 has an internal offset compensation algorithmus. The conversion and sample time for each channel is faster than 125 us. The ADC is muxed to 8 external input channels except channel 5, which is additional multiplexed with the internal channel for the CY100 offset compensation on chip. So a converting time of 1 ms of channel 0 to 4 and 6 to 7 can reached, whereas channel 5 can be converted every 2 ms. All 8 channels are running in timed mode without jitter. The input voltage range is 0 V .. 5.5 V. The input pins AN_INx are clamped to VDD5 and GND by an ESD protection diode. The ADC has a separate reference input pin AREF. After conversion of all 8 channels the results are storaged in the result RAM. After ending the conversion of channel 7 the output INT becomes active ( low ). This output can be used to trigger a microcontroller with interrupt or DMA request.
offset reference for compensation
result register RAM Bank0 Bank1
IN T
Control
internal bus
ADC - SPI transfer register (BIOR)
fCCL K
(=2. H or 3M z) 5M z H
SPI
Divider 1 (1,2,3 or 4)
fcycle
Divider 2 (2500, 3000, 5000 or 6000)
CLK
2
(c)1/2004 All rights reserved by Robert Bosch GmbH including the right to file industrial property rights Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution. page 2
preliminary SERIAL INTERFACE / ISO DRIVER
Integrated in the CY100 is one bi-directional serial interface driver, enabling data transfer according to ISO 9141. The driver can be used, for example, as the diagnosis interface, for an immobilizer or for a generator interface. If the interface is not used, the transmitter side can be deployed as a smallsignal stage. The input/output pin RT is protected against destruction from ISO impulses 3a and 3b.
SMALL SIGNAL STAGES
Two identical small-signal stages with open-drain outputs are integrated in the CY100. The output stages are mainly for digital outputs, for the control of "semi-intelligent" actors ( e.g. semi-conductor relays ) and for driving LEDs. The inputs E1 and E2 are realized as comparators with VDDIO - dependent threshold. The inputs have pull-up current sources, so that in case of an open input, the output stages are disabled. The phase of the outputs is noninverting. The output stages are disabled ( transistors switched off ), when the reset signal on RST is active.
VDDIO VDDIO
SPI-Bit s
shut off time /
shut off filter time
(SOT_EN ISO_DLY , )
RT
VDDIO
TX
SPI-Bits
Transmitter
diagnose
Ax
other modules
slew rate control
SPI-Bit (ISO_SRC)
Ex
RST
&
UB_REF
Reset signal RST
Receiver
RX
The transmit-function has to be enabled via SPI soft reset after an active RST ( low ). The open-drain outputs are current-limited, in addition the output voltage on Ax ( x=1;2 ) is monitored for plausibility. If the voltage at Ax still exceeds a certain defined threshold after switch on the output transistor and after a predefined time tvoff, a shortcircuit to battery is detected and the stage is turned off.
divider on/off
Parameter
RT low level at IRT = 40 mA RT nominal output current RT off state input current RT slew rate limitation, negative edge, deactivatable RX1 low output voltage RX1 high output voltage TX1 low level TX1 high level
Min
-5 1 0 UVDDIO - 0.4 -0.3 0.7 * UVDDIO
Max
1.4 50 10 3 0.5 UVDDIO 0.3 * UVDDIO UVDD5 + 0.3
Unit
V mA A V/s V V V V
The output stages can also be diagnosed. The error conditions short-circuit to battery ( SCB), short-circuit to ground ( SCG ) and open-load ( OL ) are detected. Error detection is done selectively according to the output stage condition : OL and SCG are detected when the output stage is disabled; SCB is detected when the output stage is on. The errors OL , SCB and SCG are filtered. Parameter
A1, A2 maximum voltage A1, A2 nominal output current A1, A2 regulated short circuit current A1, A2 on resistance Switching time E1 to A1, E2 to A2
Min
-0.6 50
Max
60 50 120 14 2
Unit
V mA mA s
The OL diagnosis can be disabled individually via the SPI interface for each output stage for applications, for which the diagnostic current can disturb ( e.g. LEDs ). Disable means, zero diagnostic current for OL and deactivated error indication OL.
3
(c)1/2004 All rights reserved by Robert Bosch GmbH including the right to file industrial property rights Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution. page 3
preliminary SPI INTERFACE
configuration reg. (read / write) status registers (read only)
The serial SPI interface establishes a communication link between CY100 and the systems microcontroller. The CY100 always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud. Applying an active slave select signal at SS CY100 is selected by the SPI master. SI is the slave in data input, SO the slave out data output. Via the serial clock input SCK the SPI clock is provided by the SPI master. In case of inactive slave select signal ( high ) or active reset the data output SO is high impedance ( tristate ). The first two bits of an instruction are used to realize an extended device-addressing. This gives the opportunity to operate up to 4 slave-devices sharing one common SS signal from the master-unit.
SS SCK SO SI
SPI Control:
State Machine
SPI Shift Register
ID registers (read only)
ADC RAM (read / write)
SYSTEM APPLICATION EXAMPLE
Sensor 1 Sensor 2 Sensor 3 Sensor 4 Sensor 5 Sensor 6 Sensor 7 Sensor 8
5V Signal 5V Signal 5V Signal 5V Signal 5V Signal 5V Signal 5V Signal 5V Signal
Ch1
Ch2
CY100 10Bit A/D @5V, 8xMUX
SI
Ch3
Ch4
RAM
Ch5
SO SCK
3V SPI
DATA BUS
3V C
3V SPI
Ch6
/SS
Ch7
-
Ch8
Contact Robert Bosch GmbH Automotive Electronics AE / VKF Sales Components Postfach 1342 D-72703 Reutlingen Germany Phone: +49 (0) 7121 / 35-2179 E-Mail: bosch.semiconductors@de.bosch.com Datasheet_CY100.doc Rev. 3 4
(c)1/2004 All rights reserved by Robert Bosch GmbH including the right to file industrial property rights Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution. page 4

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