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| PMC FEATURES Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 512 Kbit / 1Mbit / 2Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory * Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V * Memory Organization - Pm39LV512: 64K x 8 (512 Kbit) - Pm39LV010: 128K x 8 (1 Mbit) - Pm39LV020: 256K x 8 (2 Mbit) - Pm39LV040: 512K x 8 (4 Mbit) * High Performance Read - 55/70 ns access time * Cost Effective Sector/Block Architecture - Uniform 4 Kbyte sectors - Uniform 64 Kbyte blocks (sector group - except Pm39LV512) * Data# Polling and Toggle Bit Features * Hardware Data Protection * Automatic Erase and Byte Program - Build-in automatic program verification - Typical 16 s/byte programming time - Typical 55 ms sector/block/chip erase time * Low Power Consumption - Typical 4 mA active read current - Typical 8 mA program/erase current - Typical 0.1 A CMOS standby current * High Product Endurance - Guarantee 100,000 program/erase cycles per single sector (preliminary) - Minimum 20 years data retention * Industrial Standard Pin-out and Packaging - 32-pin (8 mm x 14 mm) VSOP - 32-pin PLCC - Optional lead-free (Pb-free) package GENERAL DESCRIPTION The Pm39LV512/010/020/040 are 512 Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are designed to use a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The 12.0 Volt VPP power supply for program and erase operations are not required. The devices can be programmed in standard EPROM programmers as well. The memory array of Pm39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory arrays of Pm39LV010/020/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase operation. The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The program operation is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by issuing the chip erase, block, or sector erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions, the progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or the Toggle Bit on I/O6. The Pm39LV512/010/020/040 are manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASHTM. The devices are offered in 32-pin VSOP and PLCC packages with access time of 55 and 70 ns. Programmable Microelectronics Corp. 1 Issue Date: December, 2003 Rev:1.2 PMC CONNECTION DIAGRAMS Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 39LV040 WE# WE# WE# WE# A16 A12 A15 A18 39LV020 VCC A12 A15 A16 39LV512 39LV010 A12 A15 A16 NC VCC VCC NC A12 A15 NC NC VCC 39LV040 39LV020 39LV010 39LV512 NC NC A17 A17 39LV512 39LV010 39LV020 39LV040 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 14 39LV512 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 15 I/O2 16 GND 17 I/O3 18 I/O4 19 I/O5 I/O5 I/O5 I/O5 20 I/O6 I/O6 I/O6 I/O6 39LV010 I/O1 I/O1 I/O3 I/O3 I/O3 39LV020 GND GND I/O2 I/O1 39LV040 I/O1 I/O2 32-Pin PLCC 39LV040 39LV020 39LV010 39LV512 GND I/O2 I/O4 I/O4 I/O4 39LV512 39LV010 39LV020 39LV040 A11 A9 A8 A13 A14 A17 WE# V CC A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# V CC NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# V CC NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# V CC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32-Pin VSOP Programmable Microelectronics Corp. 2 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 PRODUCT ORDERING INFORMATION Pm39LV0x0 -70 J C E Environmental Attribute E = Lead-free (Pb-free) Package Blank = Standard Package Temperature Range C = Commercial (0C to +70C) Package Type J = 32-pin Plastic J-Leaded Chip Carrier (32J) V = 32-pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)(32V) Speed Option PMC Device Number Pm39LV512 (512 Kbit) Pm39LV010 (1 Mbit) Pm39LV020 (2 Mbit) Pm39LV040 (4 Mbit) Part Number PM39LV512-70JCE 32J Pm39LV512-70JC 70 Pm39LV512-70VCE 32V Pm39LV512-70VC Pm39LV010-70JCE 32J Pm39LV010-70JC 70 Pm39LV010-70VCE 32V Pm39LV010-70VC Pm39LV020-70JCE 32J Pm39LV020-70JC 70 Pm39LV020-70VCE 32V Pm39LV020-70VC Pm39LV040-70JCE 32J Pm39LV040-70JC 70 Pm39LV040-70VCE 32V Pm39LV040-70VC Programmable Microelectronics Corp. tACC (ns) P ackag e Temperature Range Commercial (0C to +70C) 3 Issue Date: December, 2003 Rev: 1.2 PMC PIN DESCRIPTIONS Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 SYMBOL A0 - AMS(1) TYPE INPUT DESCRIPTION Address Inputs: For memory addresses input. Addresses are internally latched on the falling edge of WE# during a write cycle. Chip Enable: CE# goes low activates the device's internal circuitries for device operation. CE# goes high deselects the device and switches into standby mode to reduce the power consumption. Write Enable: Activate the device for write operation. WE# is active low. Output Enable: Control the device's output buffers during a read cycle. OE# is active low. Data Inputs/Outputs: Input command/data during a write cycle or output data during a read cycle. The I/O pins float to tri-state when OE# are disabled. Device Power Supply Ground No Connection C E# INPUT WE# OE# I/O0 - I/O7 V CC GND NC Note: INPUT INPUT INPUT/ OUTPUT 1. AMS is the most significant address where AMS = A15 for Pm39LV512, A16 for Pm39LV010, A17 for Pm39LV020, and A18 for Pm39LV040. Programmable Microelectronics Corp. 4 Issue Date: December, 2003 Rev: 1.2 PMC BLOCK DIAGRAM Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 ERASE/PROGRAM VOLTAGE GENERATOR I/O0-I/O7 I/O BUFFERS HIGH VOLTAGE SWITCH WE# CE# OE# COMMAND REGISTER CE,OE LOGIC DATA LATCH SENSE AMP ADDRESS LATCH Y-DECODER X-DECODER Y-GATING MEMORY ARRAY A0-A M S DEVICE OPERATION READ OPERATION The access of Pm39LV512/010/020/040 are similar to EPROM. To read data, three control functions must be satisfied: * CE# is the chip enable and should be pulled low ( VIL ). * OE# is the output enable and should be pulled low ( VIL). * WE# is the write enable and should remains high ( VIH ). PRODUCT IDENTIFICATION The product identification mode can be used to identify the manufacturer and the device through hardware or software read ID operation. See Table 1 for PMC Manufacturer ID and Device ID. The hardware ID mode is activated by applying a 12.0 Volt on A9 pin, typically used by an external programmer for selecting the right programming algorithm for the devices. Refer to Table 2 for Bus Operation Modes. The software ID mode is activated by a three-bus-cycle command. See Table 3 for Software Command Definition. Programmable Microelectronics Corp. BYTE PROGRAMMING The programming is a four-bus-cycle operation and the data is programmed into the devices (to a logical "0") on a byte-by-byte basis. See Table 3 for Software Command Definition. A program operation is activated by writing the three-byte command sequence followed by program address and one byte of program data into the devices. The addresses are latched on the falling edge of WE# or CE# whichever occurs later, and the data are latched on the rising edge of WE# or CE# whichever occurs first. The internal control logic automatically handles the internal programming voltages and timing. A data "0" can not be programmed back to a "1". Only erase operation can convert the "0"s to "1"s. The Data# Polling on I/O7 or Toggle Bit on I/O6 can be used to detect the progress or completion of a program cycle. 5 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 DEVICE OPERATION (CONTINUED) CHIP ERASE The entire memory array can be erased through a chip erase operation. Pre-programs the devices are not required prior to a chip erase operation. Chip erase starts immediately after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The devices will return to standby mode after the completion of chip erase. SECTOR AND BLOCK ERASE The memory array of Pm39LV512/010/020/040 are organized into uniform 4 Kbyte sectors. A sector erase operation allows to erase any individual sector without affecting the data in others. The memory array of Pm39LV010/020/040, excluding Pm39LV512, are also organized into uniform 64 Kbyte blocks (sector group consists of sixteen adjacent sectors). A block erase operation allows to erase any individual block. The sector or block erase operation is similar to chip erase. I/O7 DATA# POLLING The Pm39LV512/010/020/040 provide a Data# Polling feature to indicate the progress or completion of a program and erase cycles. During a program cycle, an attempt to read the devices will result in the complement of the last loaded data on I/O7. Once the program operation is completed, the true data of the last loaded data is valid on all outputs. During a sector, block, or chip erase cycle, an attempt to read the device will result a "0" on I/O7. After the erase operation is completed, an attempt to read the device will result a "1" on I/O7. I/O6 TOGGLE BIT The Pm39LV512/010/020/040 also provide a Toggle Bit feature to detect the progress or completion of a program and erase cycles. During a program or erase cycle, an attempt to read data from the device will result a toggling between "1" and "0" on I/O6. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase cycle. HARDWARE DATA PROTECTION Hardware data protection protects the devices from unintentional erase or program operation. It is performed in the following ways: (a) VCC sense: if VCC is below 1.8 V (typical), the write operation is inhibited. (b) Write inhibit: holding any of the signal OE# low, CE# high, or WE# high inhibits a write cycle. (c) Noise filter: pulses of less than 5 ns (typical) on the WE# or CE# input will not initiate a write operation. Table 1. Product Identification Product Identification Manufacturer ID Device ID: Pm39LV512 Pm39LV010 Pm39LV020 Pm39LV040 1B h 1C h 3D h 3E h Data 9D h Programmable Microelectronics Corp. 6 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 SECTOR/BLOCK ADDRESS TABLE Block Siz e (Kbytes) Sector Siz e (Kbytes) 4 4 Memory Density Block (1) Sector Sector 0 Sector 1 Address Range 00000h - 00F F F h 01000h - 01F F F h 512K bi t Block 0 (2) 64 : Sector 15 1 Mbit Sector 16 2 Mbit Block 1 4 Mbit Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 64 64 64 64 64 64 64 Sector 17 : 4 4 4 : 0F 000h - 0F F F F h 10000h - 10F F F h 11000h - 11FFFh : Sector 31 : 4 : 1F 000h - 1F F F F h 20000h - 2F F F F h 30000h - 3F F F F h 40000h - 4F F F F h 50000h - 5F F F F h 60000h - 6F F F F h 70000h - 7F F F F h " " " " " " " " " " " " Notes: 1. A Block is a 64 Kbyte sector group which consists of sixteen adjecent sectors of 4 Kbyte each. 2. Block erase feature is available for Pm39LV010/020/040 only. The chip erase command should be used to erase the Block 0 for the Pm39LV512. Programmable Microelectronics Corp. 7 Issue Date: December, 2003 Rev: 1.2 PMC OPERATING MODES Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 Table 2. Bus Operation Modes Mode Read Write Standby Output Disable C E# VIL VIL VIH X OE# VIL VIH X VIH WE# VIH VIL X X ADDRESS X (1) I/O DOUT DIN High Z High Z Manufacturer ID X X X A2 - AMS (2) = X, A9 = VH (3), A1 = VIL, A0 = VIL A2 - AMS (2) = X, A9 = VH (3), A1 = VIL, A0 = VIH 3. VH = 12.0 V 0.5 V. Product Identification Hardware VIL VIL VIH Device ID Notes: 1. X can be VIL, VIH or addresses. 2. AMS = Most significant address; AMS = A15 for Pm39LV512, A16 for Pm39LV010, A17 for Pm39LV020, and A18 for Pm39LV040. COMMAND DEFINITION Table 3. Software Command Definition 1st B u s C ycle Addr D ata Addr D OUT 555h A A h 555h A A h 555h A A h 555h A A h 555h A A h 555h A A h X X X h F 0h 2A A h 55h 2A A h 55h 2A A h 55h 2A A h 55h 2A A h 55h 2A A h 55h 555h 80h 555h 80h 555h 80h 555h A 0h 555h 90h 555h F 0h 555h A A h 555h A A h 555h A A h Addr D IN 2A A h 55h 2A A h 55h 2A A h 55h 555h 10h SA (1) 30h BA (2) 50h 2n d B u s C ycle Addr D ata 3rd B us C ycle Addr D ata 4th B us C ycle Addr D ata 5th B us C ylce Addr D ata 6th B us C ycle Addr D ata C ommand S eq u en ce Read C hi p Erase Sector Erase Block Erase Byte Program Product ID Entry Product ID Exi t (3) Product ID Exi t (3) B us C ycle 1 6 6 6 4 3 3 1 Notes: 1. SA = Sector address of the sector to be erased. 2. BA = Block address of the block to be erased. 3. Either one of the Product ID Exit command can be used. Programmable Microelectronics Corp. 8 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 DEVICE OPERATIONS FLOWCHARTS AUTOMATIC PROGRAMMING Start Load Data AAh to Address 555H Load Data 55h to Address 2AAh Address Increment Load Data A0h to Address 555h Load Program Data to Program Address I/O7 = Data? or I/O6 Stop Toggle? No Yes Last Address? No Yes Programming Completed Chart 1. Automatic Programming Flowchart Programmable Microelectronics Corp. 9 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 DEVICE OPERATIONS FLOWCHARTS (CONTINUED) AUTOMATIC ERASE Start Write Sector, Block, or Chip Erase Command No Data = FFh? or I/O6 Stop Toggle? Yes Erasure Completed CHIP ERASE COMMAND Load Data AAh to Address 555h SECTOR ERASE COMMAND Load Data AAh to Address 555h BLOCK ERASE COMMAND Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 80h to Address 555h Load Data 80h to Address 555h Load Data 80h to Address 555h Load Data AAh to Address 555h Load Data AAh to Address 555h Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh Load Data 10h to Address 555h Load Data 30h to SA Load Data 50h to BA Chart 2. Automatic Erase Flowchart Programmable Microelectronics Corp. 10 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 DEVICE OPERATIONS FLOWCHARTS (CONTINUED) SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT Load Data AAh to Address 555h Load Data AAh to Address 555h Load Data 55h to Address 2AAh Load Data 55h to Address 2AAh or Load Data F0h to Address XXXh Load Data 90h to Address 555h Load Data F0h to Address 555h Exit Product Identification Mode (3) Enter Product Identification Mode (1,2) Exit Product Identification Mode (3) Notes: 1. The device will enter Product Identification mode after excuting the Product ID Entry command. 2. Under Product Identification mode, the Manufacturer ID and Device ID of devices can be read at address X0000h and X0001h where X = Don't Care. 3. The device returns to standby operation. Chart 3. Software Product Identification Entry/Exit Flowchart Programmable Microelectronics Corp. 11 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 ABSOLUTE MAXIMUM RATINGS (1) Temperature Under Bias Storage Temperature Standard Package Surface Mount Lead Soldering Temperature Lead-free Package Input Voltage with Respect to Ground on All Pins except A9 pin (2) Input Voltage with Respect to Ground on A9 pin (3) All Output Voltage with Respect to Ground VCC (2) 260C 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to +13.0 V -0.5 V to VCC + 0.5 V -0.5 V to +6.0 V -65C to +125C -65C to +125C 240C 3 Seconds Notes: 1. Stresses under those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. 3. Maximum DC voltage on A9 pin is +13.0 V. During voltage transitioning period, A9 pin may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on A9 pin is -0.5 V. During voltage transitioning period, A9 pin may undershoot GND to -2.0 V for a period of time up to 20 ns. DC AND AC OPERATING RANGE Part Number Operating Temperature Vcc Power Supply Pm39LV512/010/020/040 0C to 70C 2.7 V - 3.6 V Programmable Microelectronics Corp. 12 Issue Date: December, 2003 Rev: 1.2 PMC DC CHARACTERISTICS Symbol ILI ILO ISB1 ISB2 ICC1 ICC2 (1) VIL VIH VOL VOH Parameter Input Load Current Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 Condition VIN = 0 V to VCC VI/O = 0 V to VCC CE#, OE# = VCC 0.3 V CE# = VIH to VCC f = 5 MHz; IOUT = 0 mA Min Typ Max 1 1 Units A A A mA mA mA V V V V Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current VCC Program/Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.1 0.05 4 8 -0.5 0.7 VCC 5 3 15 20 0.8 VCC + 0.3 0.45 IOL = 2.1 mA; VCC = VCC min IOH = -100 A; VCC = VCC min VCC - 0.2 Note: 1. Characterized but not 100% tested. AC CHARACTERISTICS READ OPERATIONS CHARACTERISTICS Pm39LV512-55 Pm39LV010-55 Pm39LV020-55 Pm39LV040-55 Pm39LV512-70 Pm39LV010-70 Pm39LV020-70 Pm39LV040-70 Symbol Parameter Units Min tRC tACC tCE tOE tDF tOH tVCS Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay CE# or OE# to Output High Z Output Hold from OE#, CE# or Address, whichever occured first VCC Set-up Time 0 0 50 55 Max Min 70 Max ns 70 70 35 ns ns ns ns ns s 55 55 30 15 0 0 50 25 Programmable Microelectronics Corp. 13 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 AC CHARACTERISTICS (CONTINUED) READ OPERATIONS AC WAVEFORMS t RC ADDRESS ADDRESS VALID t ACC CE# t CE t OE t DF OE# WE# tO H OUTPUT HIGH Z OUTPUT VALID t VCS VCC OUTPUT TEST LOAD 3.3 V INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 1.8 K OUTPUT PIN 3.0 V Input 0.0 V 1.5 V AC Measurement Level 1.3 K C L = 30 pF PIN CAPACITANCE ( f = 1 MHz, T = 25C ) Typ CIN COUT 4 8 Max 6 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V Note: These parameters are characterized but not 100% tested. Programmable Microelectronics Corp. 14 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 AC CHARACTERISTICS (CONTINUED) WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS Pm39LV512-55 Pm39LV010-55 Pm39LV020-55 Pm39LV040-55 Pm39LV512-70 Pm39LV010-70 Pm39LV020-70 Pm39LV040-70 Symbol Parameter U nits Min tWC tAS tAH tCS tCH tOEH tDS tDH tWP tWPH tBP tEC tVCS Wri te C ycle Ti me Address Set-up Ti me Address Hold Ti me C E# and WE# Set-up Ti me C E# and WE# Hold Ti me OE# Hi gh Hold Ti me D ata Set-up Ti me D ata Hold Ti me Wri te Pulse Wi dth Wri te Pulse Wi dth Hi gh Byte Programmi ng Ti me C hi p or Block Erase Ti me VCC Set-up Ti me 50 55 0 30 0 0 10 40 0 35 20 Max Min 70 0 30 0 0 10 40 0 35 20 Max ns ns ns ns ns ns ns ns ns ns 30 100 s ms s 30 100 50 PROGRAM OPERATIONS AC WAVEFORMS - WE# CONTROLLED Program Cycle OE# tV C S CE# tC H tC S WE# tW P tW P H tB P tA S A0 - A M S 555 tA H 2AA 555 ADDRESS tW C DATA IN AA tD S 55 tD H A0 INPUT DATA VALID DATA V CC Issue Date: December, 2003 Rev: 1.2 Programmable Microelectronics Corp. 15 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 AC CHARACTERISTICS (CONTINUED) PROGRAM OPERATIONS AC WAVEFORMS - CE# CONTROLLED Program Cycle OE# tV C S WE# tC H tC S CE# tW P tW P H tB P tA S A0 - A M S tA H 555 2AA 555 ADDRESS tW C DATA IN AA tD S 55 tD H A0 INPUT DATA VALID DATA V CC CHIP ERASE OPERATIONS AC WAVEFORMS OE# tV C S CE# tW P WE# tW P H tD H tA S AO - A M S tA H 555 tW C AA 2AA 555 555 2AA 555 tD S 55 80 AA 55 10 tE C DATA IN V CC Programmable Microelectronics Corp. 16 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 AC CHARACTERISTICS (CONTINUED) SECTOR OR BLOCK ERASE OPERATIONS AC WAVEFORMS OE# tV C S CE# tW P WE# tW P H tD H tA S AO - A M S tA H 555 tW C AA 2AA 555 555 2AA Sector or Block Address tD S 55 80 AA 55 30 or 50 tE C DATA IN V CC TOGGLE BIT AC WAVEFORMS WE# CE# tO E H OE# tO E I/O6 DATA TOGGLE TOGGLE STOP TOGGLING tD F tO H VALID DATA Note: Toggling CE#, OE#, or both OE# and CE# will operate Toggle Bit. Programmable Microelectronics Corp. 17 Issue Date: December, 2003 Rev: 1.2 PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 AC CHARACTERISTICS (CONTINUED) DATA# POLLING AC WAVEFORMS WE# CE# t CH t OEH t CE OE# t OE tO H I/O7 I/O7# VALID DATA t DF Note: Toggling CE#, OE#, or both OE# and CE# will operate Data# Polling. PROGRAM/ERASE PERFORMANCE Parameter Sector Erase Time Block Erase Time Chip Erase Time Byte Programming Time Unit ms ms ms s Typ 55 55 55 16 Max 100 100 100 30 Remarks From writing erase command to erase completion From writing erase command to erase completion From writing erase command to erase completion Excludes the time of four-cycle program command execution Note: These parameters are characterized but not 100% tested. RELIABILITY CHARACTERISTICS (1) Parameter Endurance Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up Min 100,000 20 2,000 200 100 + ICC1 (2) Typ Unit Cycles Years Volts Volts mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 Note: 1. These parameters are characterized but not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test. 18 Issue Date: December, 2003 Rev: 1.2 Programmable Microelectronics Corp. PMC Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 PACKAGE TYPE INFORMATION 32J 32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters) 12.57 12.32 11.51 11.35 15.11 14.86 Pin 1 I.D. 14.05 13.89 SEATING PLANE 0.74X30 3.56 3.18 2.41 1.93 13.46 12.45 0.53 0.33 0.81 0.66 1.27 Typ. 32V 32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters) 1.05 0.95 Pin 1 I.D. 0.27 0.17 8.10 7.90 0.50 BSC 0.15 0.05 12.50 12.30 14.20 13.80 1.20 MAX 0.25 0 5 0.20 0.10 0.70 0.50 Programmable Microelectronics Corp. 19 Issue Date: December, 2003 Rev: 1.2 PMC REVISION HISTORY Pm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040 Date May, 2003 September, 2003 Revision No. Description of Changes 1.0 1.1 Preliminary Information Updated program description and formal release Added Lead-free package option Upgraded guranteed program/erase cycles from 50,000 to 100,000 (preliminary) Revised output test load as 30 pF for all speed Revised package dimension information P ag e N o . All 5 1, 3, 12 1, 18 14 19 December, 2003 1.2 Programmable Microelectronics Corp. 20 Issue Date: December, 2003 Rev: 1.2 |
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