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PRELIMINARY
March 17, 2003
IP2012 / IP2022 Wireless Network Processors
Features and Performance Optimized for Network Connectivity
1.0
Product Highlights
inexpensive product design and, when needed, quick and easy reconfiguration to accommodate changes in market needs or industry standards.
The Ubicom IP2012TM and IP2022TM Wireless Network Processors combine support for communication physical layer, Internet protocol stack, device-specific application, and device-specific peripheral software modules in a single chip, and are reconfigurable over the Internet. They can be programmed, and reprogrammed, using pre-built software modules and configuration tools to create true single-chip solutions for a wide range of device-to-device and device-to-human communication applications. High speed communication interfaces are available via on-chip hardware Serializer/Deserializer (SerDes) blocks. These full-duplex blocks allow the IP2022 or IP2012 to be used in a variety of communication bridging applications. Each SerDes block is capable of supporting 10Base-T Ethernet (MAC and PHY), USB, GPSI, SPI, or UART. The highspeed operating frequency, combined with most instructions executing in a single cycle, delivers the throughput needed for emerging network connectivity applications. A flash-based program memory allows both in-system and runtime reprogramming. The IP2022 and IP2012 implement most peripheral, communications and control functions via software modules (ipModuleTM software), replacing traditional hardware for maximum system design flexibility. This approach allows rapid,
Key Features:
* Designed to support single-chip networked solutions * Fast processor core * 64kB Flash program memory * 16kB SRAM data/program memory * 4kB SRAM data memory * Two SerDes communication blocks supporting common PHYs (Ethernet, USB, UARTs, etc.) and bridging applications (IP2012 has only one SerDes unit) * Advanced RISC processors * IP2022 -- 120 and 160 MHz versions * IP2012 -- 120 MHz version * High speed packet processing * Instruction set optimized for communication functions * Supports software implementation of traditional hardware functions * In-system reprogrammable for highest flexibility * Run time self-programmable * Vpp = Vcc supply voltage
ipModuleTM Software
Customer Application HTTP/SMTP/TFTP TCP/UDP IP/ICMP Network Access Layer PHY Firmware Choices for Communication:
IP2022/IP2012
8/16-Bit Parallel Slave Port Internet Processor CPU 64-Kbyte Flash Memory
ipOS Operating System 16-Kbyte Inst./Data RAM 4-Kbyte Data RAM External Memory Interface General Purpose I/O Ports
Choices for Communication: ISA (802.11b) Mini-PCI/Cardbus (802.11g/802.11a) I2C General-Purpose I/O 10Base-T Ethernet (MAC/PHY on chip) USB 1.1 (SIE on chip) GPSI SPI UART/Modem Bluetooth HCI
Host Bus
10Base-T Ethernet (MAC/PHY on chip) USB 1.1 (SIE on chip) GPSI SPI UART/Modem Bluetooth HCI
High-Speed Serial Unit 1 (SERDES)
5 Timers
PLL Clock Multiplier
8-Input 10-Bit A/DC
ISP/ISD Interface
High-Speed Serial Unit 2 (SERDES)
515-063b.eps
Not available on IP2012
Figure 1-1 IP2012 / IP2022 Block Diagram
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IP2012 / IP2022 Data Sheet 1 Additional Features. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.2 Serializer/Deserializers . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.3 Low-Power Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.6 Other Supported Functions . . . . . . . . . . . . . . . . . . . . . . .5 1.2.7 Programming and Debugging Support . . . . . . . . . . . . . . .5 2.0 Pin Definitions 6 2.1 PQFP (Plastic Quad Flat Package) for IP2022. . . . . .6 2.2 PQFP (Plastic Quad Flat Package) for IP2012. . . . . .7 2.3 BGA (Micro Ball Grid Array) IP2022-120 Only . . . . .8 2.4 Signal Descriptions -- IP2022 . . . . . . . . . . . . . . . . . .9 2.5 Signal Descriptions -- IP2012 . . . . . . . . . . . . . . . . .12 15 3.0 System Architecture 3.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.1 Loading the Program RAM . . . . . . . . . . . . . . . . . . . . . .19 3.3.2 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4 Low Power Support . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4.1 Clock Stop Mode (SLEEP) . . . . . . . . . . . . . . . . . . . . . .21 3.4.2 Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.5 Speed Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.6 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.7 Interrupt Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.7.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.7.2 Global Interrupt Enable Bit . . . . . . . . . . . . . . . . . . . . . .25 3.7.3 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.7.4 Return From Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.7.5 Disabled Interrupt Resources . . . . . . . . . . . . . . . . . . . .26 3.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.8.1 Brown-Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.8.2 Reset and Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . .28 3.8.3 Register States Following Reset . . . . . . . . . . . . . . . . . .28 3.9 Clock Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.9.1 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.10 Configuration Block. . . . . . . . . . . . . . . . . . . . . . . . . .31 3.10.1 FUSE0 Register (not run-time programmable) . . . . . . . . .32 3.10.2 FUSE1 Register (not run-time programmable) . . . . . . . . .33 3.10.3 TRIM0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 35 4.0 Instruction Set Architecture 4.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.1.1 Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.1.2 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . .36 4.1.3 Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . .36 4.1.4 Indirect-with-Offset Addressing Mode . . . . . . . . . . . . . . .37 4.2 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.2.1 Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.2.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.3 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.4 Subroutine Call/Return Stack . . . . . . . . . . . . . . . . . .41 4.5 Key to Abbreviations and Symbols . . . . . . . . . . . . . .42 4.6 Instruction Set Summary Tables. . . . . . . . . . . . . . . .42 4.7 Program Memory Instructions. . . . . . . . . . . . . . . . . .47 4.7.1 Flash Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . .48 4.7.2 Interrupts During Flash Operations . . . . . . . . . . . . . . . . .48 49 5.0 Peripherals 5.1 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.1.1 Port B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.1.2 Reading and Writing the Ports . . . . . . . . . . . . . . . . . . . .50 5.1.3 RxIN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.1.4 RxOUT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.1.5 RxDIR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.6 INTED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.7 INTF Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.8 INTE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.1.9 Port Configuration Upon Power-Up . . . . . . . . . . . . . . . .51 5.2 Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.3 Real-Time Timer (RTTMR) . . . . . . . . . . . . . . . . . . . .52 5.4 Multi-Function Timers (T1 and T2) . . . . . . . . . . . . . .54 5.4.1 Timers T1, T2 Operating Modes . . . . . . . . . . . . . . . . . .54 5.4.2 T1 and T2 Timer Pin Assignments . . . . . . . . . . . . . . . . .56 1.1 1.2
2
1.0 Product Highlights
5.5 5.6
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . .57 Serializer/Deserializer (SERDES). . . . . . . . . . . . . . .58 5.6.1 SERDES TX/RX Buffers . . . . . . . . . . . . . . . . . . . . . . . .58 5.6.2 SERDES Configuration . . . . . . . . . . . . . . . . . . . . . . . . .58 5.6.3 SERDES Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5.6.4 Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.5 10base-T Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.6.6 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.6.7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.6.8 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 5.6.9 GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5.7 Analog to Digital Converter (ADC) . . . . . . . . . . . . . .72 5.7.1 ADC Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . .72 5.7.2 A/D Converter Registers . . . . . . . . . . . . . . . . . . . . . . . .72 5.7.3 Using the A/D Converter . . . . . . . . . . . . . . . . . . . . . . . .73 5.7.4 ADC Result Justification . . . . . . . . . . . . . . . . . . . . . . . .73 5.8 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.8.1 CMPCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.9 Linear Feedback Shift Register (LFSR) . . . . . . . . . .74 5.10 Parallel Slave Peripheral (PSP) . . . . . . . . . . . . . . . .79 5.10.1 PSPCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.11 External Memory Interface (IP2022 only) . . . . . . . . .80 5.11.1 EMCFG Register (IP2022 only) . . . . . . . . . . . . . . . . . . .80 83 6.0 In-System Programming 7.0 Memory Reference 84 7.0.1 Registers (sorted by address) . . . . . . . . . . . . . . . . . . . .84 7.0.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.1 Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . .89 7.1.1 ADCCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.2 ADCTMR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.3 CMPCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.1.4 EMCFG Register (IP2022 only) . . . . . . . . . . . . . . . . . . .90 7.1.5 FCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 7.1.6 INTSPD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.1.7 LFSRA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.1.8 PSPCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.1.9 RTCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.1.10 SxINTE/SxINTF Register . . . . . . . . . . . . . . . . . . . . . . .95 7.1.11 SxMODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.1.12 SxRCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.1.13 SxRCNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.1.14 SxRSYNC Register . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.1.15 SxSMASK Register . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.1.16 SxTCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.1.17 SxTMRH/SxTMRL Register . . . . . . . . . . . . . . . . . . . . . .99 7.1.18 SPDREG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.1.19 STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.1.20 T0CFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.1.21 TxCFG1H Register. . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.1.22 TxCFG2H Register. . . . . . . . . . . . . . . . . . . . . . . . . . .102 7.1.23 TxCFG1L Register . . . . . . . . . . . . . . . . . . . . . . . . . . .102 7.1.24 TxCFG2L Register . . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.1.25 TCTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 7.1.26 XCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 105 8.0 Electrical Characteristics 8.1 Absolute Maximum Ratings). . . . . . . . . . . . . . . . . .105 8.2 DC Specifications: IP2022-120, IP2012-120 . . . . .106 8.3 DC Specifications: IP2022-160. . . . . . . . . . . . . . . .108 8.4 AC Specifications: IP2022-120, IP2012-120 . . . . .110 8.5 AC Specifications: IP2022-160 . . . . . . . . . . . . . . . .111 8.6 Comparator DC and AC Specifications . . . . . . . . .112 8.7 ADC 10-bit Converter DC and AC Specifications . .112 9.0 Package Dimensions 113 9.1 PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.2 BGA (available for IP2022-120 only) . . . . . . . . . .114 10.0 Part Numbering 115
5.4.3
T1 and T2 Timer Registers . . . . . . . . . . . . . . . . . . . . . .56
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IP2012 / IP2022 Data Sheet
1.1
Additional Features
General-Purpose Hardware Peripherals * Two 16-bit timers with 8-bit prescalers supporting: - Timer mode - PWM mode - Capture/Compare mode Parallel host interface, 8/16-bit selectable for use as a communications coprocessor (IP2012 supports 8-bit only) External memory interface (IP2022 only) One 8-bit timer with programmable 8-bit prescaler One 8-bit real-time clock/counter with programmable 15-bit prescaler and 32 kHz crystal input Watchdog timer with prescaler 10-bit, 8-channel ADC with 1/2 LSB accuracy Analog comparator with hysteresis enable/disable Brown-out minimum supply voltage detector External interrupt inputs on 8 pins (Port B)
Internet Processor Capabilities Foundation for Highly Flexible Connectivity Solution * * * * * Performance: 120 MIPS @ 120 MHz, 160 MIPS @ 160 MHz Predictable execution for hard real-time applications Fast and deterministic 3-cycle (25ns @120MHz, 18.75ns @ 160 MHz) internal interrupt response Hardware save/store of key registers Functions implemented via software tightly coupled with hardware assist peripherals
*
* * * * * * * *
Multiple Networking Protocols and Physical Layer Support Hardware * Two full-duplex serializer/deserializer (SERDES) channels (IP2022 has two, IP2012 has one) - Flexible to support 10Base-T, GPSI, SPI, UART, USB protocols - Two channels for protocol bridging - On-chip squelch function for 10Base-T Ethernet on each SERDES Four hardware LFSR (Linear Feedback Shift Register) units - CRC generation/checking - Data whitening - Encryption
Sophisticated Power and Frequency/Clock Management Support * * * Operating voltage of 2.3V to 2.7V (120 MHz) Switching the system clock frequencies between different clock sources On-chip PLL clock multiplier with pre- and post-divider - 120 MHz on-chip clock from 4.8 MHz ext. crystal - 160 MHz on-chip clock from 3.2 MHz ext. crystal Changing the core clock using a selectable divider Shutting down the PLL and/or the OSC input Dynamic CPU speed control with speed instruction Power-On-Reset (POR) logic
*
Memory * * * * * 64-Kbyte (32K 16) on-chip program flash memory 16-Kbyte (8K 16) on-chip program/data RAM 4-Kbyte on-chip linear-addressed data RAM Self-programming with built-in charge pump: instructions to read, write, and erase flash memory Addresses up to 2 Mbytes of external memory (IP2022 only)
* * * *
Flexible I/O * * * * * 52 I/O Pins (48 on IP2012) 2.3V to 3.6V symmetric CMOS output drive (120MHz part) 5V-tolerant inputs Port A pins capable of sourcing/sinking 24 mA Optional I/O synchronization to CPU core clock
CPU Features * * RISC engine core IP2022-120, IP2012-120 - DC to 120 MHz operation - 8.33 ns instruction cycle at max frequency IP2022-160 - DC to 120 MHz and 160 MHz operation only - 6.25 ns instruction cycle at max frequency Compact 16-bit fixed-length instructions Single-cycle instruction execution on most instructions (3 cycles for jumps and calls) Sixteen-level hardware stack for high-performance subroutine linkage 8 8 signed/unsigned single-cycle multiply Pointers and stack operation optimized for C compiler Uniform, linear address space (no register banks)
Re-configurable Over The Internet * * * * * * Customer application program updatable - Run-time self programming On-chip in-system programming interface On-chip in-system debugging support interface Debugging at full IP2022 operating speed Programming at device supply voltage level Real-time emulation, program debugging, and integrated software development environment offered by leading third-party tool vendors
*
* * * * * *
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3
IP2012 / IP2022 Data Sheet
1.2 1.2.1
Architecture CPU
1.2.3
Low-Power Support
The IP2012 and IP2022 implement an enhanced Harvard architecture (i.e. separate instruction and data memories) with independent address and data buses. The 16-bit program memory and 8-bit dual-port data memory allow instruction fetch and data operations to occur in parallel. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by a multistage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. Ubicom has developed a revolutionary RISC-based architecture that is deterministic, jitter free, and completely reprogrammable. The architecture implements a four-stage pipeline (fetch, decode, execute, and write back). At the maximum operating frequency of 160 MHz, instructions are executed at the rate of one per 6.25 ns clock cycle.
Particular attention has been paid to minimizing power consumption. For example, an on-chip PLL allows use of a lower-frequency external source (e.g., an inexpensive 4.8MHz crystal can be used to produce a 120 MHz onchip clock; a 3.2 MHz crystal to produce a 160 MHz onchip clock), which reduces both power consumption and EMI. In addition, software can change the execution speed of the CPU to reduce power consumption, and a mechanism is provided for automatically changing the speed on entry and return from an interrupt service routine. The speed instruction specifies power-saving modes that include a clock divisor between 1 and 128. This divisor only affects the clock to the CPU core, not the timers. The speed instruction also specifies the clock source (OSC1 clock, RTCLK oscillator, or PLL clock multiplier), and whether to disable the OSC1 clock oscillator or the PLL. The speed instruction executes using the current clock divisor.
1.2.4
Memory
1.2.2
Serializer/Deserializers
One of the key elements in optimizing the IP2012 and IP2022 for device-to-device and device-to-human communication is the inclusion of on-chip serializer/deserializer units. Each unit supports popular communication protocols such as GPSI, SPI, UART, USB, and 10Base-T Ethernet, allowing the IP2000 series devices to be used in bridge, access point and gateway applications. By performing data serialization and deserialization in hardware, the CPU bandwidth needed to support serial communications is greatly reduced, especially at high baud rates. Providing two units (IP2022 only) allows easy implementation of protocol conversion or bridging functions between two fast serial devices, such as USBto-Ethernet, GPSI to ethernet, or Ethernet to Ethernet. A single SerDes unit (IP2012) provides the ability to bridge RS232, SPI, or WLAN (802.11b) to Ethernet.
The IP2012 / IP2022 CPU executes from a 32K 16 flash program memory and an 8K 16 RAM program/data memory. In addition, the ability to write into the program flash memory allows flexible non-volatile data storage. An interface is available (IP2022 only) for up to 128K bytes of linearly addressed external memory, which can be expanded to 2M bytes with additional software-based I/O addressing. At 120 MHz operation, the maximum execution rate is 40 MIPS from flash memory and 120 MIPS from RAM. At 160 MHz operation, the maximum execution rate is 53.33 MIPS from flash memory and 160 MIPS from RAM. Speed-critical routines can be copied from the flash memory to the RAM for faster execution. The IP2000 series devices have a mechanism for insystem programming of their flash and RAM program memories through a four-wire SPI interface, and software has the ability to reprogram the program memories at run time. This allows the functionality of a device to be changed in the field over the Internet.
1.2.5
Instruction Set
The IP2000 series instruction set, using 16-bit words, implements a rich set of arithmetic and logical operations, including signed and unsigned 8-bit 8-bit integer multiply with a 16-bit product.
4
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IP2012 / IP2022 Data Sheet
1.2.6
Other Supported Functions
On-chip dedicated hardware also includes a PLL, an 8channel 10-bit ADC, general-purpose timers, single-cycle multiplier, analog comparator, LFSR units, external memory interface (IP2022 only), parallel slave port, brown-out power voltage detector, watchdog timer, lowpower support, multi-source wakeup capability, userselectable clock modes, high-current outputs, and 52 general-purpose I/O pins (48 on IP2012).
1.2.7
Programming and Debugging Support
The IP2000 series has advanced in-system programming and debug support on-chip. This unobtrusive capability is provided through the ISP/ISD interface. There is no need for a bond-out chip for software development. This eliminates concerns about differences in electrical characteristics between a bond-out chip and the actual chip used in the target application. Designers can test and revise code on the same part used in the actual application. Ubicom provides the complete Red Hat GNUPro tools, including C compiler, assembler, linker, utilities and GNU debugger. In addition, Ubicom offers an integrated graphical development environment which includes an editor, project manager, graphical user interface for the GNU debugger, device programmer, and ipModuleTM configuration tool.
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IP2012 / IP2022 Data Sheet
2.0
2.1
Pin Definitions
PQFP (Plastic Quad Flat Package) for IP2022
RST OSC2 OSC1 XVss XVdd RTCLK2 RTCLK1 DVss DVdd AVss AVdd RG7 RG6 RG5 RG4 GVdd
80 79 78 76 75 74 73 72 71 70 69 68 67
TSS TSCK TSI TSO RA0 RA1 RA2 RA3 DVdd DVss IOVss IOVdd RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3
65
77
66
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 33
64 63 62 61 60 59 58 57 56 55 54
IP2022/PQ80-120 or IP2022/PQ80-160
53 52 51 50 49 48 47 46 45 44 43 42 41
RG3 RG2 RG1 RG0 RF7 RF6 RF5 RF4 DVdd DVss IOVss IOVdd RF3 RF2 RF1 RF0 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
RC4 RC5 RC6 RC7 RD0 RD1 DVdd DVss IOVss IOVdd RD2 RD3 RD4 RD5 RD6 RD7
6
515-001b.eps
Figure 2-1 IP2022 PQFP Pin Definition (Top View)
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IP2012 / IP2022 Data Sheet
2.2
PQFP (Plastic Quad Flat Package) for IP2012
RST OSC2 OSC1 XVss XVdd RTCLK2 RTCLK1 DVss DVdd AVss AVdd RG7 RG6 RG5 RG4 GVdd
80 79 78 76 75 74 73 72 71 70 69 68 67
TSS TSCK TSI TSO RA0 RA1 RA2 RA3 DVdd DVss IOVss IOVdd RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3
65
77
66
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 33
64 63 62 61 60 59 58 57 56 55 54
IP2012/PQ80-120
53 52 51 50 49 48 47 46 45 44 43 42 41
RG3 RG2 RG1 RG0 RF7 RF6 RF5 RF4 DVdd DVss IOVss IOVdd RF3 RF2 NC NC RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
RC4 RC5 RC6 RC7 NC NC DVdd DVss IOVss IOVdd RD2 RD3 RD4 RD5 RD6 RD7 Figure 2-2 IP2012 PQFP Pin Definition (Top View)
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IP2012 / IP2022 Data Sheet
2.3
BGA (Micro Ball Grid Array Package) IP2022-120 Only
IP2022/BG80-120
1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K
TOP VIEW
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
BOTTOM VIEW (ball side)
515-092b.eps
Refer to Section 2.4 for signal names. Figure 2-3 BGA Pin Definition
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IP2012 / IP2022 Data Sheet
2.4
Signal Descriptions -- IP2022
I = Digital Input, AI = Analog Input, O/DO = Digital Output, HiZ = High Impedance, P = Power, PLP = On-Chip Pullup, ST = Schmitt Trigger Table 2-1 Signal Descriptions Pin Name AVDD AVSS DVDD DVSS GVDD IOVDD IOVSS XVDD XVSS OSC1 OSC2 RST RTCLK1 RTCLK2 TSS TSCK TSI TSO RA0 RA1 RA2 RA3 RB0 RB1 RB2 PQFP 70 71 9, 31, 56, 72 10, 32, 55, 73 65 12, 34, 53 11, 33, 54 76 77 78 79 80 74 75 1 2 3 4 5 6 7 8 13 14 15 BGA B6 A6 D1,D6, E9,G5 E1,K5, E10,D5 A8 E5,G6, E6 E2,K6, E7 A4 D4 B4 A3 A2 A5 B5 A1 C2 B1 B2 D2 C1 B3 E4 F5 F1 F2 Type P P P P P P P P P I/ST O/HiZ I/ST/ PLP I O/HiZ I/ST/ PLP I/ST/ PLP I/ST /PLP O/HiZ I/O I/O I/O I/O I/O I/O I/O 24 mA 24 mA 24 mA 24 mA 8 mA 8 mA 8 mA 24 mA 24 mA 24 mA 24 mA 8 mA 8 mA 8 mA Sink @ 3.3V IOVDD Source @ 3.3V IOVDD Analog Supply Analog Ground Logic Supply Logic Ground I/O Port G supply I/O Supply (except Port G) I/O Ground (all ports) PLL Supply PLL Ground Clock/Crystal Input Crystal Output (tri-state if FUSE0 bit 15 = 1) Reset Input. There is a weak pull-up on this pin, but floating this pin does not guarantee Vih. Real-Time Clock/Crystal Input Real-Time Crystal Output (tri-state if FUSE0 bit 14 = 1) Target SPI Slave Select (used only for in-system programming and debug) Target SPI Clock (used only for in-system programming and debug) Target SPI Serial Data Input (used only for in-system programming and debug) Target SPI Serial Data output (used only for in-system programming and debug; high Z unless TSS low) I/O Port, High Power Output, Timer 1 Capture 1 Input I/O Port, High Power Output, Timer 1 Capture 2 Input I/O Port, High Power Output, Timer 1 Clock Input I/O Port, High Power Output, Timer 1 Output I/O Port, External Interrupt, Timer 2 Capture 1 Input I/O Port, External Interrupt, Timer 2 Capture 2 Input I/O Port, External Interrupt, Timer 2 Clock Input Function
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IP2012 / IP2022 Data Sheet
Table 2-1 Signal Descriptions (continued) Pin Name RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 PQFP 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 35 36 37 38 39 40 41 BGA G1 F4 J3 G2 H1 J2 H2 J1 K1 K2 K3 J4 K4 G4 J5 J6 G7 K7 J7 K8 K9 K10 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Sink @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA Source @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA Function I/O Port, External Interrupt, Timer 2 Output I/O Port, External Interrupt, External Memory WR I/O Port, External Interrupt, Parallel Slave Peripheral HOLD, External Memory RD I/O Port, External Interrupt, Parallel Slave Peripheral R/W, External Memory LE I/O Port, External Interrupt, Parallel Slave Peripheral CS, External Memory A0 I/O Port, Parallel Slave Peripheral Data D8, External Memory A9 I/O Port, Parallel Slave Peripheral Data D9, External Memory A10 I/O Port, Parallel Slave Peripheral Data D10, External Memory A11 I/O Port, Parallel Slave Peripheral Data D11, External Memory A12 I/O Port, Parallel Slave Peripheral Data D12, External Memory A13 I/O Port, Parallel Slave Peripheral Data D13, External Memory A14 I/O Port, Parallel Slave Peripheral Data D14, External Memory A15 I/O Port, Parallel Slave Peripheral Data D15, External Memory A16 I/O Port, Parallel Slave Peripheral Data D0, External Memory shared A1/D0 I/O Port, Parallel Slave Peripheral Data D1, External Memory shared A2/D1 I/O Port, Parallel Slave Peripheral Data D2, External Memory shared A3/D2 I/O Port, Parallel Slave Peripheral Data D3, External Memory shared A4/D3 I/O Port, Parallel Slave Peripheral Data D4, External Memory shared A5/D4 I/O Port, Parallel Slave Peripheral Data D5, External Memory shared A6/D5 I/O Port, Parallel Slave Peripheral Data D6, External Memory shared A7/D6 I/O Port, Parallel Slave Peripheral Data D7, External Memory shared A8/D7 I/O Port, S1CLK - SCLK (SPI), RxCLK (GPSI), optional SERDES clock input for UART or USB.
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IP2012 / IP2022 Data Sheet
Table 2-1 Signal Descriptions (continued) Pin Name RE1 RE2 RE3 RE4 RE5 PQFP 42 43 44 45 46 BGA H9 J10 J9 H10 G9 Type I/O I/O I/O I/O I/O Sink @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 24 mA Source @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 24 mA Function I/O Port, S1RXP - VP (USB), SS (SPI Slave), TxEN (GPSI Master), RxEN (GPSI Slave) I/O Port, S1RXM - VM (USB) I/O Port, S1RXD - RCV (USB), RXD (UART), DI (SPI), TxD (GPSI Master), RxD (GPSI Slave) I/O Port, S1TXPE/S1OE - TxD+ (Ethernet), OE (USB), RxEN (GPSI Master), TxEN (GPSI Slave) I/O Port, High Power Output, S1TXP - Tx+ (Ethernet), VPO (USB), TXD (UART), DO (SPI), RxD (GPSI Master), TxD (GPSI Slave) I/O Port, High Power Output, S1TXM - Tx- (Ethernet), VMO (USB), TxCLK/RxCLK (GPSI Master), TxCLK (GPSI Slave) I/O Port, S1TXME - TxD- (Ethernet), TxBUSY (GPSI) I/O Port, S2TXPE/S2OE - TxD+ (Ethernet), OE (USB), RxEN (GPSI Master), TxEN (GPSI Slave) I/O Port, High Power Output, S2TXP - Tx+ (Ethernet), VPO (USB), TXD (UART), DO (SPI), RxD (GPSI Master), TxD (GPSI Slave) I/O Port, High Power Output, S2TXM - Tx- (Ethernet), VMO (USB), TxCLK/RxCLK (GPSI Master), TxCLK (GPSI Slave) I/O Port, S2TXME - TxD- (Ethernet), TxBUSY (GPSI) I/O Port, S2CLK - SCLK (SPI), RxCLK (GPSI), optional SERDES clock input for UART or USB. I/O Port, S2RXP - VP (USB), SS (SPI Slave), TxEN (GPSI Master), RxEN (GPSI Slave) I/O Port, S2RXM - VM (USB) I/O Port, S2RXD - RCV (USB), RXD (UART), DI (SPI), TxD (GPSI Master), RxD (GPSI Slave) Output Port, ADC0 Input, Comparator Output Output Port, ADC1 Input, Comparator - Input Output Port, ADC2 Input, Comparator + Input Output Port, ADC3 Input, ADC reference Input Output Port, ADC4 Input, S1RXOutput Port, ADC5 Input, S1RX+ Output Port, ADC6 Input, S2RXOutput Port, ADC7 Input, S2RX+
RE6
47
G10
I/O
24 mA
24 mA
RE7 RF0 RF1
48 49 50
J8 F7 F9
I/O I/O I/O
8 mA 8 mA 24 mA
8 mA 8 mA 24 mA
RF2
51
F10
I/O
24 mA
24 mA
RF3 RF4 RF5 RF6 RF7 RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7
52 57 58 59 60 61 62 63 64 66 67 68 69
F6 B9 A9 D10 D9 C10 C9 B10 A10 B7 B8 A7 D7
I/O I/O I/O I/O I/O AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO
8 mA 8 mA 8 mA 8 mA 8 mA 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA*
8 mA 8 mA 8 mA 8 mA 8 mA 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA*
* GVDD = 2.5V
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IP2012 / IP2022 Data Sheet
2.5
Signal Descriptions -- IP2012
I = Digital Input, AI = Analog Input, O/DO = Digital Output, HiZ = High Impedance, P = Power, PLP = On-Chip Pullup, ST = Schmitt Trigger Table 2-2 Signal Descriptions Pin Name AVDD AVSS DVDD DVSS GVDD IOVDD IOVSS XVDD XVSS OSC1 OSC2 RST RTCLK1 RTCLK2 TSS TSCK TSI TSO RA0 RA1 RA2 RA3 RB0 RB1 RB2 PQFP 70 71 9, 31, 56, 72 10, 32, 55, 73 65 12, 34, 53 11, 33, 54 76 77 78 79 80 74 75 1 2 3 4 5 6 7 8 13 14 15 BGA B6 A6 D1,D6, E9,G5 E1,K5, E10,D5 A8 E5,G6, E6 E2,K6, E7 A4 D4 B4 A3 A2 A5 B5 A1 C2 B1 B2 D2 C1 B3 E4 F5 F1 F2 Type P P P P P P P P P I/ST O/HiZ I/ST/ PLP I O/HiZ I/ST/ PLP I/ST/ PLP I/ST /PLP O/HiZ I/O I/O I/O I/O I/O I/O I/O 24 mA 24 mA 24 mA 24 mA 8 mA 8 mA 8 mA 24 mA 24 mA 24 mA 24 mA 8 mA 8 mA 8 mA Sink @ 3.3V IOVDD Source @ 3.3V IOVDD Analog Supply Analog Ground Logic Supply Logic Ground I/O Port G supply I/O Supply (except Port G) I/O Ground (all ports) PLL Supply PLL Ground Clock/Crystal Input Crystal Output (tri-state if FUSE0 bit 15 = 1) Reset Input. There is a weak pull-up on this pin, but floating this pin does not guarantee Vih. Real-Time Clock/Crystal Input Real-Time Crystal Output (tri-state if FUSE0 bit 14 = 1) Target SPI Slave Select (used only for in-system programming and debug) Target SPI Clock (used only for in-system programming and debug) Target SPI Serial Data Input (used only for in-system programming and debug) Target SPI Serial Data output (used only for in-system programming and debug; high Z unless TSS low) I/O Port, High Power Output, Timer 1 Capture 1 Input I/O Port, High Power Output, Timer 1 Capture 2 Input I/O Port, High Power Output, Timer 1 Clock Input I/O Port, High Power Output, Timer 1 Output I/O Port, External Interrupt, Timer 2 Capture 1 Input I/O Port, External Interrupt, Timer 2 Capture 2 Input I/O Port, External Interrupt, Timer 2 Clock Input Function
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IP2012 / IP2022 Data Sheet
Table 2-2 Signal Descriptions (continued) Pin Name RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 RE4 RE5 PQFP 16 17 18 19 20 21 22 23 24 25 26 27 28 35 36 37 38 39 40 41 42 43 44 45 46 BGA G1 F4 J3 G2 H1 J2 H2 J1 K1 K2 K3 J4 K4 J6 G7 K7 J7 K8 K9 K10 H9 J10 J9 H10 G9 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Sink @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA 8 mA 8 mA 8 mA 8 mA 24 mA Source @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA 8 mA 8 mA 8 mA 8 mA 24 mA Function I/O Port, External Interrupt, Timer 2 Output I/O Port, External Interrupt I/O Port, External Interrupt, Parallel Slave Peripheral HOLD I/O Port, External Interrupt, Parallel Slave Peripheral R/W I/O Port, External Interrupt, Parallel Slave Peripheral CS I/O Port, Parallel Slave Peripheral Data D8 I/O Port, Parallel Slave Peripheral Data D9 I/O Port, Parallel Slave Peripheral Data D10 I/O Port, Parallel Slave Peripheral Data D11 I/O Port, Parallel Slave Peripheral Data D12 I/O Port, Parallel Slave Peripheral Data D13 I/O Port, Parallel Slave Peripheral Data D14 I/O Port, Parallel Slave Peripheral Data D15 I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port, S1CLK - SCLK (SPI), RxCLK (GPSI), optional SERDES clock input for UART or USB. I/O Port, S1RXP - VP (USB), SS (SPI Slave), TxEN (GPSI Master), RxEN (GPSI Slave) I/O Port, S1RXM - VM (USB) I/O Port, S1RXD - RCV (USB), RXD (UART), DI (SPI), TxD (GPSI Master), RxD (GPSI Slave) I/O Port, S1TXPE/S1OE - TxD+ (Ethernet), OE (USB), RxEN (GPSI Master), TxEN (GPSI Slave) I/O Port, High Power Output, S1TXP - Tx+ (Ethernet), VPO (USB), TXD (UART), DO (SPI), RxD (GPSI Master), TxD (GPSI Slave) I/O Port, High Power Output, S1TXM - Tx- (Ethernet), VMO (USB), TxCLK/RxCLK (GPSI Master), TxCLK (GPSI Slave) I/O Port, S1TXME - TxD- (Ethernet), TxBUSY (GPSI) I/O Port, High Power Output
RE6
47
G10
I/O
24 mA
24 mA
RE7 RF2
48 51
J8 F10
I/O I/O
8 mA 24 mA
8 mA 24 mA
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IP2012 / IP2022 Data Sheet
Table 2-2 Signal Descriptions (continued) Pin Name RF3 RF4 RF5 RF6 RF7 RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7 PQFP 52 57 58 59 60 61 62 63 64 66 67 68 69 BGA F6 B9 A9 D10 D9 C10 C9 B10 A10 B7 B8 A7 D7 Type I/O I/O I/O I/O I/O AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO AI/DO Sink @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* Source @ 3.3V IOVDD 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* 4 mA* I/O Port I/O Port I/O Port I/O Port I/O Port Output Port, ADC0 Input, Comparator Output Output Port, ADC1 Input, Comparator - Input Output Port, ADC2 Input, Comparator + Input Output Port, ADC3 Input, ADC reference Input Output Port, ADC4 Input, S1RXOutput Port, ADC5 Input, S1RX+ Output Port, ADC6 Input Output Port, ADC7 Input Function
* GVDD = 2.5V
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IP2012 / IP2022 Data Sheet
3.0
System Architecture
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Timer 1 (T1)
Edge Det.
Parallel Timer 2 8/16-bit Slave (T2) Peripheral
Timer 0 (T0)
Ext. Memory Interface Interrupt
(2) Serializer/ Deserializers SxCLK
ADC
Analog Comparator, 2x Ethernet Squelch
Internal Data Bus CPU Core Clock Reset Brown Out POR RST Internal RC Clock Watchdog Timer with Pre-Scaler ISD (4) LFSR Units Writeback Execute Decode Fetch W ALU Real-Time Timer RTCLK Divider Multiplexer Divider PLL Divider System Clock Divider Multiplexer
ISP
64KB Flash Program Memory
16KB RAM Program Memory
4KB Data Memory
Real-Time Clock Driver
OSC Driver
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Figure 3-1 IP2022 Detailed Block Diagram The IP2012 / IP2022 CPUs execute from a 32K 16 flash program memory and an 8K 16 RAM program memory. Figure 3-1 shows the IP2022 detailed block diagram, and Figure 3-2 shows the IP2012 detailed block diagram. At 120 MHz operation, the maximum execution rate is 40 MIPS from Flash and 120 MIPS from RAM. At 160 MHz operation, the maximum execution rate is 53.33 MIPS from Flash and 160 MIPS from RAM. Speed-critical routines can be copied from the flash memory to the RAM for faster execution. The CPU operates on 8-bit data in 128 special-purpose registers, 128 global registers, and 3840 bytes of data memory. The special-purpose registers hold control and status bits used for CPU control and for interface with hardware peripherals (timers, I/O ports, A/D converter, etc.)Although the philosophy followed in the design of Ubicom products emphasizes the use of fast RISC CPUs with predictable execution times to emulate peripheral devices in software (the ipModuleTM concept), there are a few hardware peripherals which are difficult to emulate in software alone (e.g. an A/D converter) or consume an excessive number of instruction cycles when operating at high speed (e.g. data serialization/deserialization). The design of the IP2012 / IP2022 incorporates only those hardware peripherals which can greatly accelerate or extend the reach of the ipModuleTM concept. The hardware peripherals included on-chip are:
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* * * * * * * * * * *
52 I/O port pins (48 on IP2012) Watchdog timer Real-time timer 2 Multifunction 16-bit timers with compare and capture registers 2 Real-time 8-bit timers 2 Serializer/deserializer (SERDES) units (IP2012 has one unit) 4 Linear feedback shift register (LFSR) units 10-bit, 8-channel A/D converter Analog comparator Parallel slave peripheral interface External SRAM interface (IP2022 only)
There is a single interrupt vector which can be reprogrammed by software. On-chip peripherals and up to 8 external inputs can raise interrupts. There are five sources of reset: * RST external reset input * Power-On Reset (POR) logic * Brown-Out Reset (BOR) logic (detects low AVdd condition) * Watchdog timer reset * In-system debugging/programming interface reset An on-chip PLL clock multiplier (x50) enables high-speed operation (up to 160 MHz) from a slow-speed external
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IP2012 / IP2022 Data Sheet
clock input or crystal. A CPU clock-throttling mechanism allows fine control over power consumption in modes that do not require maximum speed, such as waiting for an interrupt. The IP200 series has a mechanism for in-system programming of its flash and RAM program memories through a four-wire SPI interface. This provides easy programming and reprogramming of devices on
assembled circuit boards. In addition, the flash memory can be programmed by software at run time, for example to store user-specific data such as phone numbers and to receive software upgrades downloaded over the Internet. The devices also have an on-chip debugging facility which makes the internal operation of the chip visible to thirdparty debugging tools.
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Timer 1 (T1)
Edge Det.
Timer 2 (T2)
Parallel 8-bit Slave Peripheral
Timer 0 (T0) Interrupt Internal Data Bus
(1) Serializer/ Deserializer SxCLK
ADC
Analog Comparator, 2x Ethernet Squelch
CPU Core Clock Reset Brown Out POR RST Internal RC Clock Watchdog Timer with Pre-Scaler ISD (4) LFSR Units Writeback Execute Decode Fetch W ALU Real-Time Timer RTCLK Divider Multiplexer Divider PLL Divider System Clock Divider Multiplexer
ISP
64KB Flash Program Memory
16KB RAM Program Memory
4KB Data Memory
Real-Time Clock Driver
OSC Driver
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Figure 3-2 IP2012 Detailed Block Diagram
3.1
CPU Registers
Figure 3-3 shows the CPU registers, which consist of seven 8-bit registers, seven 16-bit registers, and one 24bit register. The 16-bit registers are formed from pairs of 8-bit registers, and the 24-bit register is formed from three 8-bit registers. For the register quick reference guide, see Section 7.0 and Section 7.1. The W or working register is used as the source or destination for most arithmetic, movement, and logical instructions. The STATUS register holds the condition flags for the results of arithmetic and logical operations, the page bits (used for jumps and subroutine calls), and bits which indicate the skipping state of the core and control of continuation skip after return from interrupt. Figure 3-4 shows the assignment of the bits in the STATUS register.
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IP2012 / IP2022 Data Sheet
7 W Register
0
*
STATUS Register MULH Register SPDREG Register INTSPD Register 15 XCFG Register PCH/PCL Register 15 Interrupt Registers IPCH/IPCL Register * INTVECH/INTVECL Register * 15 Pointer Registers IPH/IPL Register DPH/DPL Register SPH/SPL Register Program Memory/External Memory Interface Registers 7 15 23 0 0
*
*
choose either to clear the SSF flag in the ISR or to make the first instruction of the context switching code a nop to flush out the skip state. Z--Zero bit. Affected by most logical, arithmetic, and data movement instructions. Set if the result was zero, otherwise cleared. DC--Digit Carry bit. After addition, set if carry from bit 3 occurred, otherwise cleared. After subtraction, cleared if borrow from bit 3 occurred, otherwise set. C--Carry bit. After addition, set if carry from bit 7 of the result occurred, otherwise cleared. After subtraction, cleared if borrow from bit 7 of the result occurred, otherwise set. After rotate (rr or rl) instructions, loaded with the LSB or MSB of the operand, respectively.
The MULH register receives the upper 8 bits of the 16-bit product from signed or unsigned multiplication. The lower 8 bits are loaded into the W register. The SPDREG register holds bits that control the CPU speed and clock source settings, and is loaded by using the speed instruction, as shown in Figure 3-5. The SPDREG register is read-only, and its contents may only be changed by executing a speed instruction, taking an interrupt, or returning from an interrupt. For more information about the speed instruction and the clock throttling mechanism, see Section 3.4 and Figure 3-17. Note: The speed instruction should be followed by a nop instruction if Port B interrupt is used to wake up from sleep mode.
0
ADDRSEL Register DATAH/DATAL Register *
ADDRX/ADDRH/ADDRL Register * Low byte doesn't carry to high byte
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Figure 3-3 CPU Registers 7 PLL . 7 6 PA2:0 5 4 SAR 3 SSF 2 Z 1 DC 0 C * 6 OSC 5 4 3 CDIV3:0 0 CLK1:0
Figure 3-5 SPDREG Register PLL--enable x50 PLL clock multiplier; 0 = enabled; 1 = disabled. Power consumption can be reduced by disabling it. See Figure 3-17. OSC--enable OSC oscillator; 0 = enabled; 1 = disabled (stops OSC oscillator and blocks propagation of OSC1 external clock input). Power consumption can be reduced by disabling it. CLK1:0--selects the system clock source, as shown in Table 3-1. See Figure 3-17 for the clock logic. See Section 7.1.5 (FCFG register, FRDTS1:0 bits) for exceptions.
Figure 3-4 STATUS Register * PA2:PA0--Program memory page select bits. Used to extend the 13-bit address encoded in jump and call instructions (selects 8K-word pages). Modified using the page instruction. SAR--Skip After Return bit. This bit should be set if the core should be in the skipping state, and should not be set if the core should not be in the skipping state after the completion of the return instruction (ret, retnp, or retw instructions, but not reti). The return instruction will also clear the SAR control bit to ensure correct behavior after the dynamic jump. SSF--Shadowed Skipping/not state Flag. Gives the ISR the ability to know if the interrupt occurred immediately following a skip instruction. The software can
*
*
*
*
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IP2012 / IP2022 Data Sheet
Table 3-1 CLK1:0 Field Encoding CLK1:0 00 01 10 11 * System Clock Source PLL Clock Multiplier OSC Oscillator/External OSC1 Input RTCLK oscillator/external clock on RTCLK1 input System Clock Off
The XCFG register holds additional control and status bits, as shown in Figure 3-6. 7 6 5 4 3 21 0
GIE FWP RTEOS RTOSC_EN INT_EN Rsvd FBUSY Figure 3-6 XCFG Register * GIE--global interrupt enable bit. When set, interrupts are enabled. When clear, interrupts are disabled. For more information about interrupt processing, see Section 3.7. FWP--flash write protect bit. When clear, writes to flash memory are ignored. For more information about programming the flash memory, see Section 4.7. RTEOS--real-time timer oversampling enable bit. When set, oversampling is used. For more information, see Section 5.3. RTOSC_EN--RTCLK oscillator enable bit. When clear, the RTCLK oscillator is operational. When set, the RTCLK oscillator is turned off. INT_EN--int instruction interrupt enable bit. When set, int instructions cause interrupts. When clear, int instructions only increment the PC, like nop. FBUSY--read-only flash memory busy bit. Set while fetching instructions out of flash memory or while busy processing an iread, ireadi, iwrite, iwritei, fwrite, fread or ferase instruction that operates on Flash, otherwise clear. For more information about programming the flash memory, see Section 4.7.
CDIV3:0--selects the clock divisor used to generate the CPU core clock from the system clock, as shown in Table 3-2 (also see Figure 3-17). Table 3-2 System Clock Divisor CDIV3:0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 System Clock Divisor 1 2 3 4 5 6 8 10 12 16 24 32 48 64 128 Clock Off CPU Core Frequency 120 MHz System Clock 120 MHz 60 MHz 40 MHz 30 MHz 24 MHz 20 MHz 15 MHz 12 MHz 10 MHz 7.5 MHz 5 MHz 3.75 MHz 2.5 MHz 1.875 MHz 0.9375 MHz 0 MHz 160 MHz System Clock 160 MHz 80 MHz 53.33 MHz 40 MHz 32 MHz 26.66 MHz 20 MHz 16 MHz 13.33 MHz 10 MHz 6.66 MHz 5 MHz 3.33 MHz 2.5 MHz 1.25 MHz 0 MHz
*
*
*
*
*
The PCH and PCL register pair form a 16-bit program counter. The PCH register is read-only. The PCL register can be used to implement a lookup table, by moving a variable to the w register, then executing an add PCL,w instruction. If w=01 when the add occurs, the instruction after the add will be skipped; if w=02, two instructions will be skipped, etc. The IPCH and IPCL register pair specifies the return address when a reti instruction is executed. The INTVECH and INTVECL register pair specifies the interrupt vector. It has a default value of 0 following reset. On a return from interrupt, an option of the reti instruction allows software to save the incremented value of the program counter in the INTVECH and INTVECL registers. The IPH and IPL register pair is used as a pointer for indirect addressing. For more information about indirect addressing, see Section 4.1.3. The DPH and DPL register pair and the SPH and SPL register pair are used as pointer registers for indirect-withoffset addressing. For more information about indirect-
The INTSPD register holds bits that control the CPU speed and clock source during interrupt service routines (it is copied to the SPDREG register when an interrupt occurs). It has the same format as the SPDREG register. When the OSC crystal driver is stopped (SPDREG bit 6 = 1) and Port B or Real Time Timer interrupts are enabled, then INTSPD bits 5 and 4 must not both be 0, because the crystal startup time plus PLL startup time may be greater than WUDP2:0 (see Figure 3-17).
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IP2012 / IP2022 Data Sheet
with-offset addressing, see Section 4.1.4. The SPH and SPL registers are automatically post-decremented when storing to memory with a push instruction, and they are automatically pre-incremented when reading from memory with a pop instruction. The ADDRSEL register holds an index to one of eight 24bit pointers used to address program memory. The current program memory/external memory 24-bit address selected by the ADDRSEL register is accessible in the ADDRX (bits 23:16), ADDRH (bits 15:8), and ADDRL (bits 7:0) registers. The upper 5-bits of the ADDRSEL register are unused. All 8 banks of 24-bits are initialized to 0x000000 upon reset. Program memory is always read or written as 16-bit words. On reads, the data from program memory is loaded into the DATAH and DATAL register pair. On writes, the contents of the DATAH and DATAL register pair are loaded into the program memory.
3.3
Program Memory
Figure 3-8 is a map of the program memory. A program memory address in the INTVECH/INVECL, IPCH/IPCL, or PCH/PCL registers or on the hardware stack is a word address. However, the GNU software tools require byte addresses when referring to locations in program memory. An address loaded in the ADDRX/ADDRH/ADDL register is a byte address. The program memory is organized as 8K-word pages (16K bytes). Single-instruction jumps and subroutine calls are restricted to be within the same page. Longer jumps and calls require using a page instruction to load the upper address bits into the PA2:0 bits of the STATUS register. The page instruction must immediately precede the jump or call instruction. The PA2:0 bits should not be modified by writing directly to the STATUS register, because this may cause a mismatch between the PA2:0 bits in the STATUS register and the current program counter (see Section 3.3.2). For more information about the flash program memory, see Section 4.7 and Section 7.0.2.
3.2
Data Memory
Figure 3-7 is a map of the data memory. The specialpurpose registers and the first 128 data memory locations (between addresses 0x080 and 0x0FF) can be accessed with a direct addressing mode in which the absolute address of the operand is encoded within the instruction. The remaining 3840 bytes of data memory (between addresses 0x100 and 0xFFF) must be accessed using indirect or indirect-with-offset addressing modes. There is one 16-bit register for the indirect address pointer, and two 16-bit registers for indirect-with-offset address pointers. The offset is a 7-bit value encoded within the instruction. For more information about the addressing modes, see Section 4.1.
7 0x001 0x07F 0x080 0x0FF 0x100 127 Special-Purpose Registers 128 Global Registers 0
Word Address
Byte Address
15 Program RAM Reserved (undefined data)
0
0x0000 0x000000 0x1FFF 0x003FFE 0x2000 0x004000
0x7FFF 0x00FFFE 0x8000 0x010000 0x9FFF 0x013FFE 0xA000 0x014000 0xBFFF 0x017FFE 0xC000 0x018000 0xDFFF 0x01BFFE 0xE000 0x01C000 0xFFFF 0x01FFFE
Flash Program Memory Flash Program Memory Flash Program Memory Flash Program Memory
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Figure 3-8 Program Memory Map External memory is not shown in Figure 3-8 because the CPU cannot execute instructions directly out of external memory. For more information about external memory, see Section 5.11.
3840 Bytes Data Memory
3.3.1
Loading the Program RAM
0xFFF
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Figure 3-7 Data Memory Map
Software loads the program RAM from program flash iread/ireadi and memory using the iwrite/iwritei instructions. The iread instruction reads the 16-bit word specified by the address held in the ADDRX/ADDRH/ADDRL register. This word can be in program flash memory, program RAM, or external memory. When the iread instruction is executed, bits
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15:8 of the word are loaded into the DATAH register, and bits 7:0 are loaded into the DATAL register. The address is a word-aligned byte address (i.e. an address that is zero in its LSB). The ireadi instruction is identical to the iread instruction, except that it also increments the address by 2. The iwrite instruction writes the 16-bit word held in the DATAH/DATAL registers to the program RAM location specified by the address held in the ADDRX/ADDRH/ADDRL register. The iwritei instruction is identical, except that it also increments the address by 2. For more information about the iread/ireadi and iwrite/iwritei instructions, see Section 4.7.
For maximum power savings when running from the OSC clock, disable the RTCLK oscillator (RTOSC_EN bit in the XCFG register), disable the watchdog timer (WDTE bit in the FUSE1 register), disable the A/D converter (ADCGO bit in the ADCCFG register, disable the analog comparator (CMPEN bit in the CMPCFG register) and check that no flash operation is in progress (FBUSY bit in the XCFG register) before executing a speed #$FF instruction. To summarize settings for lowest power: * * * * * XCFG bit 4 = 1 FUSE1 bit 3 = 0 CMPCFG bit 7 = 0 ADCCFG bit 3 = 0 XCFG bit 0 = 0
3.3.2
Program Counter
The program counter holds the 16-bit address of the instruction to be executed. The lower eight bits of the program counter are held in the PCL register, and the upper eight bits are held in the PCH register. A write to the PCL register will cause a jump to the 16-bit address specified by the PCH and PCL registers. If the PCL register is written as the destination of an add or addc instruction and carry occurs, the PCH register is automatically incremented. (This may cause a mismatch between the PA2:0 bits in the STATUS register and the current program counter, therefore it is strongly recommended that direct modification of the PCL register is only used for jumps within a page.) The PCH register is read-only. The PA2:0 bits in the STATUS register are not used for address generation, except when a jump or subroutine call instruction is executed. However, when an interrupt is taken, the PA2:0 bits are automatically updated with the upper three bits of the interrupt vector (INTVECH/L). These bits are restored from the STATUS shadow register when the interrupt service routine returns (i.e. executes a reti instruction).
Note: Before executing the speed instruction or executing an interrupt (an interrupt will cause INTSPD to be copied to SPDREG), insure that the FCFG register has appropriate settings for the new clock frequency. The SPDREG register (see Figure 3-5) holds the current settings for the clock divisor, clock source, and disable bits. These settings can be explicitly changed by executing a speed instruction, and they change automatically on interrupts. The SPDREG register is readonly, and its contents may only be changed by executing a speed instruction, taking an interrupt, or returning from an interrupt. Two consecutive speed instructions are not allowed. The INTSPD register specifies the settings used during execution of the interrupt service routine. The INTSPD register is both readable and writable. On return from interrupts, the reti instruction includes a bit that specifies whether the pre-interrupt speed is restored or the current speed is maintained (see Table 35). The actual speed of the CPU is indicated by the SPDREG register unless the specified speed is faster than the flash access time and the program is executing out of flash. When program execution moves from program RAM to program flash memory, the new clock divisor will be the greater (slower) of the clock divisor indicated by the SPDREG register and the clock divisor required to avoid violating the flash memory access time. The SPDREG register does not indicate if the flash clock divisor is being used. The speed indicated by the SPDREG will be overridden only if the speed is too fast for the flash memory. The FCFG register holds bits that specify the minimum number of system clock cycles for each flash memory cycle (see Section 4.7.1).
3.4
Low Power Support
Software can change the execution speed of the CPU to reduce power consumption. A mechanism is also provided for automatically changing the speed on entry and return from the interrupt service routine. The speed instruction specifies power-saving modes that include a clock divisor between 1 and 128. This divisor only affects the clock to the CPU core, not the timers, SERDES, external memory or ADC (see Figure 3-17). The speed instruction also specifies the clock source (OSC clock, RTCLK oscillator, or PLL clock multiplier) and whether to disable the OSC clock oscillator or the PLL.
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3.4.1
Clock Stop Mode (SLEEP)
When a speed instruction occurs, it is possible for the CPU clock source to be disabled. The clock to the CPU core may be disabled while the system clock is left running, or the system clock may be disabled which also disables the CPU core clock. See SPDREG, Section 7.1.18.
The automatic speed changes require a certain amount of delay to take effect (see Figure 3-5 and Figure 3-17): * Changing the Core Clock Divisor--there is no delay when the clock divisor is changed (the instruction after the speed instruction is executed at the new speed). Changing the System Clock Source--the delay is up to one cycle of the slower clock. For example, changing between 4 MHz and 120 MHz could require up to 0.25 microseconds. Turning on the OSC Clock Oscillator (clearing the OSC bit in the SPDREG register)--the system clock suspend time is specified in the WUDX2:0 bits in the FUSE0 register (see Section 3.10.1). Turning on the PLL Clock Multiplier (clearing the PLL bit in the SPDREG register)--the system clock suspend time is specified in the WUDP2:0 bits in the FUSE0 register.
*
3.4.2
Wakeup
*
Recovery from SLEEP (core clock stop) mode to normal execution is possible from these sources: * * * * * External interrupts (i.e. Port B interrupts) Real-time timer interrupts Watchdog timer overflow reset Brown-out voltage reset RST external reset
*
The first two sources listed do not reset the chip, so register and CPU states are maintained. The last three sources reset the chip, so software must perform all of its reset initialization tasks to recover. This usually requires additional time, as compared to recovery through an interrupt. If a Port B or Real Time Timer interrupt occurs during core clock stop mode, the INTSPD register will be copied to the SPDREG register, the ISR will be executed, then mainline code will resume execution at the instruction after the speed command that caused the clock to stop. Note: If wakeup triggers an ISR that has a reti instruction which reinstates the pre-interrupt speed (see Table 3-5), the device goes back to sleep. If a subsequent wakeup occurs which does not reinstate the pre-interrupt speed, then a nop must be inserted after the speed instruction which puts it to sleep.
If both the OSC oscillator and PLL are re-enabled simultaneously, the delay is controlled by only the WUDP2:0 bits. Bits in the FUSE0 register are flash memory cells which cannot be changed dynamically during program execution.
3.6
Instruction Timing
All instructions that perform branches take 3 cycles to complete, consisting of 1 cycle to execute and 2 cycles to load the pipeline. Table 3-3 Branch Timing Instruction Execution Time 1 1 1 1 Pipeline Load Time 2 2 2 2
jmp call ret reti
3.5
Speed Change
The speed instruction executes using the current clock divisor. The new clock divisor takes effect with the following instruction, as shown in the following code example.
nop speed #0x06 nop speed #0x00 nop ;assume divisor is 4, so this ;instruction takes 4 cycles ;change the divisor to 8, ;instruction takes 4 cycles ;instruction takes 8 cycles ;change the divisor to 1, ;instruction takes 8 cycles ;instruction takes 1 cycle
In the case of an automatic speed change, the execution time will be with respect to the original speed and the pipeline load time will be with respect to the new speed. Conditional branching is implemented in the IP2012 / IP2022 by using conditional skip instructions to branch over an unconditional jump instruction. To support conditional branching to other pages, the conditional skip instructions will skip over two instructions if the first instruction is a page instruction. The loadh and loadl instructions also cause an additional instruction to be skipped. When any of these conditions occur, it is called an extended skip instruction.
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Skip instructions take 1 cycle if they do not skip, or 2 cycles if they skip over one instruction. An extended skip instruction may skip over more than one loadh, loadl, or page instruction, however this operation is interruptible and does not affect interrupt latency. The iread and iwrite instructions take 4 cycles. The multiply instructions take 1 cycle.
3.7.1
Interrupt Processing
3.7
*
Interrupt Support
On-Chip Peripherals-the serializer/deserializer units, real-time timer, timer 0, timer 1, and timer 2 are capable of generating interrupts. The Parallel Slave Peripheral does not generate interrupts on its own; it requires programming one of the Port B external interrupt inputs to generate interrupts on its behalf. External Interrupts-the eight pins on Port B can be programmed to generate interrupts on either rising or falling edges (see Section 5.1.1). int Instruction-the int instruction can be executed by software to generate an interrupt. The INT_EN bit can be considered as the interrupt flag for the int instruction, if the ISR checks for interrupt source. The INT_EN bit in the XCFG register must be set to enable the int instruction to trigger an interrupt. Because the reti instruction returns to the int instruction, the INT_EN bit must be cleared in the interrupt service routine (ISR) before returning.
There are three types of interrupt sources:
There is one interrupt vector held in the INTVECH and INTVECL registers, which is reprogrammable by software. When an interrupt is taken, the current PC is saved in the IPCH and IPCL registers. On return from interrupt (i.e. execution of the reti instruction), the PC is restored from the IPCH and IPCL registers. Optionally, the reti instruction may also copy the incremented PC to the INTVECH and INTVECL registers before returning. This has the effect of loading the INTVECH and INTVECL registers with the address of the next instruction following the reti instruction. This option can be used to directly implement a state machine, such as a simple round-robin scheduling mechanism for a series of interrupt service routines (ISRs) in consecutive memory locations. If multiple sources of interrupts have been enabled, the ISR must check the interrupt flags of each source to determine the cause of the interrupt. The ISR must clear the interrupt flag for the source of the interrupt to prevent retriggering of the interrupt on completion of the ISR (i.e. execution of the reti instruction). Because the interrupt logic adds a 2-cycle delay between clearing an interrupt flag and deasserting the interrupt request to the CPU, the flag must be cleared at least 2 cycles before the reti instruction is taken. When an interrupt is taken, the registers shown in Figure 3-10 are copied to a shadow register set. Each shadow register is actually a 2-level push-down stack, so one level of interrupt nesting is supported in hardware. The interrupt processing mechanism is completely independent of the 16-level call/return stack used for subroutines. The contents of the DATAH and DATAL registers are pushed to their shadow registers 4 cycles after the interrupt occurs, to protect the result of any pending iread instruction. Therefore, software should not access the DATAH or DATAL registers during the first instruction of an ISR.
*
*
Figure 3-9 shows the system interrupt logic. Each interrupt source has an interrupt enable bit. To be capable of generating an interrupt, the interrupt enable bit and the global interrupt enable (GIE) bit must be set.
Port B Interrupt SerDes Interrupt Timer 0 T0IF Bit Real-Time Timer RTIF Bit Timer 1 OFIF Bit Timer 1 CAP2IF/CMP2IF Bit Timer 1 CAP1IF Bit Timer 1 CMP1IF Bit Timer 2 OFIF Bit Timer 2 CAP2IF/CMP2IF Bit Timer 2 CAP1IF Bit Timer 2 CMP1IF Bit int Instruction INT_EN Bit
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GIE Bit Interrupt to CPU
Figure 3-9 System Interrupt Logic
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INTVECH/INTVECL Register INTSPD Register
PC SPDREG Register W Register
IPCH/IPCL Register SPDREG Shadow Register 1 W Shadow Register 1 STATUS Shadow Register 1 MULH Shadow Register 1 IPH/IPL Shadow Register 1 DPH/DPL Shadow Register 1 SPH/SPL Shadow Register 1 DATAH/DATAL Shadow Register 1 GIE Shadow bit 1
IPCH/IPCL Shadow Register SPDREG Shadow Register 2 W Shadow Register 2 STATUS Shadow Register 2 MULH Shadow Register 2 IPH/IPL Shadow Register 2 DPH/DPL Shadow Register 2 SPH/SPL Shadow Register 2 DATAH/DATAL Shadow Register 2 GIE Shadow bit 2
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INTVECH bits 7:5 copied
STATUS Register MULH Register IPH/IPL Register DPH/DPL Register SPH/SPL Register DATAH/DATAL Register GIE XCFG bit 7
GIE = 0
Figure 3-10 Interrupt Processing (On Entry to the ISR) Note: On entry to the ISR the W, MULH, IPH/IPL, DPH/DPL, SPH/SPL, ADDRSEL and DATAH/DATAL register values don't change from their mainline code values (they are copied to their shadow registers).
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On return from the ISR, these registers are restored from the shadow registers, as shown in Figure 3-11.
If reti Instruction Bit 1 is Set IPCH/IPCL Shadow If reti Instruction Bit 0 is Set If reti Instruction Bit 2 is Set SPDREG Shadow Register 2 W Shadow Register 2 STATUS Shadow Register 2 MULH Shadow Register 2 IPH/IPL Shadow Register 2 DPH/DPL Shadow Register 2 SPH/SPL Shadow Register 2 DATAH/DATAL Shadow Register 2 GIE Shadow bit 2
PC + 1
INTVECH/INTVECL Register
IPCH/IPCL Register T0TMR + W
PC
T0TMR Register
SPDREG Shadow Register 1 W Shadow Register 1 STATUS Shadow Register 1 MULH Shadow Register 1 IPH/IPL Shadow Register 1 DPH/DPL Shadow Register 1 SPH/SPL Shadow Register 1 DATAH/DATAL Shadow Register 1 GIE Shadow bit 1
SPDREG Register W Register STATUS Register MULH Register IPH/IPL Register DPH/DPL Register SPH/SPL Register DATAH/DATAL Register GIE XCFG bit 7
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Figure 3-11 Interrupt Return Processing (upon execution of reti)
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3.7.2
* *
Global Interrupt Enable Bit
3.7.3
Interrupt Latency
The GIE bit serves two purposes: Preventing an interrupt in a critical section of mainline code Supporting nested interrupts
The GIE bit is automatically cleared when an interrupt occurs, to disable interrupts while the ISR is executing. The GIE bit is automatically set by the reti instruction to re-enable interrupts when the ISR returns. Table 3-4 GIE Bit Handling Event Enter ISR (interrupt) Exit ISR (reti instruction) Effect GIE bit is cleared GIE bit is set Enable interrupts for nested interrupt support Nothing, the GIE bit is already clear Enable interrupts Disable interrupts
The interrupt latency is the time from the interrupt event occurring to first ISR instruction being latched from the decode to the execute stage (see Section 4.3). If the interrupt comes from a Port B input and the SYNC bit in the FUSE1 register is 0, an additional two core clock cycles of synchronization delay are added to the interrupt latency. The ireadi or iwritei instructions are blocking (i.e. prevent other instructions and interrupts from being executed) for 4 core clock cycles. The iread or iwrite instructions are blocking for 4 core clock cycles while operating on program RAM, and non-blocking (single cycle) while operating on external memory. When an interrupt event is triggered, the CPU speed is changed to the speed specified by the INTSPD register (the SPDREG register is copied to a shadow register, then loaded with the value from the INTSPD register). If INTSPD is set the same as SPDREG when an interrupt occurs, then the interrupt latency is 3 core clock cycles for synchronous interrupts. If not, then the interrupt latency is 3 core clock cycles, plus the speed change (delay described in Section 3.5).
setb xcfg,7
instruction (inside ISR)
clrb xcfg,7
instruction (inside ISR)
setb xcfg,7
instruction (mainline code)
clrb xcfg,7
instruction (mainline code)
3.7.4
Return From Interrupt
To re-enable interrupts during ISR execution, the ISR code must first clear the source of the first interrupt. It may also be desirable to disable specific interrupts before setting the GIE bit to provide interrupt prioritization. Even with GIE deasserted, interrupt triggers are still captured but an interrupt won't be triggered until GIE is re-enabled. Caution must be taken not to exceed the interrupt shadow register stack depth of 2. Clearing the GIE bit in the ISR cannot be used to globally disable interrupts so that they remain disabled when the ISR returns, because the reti instruction automatically sets the GIE bit. To disable interrupts in the ISR so that they remain disabled after the ISR returns, the individual interrupt enable bits for each source of interrupts must be cleared.
The reti instruction word includes three bits which control its operation, as shown in Table 3-5. The three bits are specified from assembly language in a literal (e.g. reti #0x7 to specify all bits as 1). Table 3-5 reti Instruction Options Bit 2 1 Function Reinstate the pre-interrupt speed 1 = enable, 0 = disable Store the PC+1 value in the INTVECH and INTVECL registers 1 = enable, 0 = disable Add W to the T0TMR register 1 = enable, 0 = disable
0
Updating the interrupt vector allows the programmer to implement a sequential state machine. The next interrupt will resume the code directly after the previous reti instruction. The reti instruction takes 1 cycle to execute, and there is a further delay of 2 cycles at the mainline code speed to load the pipeline before the mainline code is resumed.
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Note: If RETI can return to Flash program memory, insure that all Flash reads or writes are complete (XCFG bit 0 = 0) before RETI is executed.
3.7.5
Disabled Interrupt Resources
If a peripheral is disabled and its interrupt flag is cleared, the peripheral does not have the ability to set an interrupt flag. The interrupt flag, however, is still a valid source of interrupt (If software sets an interrupt flag, the corresponding interrupt enable bit is set, and the GIE bit is set, then the CPU will be interrupted whether or not the peripheral is enabled or disabled). If a peripheral is disabled inside the ISR, then its interrupt flag must be cleared to prevent an undesired interrupt from being taken when the ISR completes or when GIE is enabled (enabling nested interrupts - see Section 3.7.2).
The IP2012 / IP2022 incorporates a Power-On Reset (POR) detector that generates an internal reset as DVdd rises during power-up. Figure 3-12 is a block diagram of the reset logic. The startup timer controls the reset timeout delay. The reset latch controls the internal reset signal. On power-up, the reset latch is cleared (CPU held in reset), and the startup timer starts counting once it detects a valid logic high signal on the RST pin. Once the startup timer reaches the end of the timeout period, the reset latch is cleared, releasing the CPU from reset. Note: CPU operation does not start until the CPU is released from reset and valid core clocks are received past the system clock suspend circuit (see WUDX block in Figure 3-17). So, for a POR with FUSE0 register WUDX=350us, for example, the core starts operation ~70ms after power up. For a POR with WUDX= 1.1sec, the core starts operation ~1.1sec after power up. The PSPCFG (address 0x06E) register contains two bits to indicate possible sources of the reset, WD and BO. The WD bit is cleared on reset unless the reset was caused by the watchdog timer, in which case the WD bit is set. The BO bit is cleared on reset unless the reset was caused by the brown-out logic, in which case, the BO bit is set. Figure 3-13 shows a power-up sequence in which RST is not tied to the DVDD pin and the DVDD signal is allowed to rise and stabilize before RST pin is brought high. The WUDX2:0 bits of the FUSE0 register specify the length of time from the rising edge of RST until the device leaves reset.
3.8
* * * * *
Reset
Power-On Reset (POR; reset occurs at power up) Brown-Out Reset (BOR) Watchdog Reset External Reset (from the RST pin) Tool Reset (from the debugging interface)
There are five sources of reset:
Each of these reset conditions causes the program counter to branch to the reset vector at the top of the program memory (word address 0xFFF0 or byte address 0x1FFE0).
For RST, Tool Reset or Watchdog = WUDX2:0 (FUSE0) For POR or BOR (1025 x 70us) 70ms Internal Time-Out Reset Signal (active low) Watchdog Start-Up RC Clock Timer (~14KHz) Core Clock Clear
FF
FF
Core Reset (active low, initially low)
DVDD AVDD RST
POR
Power-On Reset
Brown-Out Detection
Watchdog Timer Overflow Tool Reset
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Figure 3-12 On-Chip Reset Circuit Block Diagram
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DVDD RST POR WUDX Startup Timer (Time-Out) Internal Reset Signal
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DVDD rise time has the possibility of being too slow (refer to SVdd specification in Section 8.4).
DVDD
R2 R1 RST C1
IP2022
Figure 3-13 Power-Up, Separate RST Signal Figure 3-14 shows the on-chip Power-On Reset sequence in which the RST and DVDD pins are tied together. The DVDD signal is stable before the startup timer expires. In this case, the CPU receives a reliable reset.
DVDD RST POR Startup Timer (Time-Out) Internal Reset Signal
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Figure 3-16 External Reset Circuit The diode D discharges the capacitor when DVDD is powered down. R1 = 100 to 1K will limit any current flowing into RST from external capacitor C1. This protects the RST pin from breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
70ms
R2 < 40K is recommended to make sure that voltage drop across R2 leaves the RST pin above a Vih level. C1 should be chosen so that R2 C1 exceeds five times the time period required for DVDD to reach a valid operating voltage.
Figure 3-14 Power-On Reset, RST Tied To DVdd However, Figure 3-15 depicts a situation in which DVDD rises too slowly. In this scenario, the startup timer will time out prior to DVDD reaching a valid operating voltage level (DVDD min). This means the CPU will come out of reset and start operating with the supply voltage below the level required for reliable performance. In this situation, an external RC circuit is recommended for driving RST. The RC delay should exceed five times the time period required for DVDD to reach a valid operating voltage.
DVDD RST 70ms
POR Startup Timer (Time-Out) Internal Reset Signal
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Figure 3-15 DVdd Rise Time Exceeds Tstartup Figure 3-16 shows the recommended external reset circuit. The external reset circuit is required only if the
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3.8.1
Brown-Out Detector
registers are initialized to specific values, some are left unchanged, and some are undefined. A register that starts with an unknown value should be initialized by the software to a known value if it is going to be used (no need to initialize unused registers nor data memory). Do not simply test the initial state and rely on it starting in that state consistently. See Table 7-1 for more detailed information.
The on-chip brown-out detection circuitry resets the CPU when AVdd dips below the brown-out voltage level programmed in the BOR2:0 bits of the FUSE1 register (refer to Section 3.10.2). Bits in the FUSE1 register are flash memory cells which cannot be changed dynamically during program execution. The device is held in reset as long as AVdd stays below the brown-out voltage. The CPU will come out of reset when AVdd rises between 100mV and 200mV above the brown-out voltage (the CPU may never come out of brownout reset, even after AVdd returns to acceptable level, if the brownout setting is too high). Therefore, the 2.10V setting is recommended. The brown-out level can be programmed using the BOR2:0 bits in the FUSE1 register, as shown in Section 3.10.2.
3.8.2
Reset and Interrupt Vectors
After reset, the PC is loaded with 0xFFF0, which is near the top of the program memory space. Typical activities for the reset initialization code include: * * * Setting up the FCFG register with appropriate values for flash timing compensation. Issuing a speed instruction to initialize the CPU core clock speed. Checking for the cause of reset (brown-out voltage, watchdog timer overflow, or other cause). In some applications, a "warm" reset allows some data initialization procedures to be skipped. Copying speed-critical sections of code from flash memory to program RAM. Setting up data memory structures (stacks, tables, etc.). Initializing peripherals for operation (timers, etc.). Initializing the dynamic interrupt vector and enabling interrupts.
* * * *
Because the default interrupt vector location is 0, which is in program RAM, interrupts should not be enabled until the ISR is loaded in shadow RAM or the dynamic interrupt vector is loaded with the address of an ISR in flash memory. There is a single dynamic interrupt vector shared by all interrupts. The interrupt vector can be changed by loading the INTVECH and INTVECL registers, or by issuing a reti instruction with an option specifying that the interrupt vector should be updated with the current PC value plus 1.
3.8.3
Register States Following Reset
The effect of different reset sources on a register depends on the register and the type of reset operation. Some
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3.9
Clock Oscillator
There are two clock oscillators, the OSC oscillator and the RTCLK oscillator. Using the PLL clock multiplier, the OSC clock is intended to provide the time base for running the CPU core at speeds up to 120MHz for the standard version, and at 160 MHz for the faster version. The RTCLK oscillator operates at 32.768kHz using an external crystal. This oscillator is intended for running the real-time timer when the OSC oscillator and PLL clock multiplier are turned off. Either clock source can be driven by an external clock signal up to 120MHz. Figure 3-17 shows the clock logic for the IP2022, and Figure 3-18 shows that of the IP2012. The PLL clock
multiplier has a fixed multiplication factor of 50. The PLL is preceded by a divider capable of any integer divisor between 1 and 8, as controlled by the PIN2:0 bits of the FUSE0 register (refer to Section 3.10.1). The PLL is followed by a second divider capable of any integer divisor between 1 and 4, as controlled by the POUT1:0 bits of the FUSE0 register. A third divider which only affects the clock to the CPU core is controlled by the speed change mechanism described in Section 3.4. See Section 3.10.1 for a description of the FUSE0 WUDX2:0 and WUDP2:0 bits. Note: Bits in the FUSE0 register are flash memory cells which cannot be changed dynamically during program execution.
speed Instruction (SPDREG bits 5:4) FUSE0 WUDX2:0 WUDP2:0 01 00 System Clock 0-120 MHz speed Instruction (SPDREG bits 3:0)
IP2022-120, IP2012-120: FUSE0 Crystal 4.75-5 MHz Register Ext. 0-120 MHz (bits 11:9) OSC1 OSC Driver OSC2 0-120 MHz
PLL Bypass
FUSE0 Register (bits 13:12)
4.75-5 237.5-250 50X PLL MHz Pre- MHz PostClock Scaler Scaler Multiplier 11 10 SxCLK (RE0 or RF4) 01 00 SxMode Register (CLKS1:0)
SPDREG Divider
CPU Core 0-120MHz Timer 0 Timer 1 Timer 2 ADC External Memory Logic (IP2022 only) SERDES Clock
WUDX2:0
10 11
Crystal 32.768 kHz Ext. 0-120 MHz RTCLK1 RTCLK Driver RTCLK2
0 RTTMR 1
RTCFG Register, RTSS bit
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Figure 3-17 IP2022-120 and IP2012-120 Clock Logic
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IP2022-160: Crystal 4.75-5 MHz, 3.2 MHz Ext. 0-120 MHz OSC1 OSC Driver OSC2 0-120 MHz
FUSE0 Register (bits 11:9)
PLL Bypass
FUSE0 Register (bits 13:12)
speed Instruction (SPDREG bits 5:4) FUSE0 WUDX2:0 01
speed Instruction (SPDREG bits 3:0)
160 3.2 50X PLL MHz Pre- MHz PostClock WUDP2:0 or Scaler or Scaler 4.75-5 Multiplier 237.5-250 MHz MHz WUDX2:0 11 10 SxCLK (RE0 or RF4) 01 00 SxMode Register (CLKS1:0)
System Clock 0-120, 160 MHz SPDREG 00 Divider 10 11
CPU Core 0-120MHz, 160MHz Timer 0 Timer 1 Timer 2 ADC External Memory Logic SERDES Clock
Crystal 32.768 kHz Ext. 0-120 MHz RTCLK1 RTCLK Driver RTCLK2
0 RTTMR 1
RTCFG Register, RTSS bit
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Figure 3-18 IP2022-160 Clock Logic
3.9.1
External Connections
Figure 3-19 shows the connections for driving the OSC and/or RTCLK clock sources with an external signal. To drive the OSC clock source, the external clock signal is driven on the OSC1 pin and the OSC2 pin is left open. The external clock signal driven on the OSC1 pin may be any frequency up to 120 MHz. To drive the RTCLK clock source, the external clock signal is driven on the RTCLK1 input and the RTCLK2 output is left open. The external clock signal driven on the RTCLK1 pin may be any frequency up to 120 MHz.
Figure 3-20 shows the connections for attaching a crystal to the OSC and/or RTCLK oscillator. For the OSC oscillator, a crystal is connected across the OSC1 and OSC2 pins. For the RTCLK oscillator, a 32.768kHz crystal is connected across the RTCLK1 and RTCLK2 pins. There is about 4pf of capacitance on each of OSC1 and OSC2 pins to DVss and about 10pf of capacitance on each of RTCLK1 and RTCLK2 pins to DVss. There is also an internal feedback resistor (no external feedback resistor needed). For the OSC crystal, a parallel resonant crystal is recommended that has a maximum ESR of 100 ohms and a load capacitance rating of 12pF (requires 24pF on each of OSC1 and OSC2 pins). For the optional RTCLK crystal, a parallel resonant crystal is recommended that has a maximum ESR of 50K ohms, and a load capacitance rating of 12.5pF (requires 25pF on each of RTCLK1 and RTCLK2 pins). The crystal manufacturer's load capacitance rating (CL) should be equal to (C1 x C2)/(C1 + C2), where C1 = capacitance on OSC1 (4pF + stray board capacitance + added capacitance), and C2 = capacitance on OSC2 (4pF + stray board capacitance + added capacitance). The trace length between the OSC pins and the crystal should be as short as possible, to avoid noise coupling. When RTCLK1 is unused, it should be tied to GND.
IP2012/IP2022 FUSE0 bit 15=1 OSC1 FUSE0 bit 14=1 OSC2 Open RTCLK1 RTCLK2 Open
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Externally Generated Clock
Externally Generated Clock
Figure 3-19 External Clock Inputs
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IP2012/IP2022 XTAL (FUSE0 bit 15=0) OSC1 OSC2 Crystal RTCLK (FUSE0 bit 14=0) RTCLK1 RTCLK2 Crystal
20pF
20pF
15pF
15pF
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Figure 3-20 Crystal Connection
3.10
Configuration Block
block registers are used by software tools. The configuration block is readable but not writable when Code Protection is enabled. Table 3-6 lists the configuration block registers.
The configuration block is a set of flash memory registers outside of both program memory and data memory. These registers are not readable or writable at run time.
The FUSE0, FUSE1 registers hold settings that must be specified by system designers. The other configuration Table 3-6 Configuration Block Word Address 0x00010000 0x00010001 0x00010002 to 0x00010003 0x00010004 0x00010005 to 0x0001001D 0x0001001E0x0001001F 0x00010020 to 0x00010027 0x00010028 to 0x0001002F 0x00010030 to 0x00010031 0x00010032 to 0x00010033 0x00010034 to 0x00010035 0x00010036 to 0x0001003F Total 16-bit words Words 1 1 2 1 25 2 8 8 2 2 2 10 64 FUSE0 FUSE1 TRIM0 FREQ VCOMPANY VPRODUCT VVERSION VSOFTDATE VPROGDATE Name
Description FUSE0 register FUSE1 register Reserved TRIM0 register, factory programmed to FBFE Reserved OSC1 input frequency during device programming - used by tools only Company name Product name Software version Software date Programming date Reserved
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IP2012 / IP2022 Data Sheet
3.10.1 FUSE0 Register (not run-time programmable)
15 XTAL XTAL 14 RTCLK 13 12 11 10 PIN2:0 9 8 7 Reserved 6 5 4 WUDP2:0 3 2 1 WUDX2:0 0 POUT1:0
Figure 3-21 FUSE0 Register OSC2 crystal drive output 0 = Enabled -- Use for crystal clock 1 = Disabled -- Use for external clock RTCLK RTCLK2 crystal drive output 0 = Enabled -- Use for crystal clock 1 = Disabled -- Use for external clock POUT1:0 Specifies PLL clock multiplier postscaler divisor 00 = 1 (reserved) 01 = 2 10 = 3 11 = 4 PIN2:0 Specifies PLL clock multiplier prescaler divisor 000 = 1 100 = 5 001 = 2 101 = 6 010 = 3 110 = 7 011 = 4 111 = 8 WUDP2:0 Specifies system clock suspend time during PLL startup (after a speed instruction clears the PLL bit in the SPDREG register). 000 = 140 s 100 = 1 ms 001 = 210 s 101 = 2 ms 010 = 350 s 110 = 5 ms 011 = 630 s 111 = 9 ms WUDX2:0 Specifies system clock suspend time during OSC and RTCLK start-up. Used to keep the clock from propagating to the core before the crystal achieves valid signal levels (see Figure 3-17). Also keeps RST asserted except for POR and BOR. 000 = 450 s 001 = 1 ms 010 = 5 ms 011 = 9 ms 100 = 18 ms 101 = 72 ms 110 = 574 ms 111 = 1147 ms . Clock suspend time after POR is twice this long if the Watchdog is enabled in FUSE1 to a value less than WUDX.
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3.10.2 FUSE1 Register (not run-time programmable)
15 CP CP 14 SYNC 13 Reserved 7 6 5 BOR2:0 4 3 WDTE 2 1 WDPS2:0 0
SYNC
Figure 3-22 FUSE1 Register Clear to enable code protection. Once cleared, this bit cannot be set until the entire device is erased. When code protection is enabled, program memory reads as all 0 to an external device programmer. This bit does not affect access to program memory made by software, using the iread, ireadi, iwrite, iwritei, ferase, fwrite and fread instructions. In-system debugging is not available when code protection is enabled. Code protection does not protect the configuration block against reading, only against writing. Note: After clearing this bit during programming, Code Protect is not activated until the part is powered down or reset. 0 = enabled 1 = disabled Set to read directly from the port pins through the RxIN register, clear to read through a CPU core clock synchronization register. This bit should be clear if any external devices that can be read from I/O port pins are running asynchronously to the CPU core clock. See Figure 5-1. 0 = enabled 1 = disabled Specifies brown-out voltage level. If AVdd goes below this level, the IP2012 / IP2022 is reset. This setting should be at least 0.2V below the minimum operating AVdd, because there is a maximum of 0.2V hysteresis to leave brownout reset after power up and after brownout reset occurs. 000 = 2.30V 0.1V Do not use unless AVdd 2.50V 001 = 2.25V 0.1V Do not use unless AVdd 2.45V 010 = 2.20V 0.1V 011 = 2.15V 0.1V 100 = 2.10V 0.1V Recommended 101 = Reserved 110 = Reserved 111 = Disabled, no brown-out reset can occur. Enables Watchdog Timer in run mode. Disabled in debug mode regardless of this bit. 0 = disabled 1 = enabled Specifies the Watchdog Timer prescaler divisor. This controls the time period before the Watchdog Timer expires. If the Watchdog Timer is enabled, software must clear the Watchdog Timer periodically within this time period to prevent a reset of the IP2012 / IP2022 from occurring. The cwdt instruction or any reset clears both the Watchdog Timer and its prescaler. Care must be taken to ensure that this setting is not greater than the maximum crystal start-up time plus the time required to get to the first cwdt instruction. 000 = 1 (~20 ms) = 256 x WRC 100 = 16 (~320 ms) 001 = 2 (~40 ms) 101 = 32 (~640 ms) 010 = 4 (~80 ms) 110 = 64 (~1280 ms) 011 = 8 (~160 ms) 111 = 128 (~2560 ms)
BOR2:0
WDTE
WDPS2:0
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3.10.3 TRIM0 Register
Factory programmed to $FBFE for 120MHz versions, $FBFD for 160MHz versions operating at 160MHz. Must leave at factory default for proper operation. 15 14 13 12 SQUELT3:0 11 SQUELT5 10 FPERT 9 8 7 CMPT2:0 6 5 4 3 SQUELT4 VCOT3 SQUELT7:6 2 1 0 VCOT2:0
Figure 3-23 TRIM0 Register SQUELT7:0 FPERT SERDES squelch trim bits Controls flash block pulse erase, both for self-programming ferase and for the FERASE command from the ISD/ISP interface 0 = 20 ms, if OSC1 frequency and FCFG register settings are optimal 1 = Reserved - 10ms block erase (do not use) Comparator offset trim bits PLL VCO frequency trim bits 1110 = 4.75-5.0 MHz into PLL 1101 = 3.2 MHz into PLL
CMPT2:0 VCOT3:0
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4.0
Instruction Set Architecture
4.1
Addressing Modes
The IP2012 / IP2022 implements a powerful load-store RISC architecture with a rich set of arithmetic and logical operations, including signed and unsigned 8-bit 8-bit integer multiply with a 16-bit product. The CPU operates on data held in 128 special-purpose registers, 128 global registers, and 3840 bytes of data memory. The special-purpose registers are dedicated to control and status functions for the CPU and peripherals. The global registers and data memory may be used for any functions required by software, the only distinction among them being that the 128 global registers (addresses 0x080 to 0x0FF) can be accessed using a direct addressing mode. The remaining 3840 bytes of data memory (between addresses 0x100 and 0xFFF) must be accessed using indirect or indirect-with-offset addressing modes. The IPH/IPL register is the pointer for the indirect addressing mode, and the DPH/DPL and SPH/SPL registers are the pointers for the indirect-with-offset addressing modes.
A 9-bit field within the instruction, called the "fr" field, specifies the addressing mode and the address (in the case of direct addressing) or the address offset (in the case of indirect-with-offset addressing), as shown in Table 4-1. (See Figure 3-7 for data RAM map.)
4.1.1
Pointer Registers
When an addition or increment instruction (i.e. add, inc, incsz, or incsnz) on the low byte of a pointer register (i.e. IPL, DPL, SPL, or ADDRL) generates a carry, the high part of the register is incremented. For example, if the IP register holds 0x00FF and an inc ipl instruction is executed, the register will hold 0x0100 after the instruction. When a subtraction or decrement instruction (i.e. sub, subc, dec, decsz, or decsnz) generates a borrow, the high part of the register is decremented. Note: Because carry and borrow are automatically handled, the addc and subc instructions are not needed for arithmetic operations on pointer registers.
Table 4-1 Addressing Mode Summary "fr" Field 0 0000 0000 0 0nnn nnnn 0 1nnn nnnn 1 0nnn nnnn 1 1nnn nnnn Mode Indirect Direct, specialpurpose registers Direct, global registers Indirect with offset, data pointer Indirect with offset, stack pointer Syntax
mov w,(ip) mov (ip),w mov w,fr mov fr,w mov w,fr mov fr,w mov w,offset(dp) mov offset(dp),w mov w,offset(sp) mov offset(sp),w
Effective Address (EA) IPH || IPL nnnnnnn 0x080 + nnnnnnn DPH || DPL + nnnnnnn SPH || SPL + nnnnnnn
Restrictions 0x020 < EA < 0xFFF 0x002 < EA < 0x07F 0x080 < EA < 0x0FF 0x000 < nnnnnnn < 0x07F 0x020 < EA < 0xFFF 0x000 < nnnnnnn < 0x07F 0x020 < EA < 0xFFF
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4.1.2
Direct Addressing Mode
4.1.3
Indirect Addressing Mode
Figure 4-1 shows the direct addressing mode used to reference the special-purpose registers. Seven bits from the "fr" field allow addressing up to 128 special-purpose registers. (Not all 128 locations in this space are implemented in the IP2012 / IP2022; several locations are reserved for future expansion.)
9-Bit "fr" Field from Instruction 876 0 00nnnnnnn 7 0
The indirect addressing mode is used when all of the bits in the "fr" field are clear. The location of the operand is specified by a 12-bit pointer in the IPH and IPL registers. The upper four bits of the IPH register are not used. Figure 4-3 shows indirect mode.
7 0 0
9-Bit "fr" Field from Instruction 8 000000000
127 Special-Purpose Registers 128 Global Registers
127 Special-Purpose Registers
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IPH Register IPL Register 7 43 07 0 XXXXn n n n n n n n n n n n
Figure 4-1 Direct Mode, Special-Purpose Registers The following code example uses direct mode.
mov w,0x0012 ;load W with the contents of ;the memory location at 0x0012 ;(the DATAL register)
3840 Bytes Data Memory
Figure 4-2 shows the direct addressing mode used to reference the global registers. This mode is distinguished from the mode used to access the special-purpose registers with bit 7 of the "fr" field. Because these registers have this additional addressing mode not available for the other data memory locations, they are especially useful for holding global variables and frequently accessed data.
9-Bit "fr" Field from Instruction 876 0 01nnnnnnn 7 0
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Figure 4-3 Indirect Mode The following code example uses indirect mode.
mov mov mov mov mov w,#0x03 iph,w w,#0x85 ipl,w w,(ip) ;load W with 0x03 ;load the high byte of the ;indirect pointer from W ;load W with 0x85 ;load the low byte of the ;indirect pointer from W ;load W with the contents of ;the memory location at ;effective address 0x0385
127 Global Registers
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Figure 4-2 Direct Mode, Global Registers Note: Addresses from 0x000 to 0x01F can only be accessed with Direct mode.
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4.1.4
Indirect-with-Offset Addressing Mode
mov
w,8(dp)
The indirect-with-offset addressing mode is used when bit 8 of the "fr" field is set. The location of the operand is specified by a 7-bit unsigned immediate from the "fr" field added to a 12-bit base address in a pointer register. When bit 7 of the "fr" field is clear, the DPH/DPL register is selected as the pointer register. This register is accessed using the loadh and loadl instructions, which load its high and low bytes, respectively. The upper four bits of the DPH register are not used. Figure 4-4 shows indirect-with-offset addressing using the DPH/DPL register as the pointer register.
9-Bit "fr" Field from Instruction 876 0 1 0 mmmmmmm 7 0
;load W with the contents of ;the memory location at ;effective address 0x038D ;(i.e. 0x0385 + 0x0008)
127 Special-Purpose Registers 128 Global Registers
When bit 7 of the "fr" field is set, the SPH/SPL register is selected as the pointer register. The upper four bits of the SPH register are not used. Figure 4-5 shows indirect-withoffset mode using the SPH/SPL register. In addition to this indirect-with-offset addressing mode, there are also push and pop instructions which automatically increment and decrement the SPH/SPL register while performing a data transfer between the top of stack and a data memory location specified by the "fr" field. Stacks grow down from higher addresses to lower addresses. This stack addressing mechanism is completely independent from the hardware stack used for subroutine call and return. When a pop instruction is used with the indirect-withoffset addressing mode, the address calculation for the "fr" operand is made using the value in the SPH/SPL register before the automatic increment, even though the stack operand itself is addressed using the value after the automatic increment. Figure 4-5 Indirect-with-Offset Mode, Stack Pointer
7 0
DPH Register DPL Register 7 43 07 0 XXXXn n n n n n n n n n n n
+ 3840 Bytes Data Memory
9-Bit "fr" Field from Instruction 876 0 1 1 mmmmmmm
127 Special-Purpose Registers 128 Global Registers
SPH Register SPL Register 7 43 07 0 XXXXn n n n n n n n n n n n
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+ 3840 Bytes Data Memory
Figure 4-4 Indirect-with-Offset Mode, Data Pointer The following code example uses indirect-with-offset addressing mode.
MyStuff= 0x038D loadh MyStuff ;define address MyStuff ;load the high byte of the ;DPH/DPL pointer register ;with 0x03 ;load the low byte of the ;DPH/DPL pointer register ;with 0x8D
loadl
MyStuff
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4.2
Instruction Set
instructions that use the top of the stack or a specialpurpose register as the destination operand. 15 Opcode 8 7 8-Bit Literal ("#lit8") 0
The instruction set consists entirely of single-word (16-bit) instructions, most of which can be executed at a rate of one instruction per clock cycle, for a throughput of up to 120 MIPS when executing out of program RAM. Assemblers may implement additional instruction mnemonics for the convenience of programmers, such as a long jump instruction which compiles to multiple IP2012 / IP2022 instructions for handling the page structure of program memory. Refer to the assembler documentation for more information about any instruction mnemonics implemented in the assembler.
Figure 4-7 Immediate-Operand Instruction Format Figure 4-8 shows the format of the jump and subroutine call instructions. 13 bits of the entry point address are encoded in the instruction. The remaining three bits come from the PA2:0 bits of the STATUS register. 15 13 12 Opcode 0 Entry Point Address ("addr13")
Figure 4-8 Jump and Call Instruction Format
4.2.1
* * * * *
Instruction Formats
There are five instruction formats: Two-operand arithmetic and logical instructions Immediate-operand arithmetic and logical instructions Jumps and subroutine calls Bit operations Miscellaneous instructions
Figure 4-9 shows the format of the instructions that clear, set, and test individual bits within registers. The register is specified by the "fr" field, and a 3-bit field in the instruction selects one of the eight bits in the register. 15 Opcode 12 11 Bit 9 8 "fr" Field 0
Figure 4-9 Bit Operation Instruction Format Figure 4-10 shows the format of the remaining instructions. 15 14 13 12 11 10 9 0000000 8 Opcode 0
Figure 4-6 shows the two-operand instruction format. The two-operand instructions perform an arithmetic or logical operation between the W register and a data memory location specified by the "fr" field. The D bit indicates the destination operand. When the D bit is clear, the destination operand is the W register. When the D bit is set, the destination operand is specified by the "fr" field. There are some exceptions to this behavior. The multiply instructions always load the 16-bit product into the MULH and W registers. The MULH register receives the upper 8 bits, and the W register receives the lower 8 bits. Traditionally single-operand instructions, such as increment, are available in two forms distinguished by the D bit. When the D bit is clear, the source operand is specified by the "fr" field and the destination operand is the W register. When the D bit is set, the data memory location specified by the "fr" field is both the source and destination operand. Also, there are a few cases of unrelated instructions, such as clr and cmp, which are distinguished by the D bit. 15 Opcode 10 9 8 D 0 "fr" Field
Figure 4-10 Miscellaneous Instruction Format
4.2.2
Instruction Types
The instructions are grouped into the following functional categories: * * * * * * Logical instructions Arithmetic and shift instructions Bit operation instructions Data movement instructions Program control instructions System control instructions
Logical Instructions Each logic instruction performs a standard logical operation (AND, OR, exclusive OR, or logical complement) on the respective bits of the 8-bit operands. The result of the logic operation is written to W or to the data memory location specified by the "fr" field. All of these instructions take one clock cycle for execution. Arithmetic and Shift Instructions Each arithmetic or shift instruction performs an operation such as add, subtract, add with carry, subtract with carry,
Figure 4-6 Two-Operand Instruction Format Figure 4-7 shows the immediate operand instruction format. In this format, an 8-bit literal value is encoded in the instruction field. Usually the W register is the destination operand, however this format also includes
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rotate left or right through carry, increment, decrement, clear to zero, or swap high/low nibbles. The compare (cmp) instruction performs the same operation as subtract, but it only updates the C, DC, and Z flags of the STATUS register; the result of the subtraction is discarded. There are instructions available (incsz, decsz) that increment or decrement a register and simultaneously test the result. If the 8-bit result is zero, the next instruction in the program is skipped. These instructions can be used to make program loops. There are also compare-and-skip instructions (cse, csne) which perform the same operation as subtract, but perform a conditional skip without affecting either operand or the condition flags in the STATUS register. All of the arithmetic and shift instructions take one clock cycle for execution, except in the case of the test-and-skip instructions when the tested condition is true and a skip occurs, in which case the instruction takes at least two cycles. If a skip instruction is immediately followed by a loadh, loadl, or page instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles. This is useful for skipping over a conditional branch to another page, in which a page instruction precedes a jmp instruction. If several page or loadh/loadl instructions immediately follow a skip instruction, then they are all skipped plus the next instruction and a cycle is consumed for each. These "extended skip instructions" are interruptible, so they do not affect interrupt latency. Bit Operation Instructions There are four bit operation instructions: * * * *
Program Control Instructions A program control instruction alters the flow of the program by changing the contents of the program counter. Included in this category are the jump, call, return-fromsubroutine, and interrupt instructions. The jmp instruction has a single operand that specifies the entry point at which to continue execution. The entry point is typically specified in assembly language with a label, as in the following code example:
snb jmp status,0 do_carry ;test the carry bit ;jump to do_carry routine ;if C = 1
... do_carry: ...
;jump destination label ;execution continues here
If the carry bit is set to 1, the jmp instruction is executed and program execution continues where the do_carry label appears in the program. The call instruction works in a similar manner, except that it saves the contents of the program counter to the CALLH/CALLL registers before jumping to the new address. It calls a subroutine that is terminated by a ret, retw, or retnp instruction, as shown in the following code example:
call nop add_2bytes ;call subroutine ;add_2bytes ;execution returns to ;here after the ;subroutine is finished ;subroutine label ;subroutine code goes ;here ;return from subroutine
setb--sets a single bit in a data register without affecting other bits clrb--clears a single bit in a data register without affecting other bits sb--tests a single bit in a data register and skips the next instruction if the bit is set snb--tests a single bit in a data register and skips the next instruction if the bit is clear
... add_2bytes: ... ret
All of the bit operation instructions take one clock cycle for execution, except for test-and-skip instructions when the tested condition is true and a skip occurs. Data Movement Instructions A data movement instruction moves a byte of data from a data memory location to either the W register or the top of stack, or it moves the byte from either the W register or the top of stack to a data memory location. The location is specified by the "fr" field. The SPH/SPL register pair points to the top of stack. This stack is independent of the hardware stack used for subroutine call and return.
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Returning from a subroutine restores the saved program counter contents from the CALLH/CALLL registers, which causes program to resume execution with the instruction immediately following the call instruction (a nop instruction, in the above example) A program memory address contains 16 bits. The jmp and call instructions specify only the lowest thirteen bits of the jump/call address. The upper 3 bits come from the PA2:0 bits of the STATUS register. An indirect relative jump can be accomplished by adding the contents of the W register to the PCL register (i.e. an add pcl,w instruction). Program control instructions such as jmp, call, and ret alter the normal program sequence. When one of
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these instructions is executed, the execution pipeline is automatically cleared of pending instructions and refilled with new instructions, starting at the new program address. Because the pipeline must be cleared, three clock cycles are required for execution, one to execute the instruction and two to reload the pipeline. System Control Instructions A system control instruction performs a special-purpose operation that sets the operating mode of the device or reads data from the program memory. Included in this category are the following types of instructions: * * * * * * * * * * * *
4.3
Instruction Pipeline
speed--changes the CPU core speed (for saving
power)
An instruction goes through a four-stage pipeline to be executed, as shown in Figure 4-11. The first instruction is fetched from the program memory on the first core clock cycle. On the second clock cycle, the first instruction is decoded and a second instruction is fetched. On the third clock cycle, the first instruction is executed, the second instruction is decoded, and a third instruction is fetched. On the fourth clock cycle, the first instruction's results are written to its destination, the second instruction is executed, the third instruction is decoded, and a fourth instruction is fetched. Once the pipeline is full, instructions are executed at the rate of one per clock cycle. Stage Core Cycle 1 Core Cycle 2 Core Cycle 3 Core Cycle 4
Instruction 4 Instruction 3 Instruction 2 Instruction 1
break--enters debug mode page--writes to the PA2:0 bits in the STATUS register
loadh/loadl--loads a 16-bit pointer into the DPH
and DPL registers iread--reads a word from external memory, program flash memory, or program RAM ireadi--reads a word (and auto-increments ADDR by 2) from program flash memory, or program RAM iwrite--writes a word to external memory or program RAM iwritei--writes a word (and auto-increments ADDR by 2) to program RAM fread--reads a word from flash program memory fwrite--writes a word to flash program memory ferase--erases a block of flash program memory cwdt--clears the Watchdog Timer
Fetch Instruction 1 Instruction 2 Instruction 3 Instruction 1 Instruction 2 Decode Instruction 1 Execute Write Figure 4-11 Pipeline Execution
Instructions that directly affect the contents of the program counter (such as jumps and calls) require that the pipeline be cleared and subsequently refilled. Therefore, these instructions take two additional clock cycles (the PC will be changed during the execute cycle of a jump instruction).
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4.4
Subroutine Call/Return Stack
A 16-level hardware call/return stack is provided for saving the program counter on a subroutine call and restoring the program counter on subroutine return. The stack is not mapped into the data memory address space except for the top level, which is accessible as the CALLH and CALLL registers. Software can read and write these registers to implement a deeper stack, in those cases which require nesting subroutines more than 16 levels deep. This stack is completely independent of the stack used with the push and pop instructions and the SPH/SPL register pair. Note: The CALLL and CALLH registers require special attention as modification of these values (the top of the stack) changes the return vector. When a subroutine is called, the return address is pushed onto the subroutine stack, as shown in Figure 4-12. Specifically, each saved address in the stack is moved to the next lower level to make room for the new address to be saved. Stack 1 receives the contents of the program counter. Stack 16 is overwritten with what was in Stack 15. The contents of stack 16 are lost.
Program Counter (15:0) CALLH/CALLL Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 Stack 7 Stack 8 Stack 9 Stack 10 Stack 11 Stack 12 Stack 13 Stack 14 Stack 15 Stack 16 Stack 16 Contents are Discarded
and the contents of each stack level are moved to the next higher level. When a value is popped off the stack, the bottom entry is initialized to 0xFFFF. For example, Stack 1 receives the contents of Stack 2, etc., and Stack 15 is overwritten with the contents of Stack 16. Stack 16 is initialized to 0xFFFF.
Program Counter (15:0) Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 Stack 7 Stack 8 Stack 9 Stack 10 Stack 11 Stack 12 Stack 13 Stack 14 Stack 15 Stack 16 Stack 16 Contents Loaded with 0xFFFF
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Figure 4-13 Stack Operation on Subroutine Return For program bugs involving stack underflow, the instruction at byte address 0x1FFFE (word address 0xFFFF) can be used to jump to an appropriate handler. For example, system recovery may be possible by jumping to the reset vector at byte address 0x1FFE0 (word address 0xFFF0). The options for returning from a CALL are: 1. RET - The stack will be popped (CALLH/L will be loaded into PCH/L) and the page bits (PA2:0 in the STATUS register) will be loaded with the upper 3 bits of CALLH. 2. RETNP - Same as above, but PA2:0 are not changed. 3. RETW #lit - Same as RET, but also moves literal to W.
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Figure 4-12 Stack Operation on Subroutine Call When a return instruction is executed the subroutine stack is popped, as shown in Figure 4-13. Specifically, the contents of Stack 1 are copied into the program counter
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4.5
Key to Abbreviations and Symbols
Description
Symbol ^ | ||
Description Logical exclusive OR Logical OR Concatenation
Symbol
(address) Contents of memory referenced by address
addr13 13-bit address in assembly language instruction addr16 16-bit address in assembly language instruction bit BO C DC DPH DPL f fr IPH IPL k n PCL SPH SPL Bit position selector bit in opcode Brown-out bit in the PSPCFG register (bit 0) Carry bit in the STATUS register (bit 0) Digit Carry bit in the STATUS register (bit 1) Upper half of data pointer for indirect-with-offset addressing (global file register 0x00C) Lower half of data pointer for indirect-with-offset addressing (global file register 0x00D) File register address bit in opcode File register field (a 9-bit file register address specified in the instruction) Indirect Pointer High - Upper half of pointer for indirect addressing (global file register 0x004) Indirect Pointer Low - Lower half of pointer for indirect addressing (global file register 0x005) Constant value bit in opcode Numerical value bit in opcode Virtual register for direct PC modification (global file register 0x009) Upper half of stack pointer for indirect-with-offset addressing (global file register 0x006) Lower half of stack pointer for indirect-with-offset addressing (global file register 0x007) Working register Watchdog Timeout bit in the PSPCFG register (bit 1) Watchdog Timer counter and prescaler Zero bit in the STATUS register (bit 2 File register/bit selector separator (e.g. clrb status,z) inequality Immediate literal designator in assembly language instruction (e.g. mov w,#0xff) 8-bit literal value in assembly language instruction Logical AND
4.6
Instruction Set Summary Tables
Table 4-2 through Table 4-7 list all of the IP2012 / IP2022 instructions, organized by category. For each instruction, the table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycles required for execution, the binary opcode, and the flags in the STATUS register affected by the instruction. Although the number of clock cycles for execution is typically 1, for the skip instructions the exact number of cycles depends whether the skip is taken or not taken. Taking the skip adds 1 cycle. The effect of extended skip instructions (i.e. a skip followed by a loadh, loadl, or page instruction) is not shown. For more detailed description, refer to the Programmer's Reference Manual.
PA2:PA0 Page bits in the STATUS register (bits 7:5)
STATUS STATUS register (global file register 0x00B) W WD WDT Z , != # #lit8 &
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Table 4-2 Logical Instructions Assembler Syntax
and fr,w and w,fr and w,#lit8 not fr not w,fr or fr,w or w,fr or w,#lit8 xor fr,w xor w,fr xor w,#lit8
Pseudocode Definition fr = fr & W W = W & fr W = W & lit8 fr = fr W = fr fr = fr | W W = W | fr W = W | lit8 fr = fr ^ W W = W ^ fr W = W ^ lit8
Description AND fr,W into fr AND W,fr into W AND W,literal into W Complement fr into fr Complement fr into W OR fr,W into fr OR W,fr into W OR W,literal into W XOR fr,W into fr XOR W,fr into W XOR W,literal into W
Core Cycles 1 1 1 1 1 1 1 1 1 1 1
Opcode
0001 011f ffff ffff 0001 010f ffff ffff 0111 1110 kkkk kkkk 0010 011f ffff ffff 0010 010f ffff ffff 0001 001f ffff ffff 0001 000f ffff ffff 0111 1101 kkkk kkkk 0001 101f ffff ffff 0001 100f ffff ffff 0111 1111 kkkk kkkk
Flags Affected Z Z Z Z Z Z Z Z Z Z Z
Table 4-3 Arithmetic and Shift Instructions Assembler Syntax
add fr,w add w,fr add w,#lit8 addc fr,w addc w,fr clr fr cmp w,fr cmp w,#lit8 cse w,fr cse w,#lit8 csne w,fr
Pseudocode Definition fr = fr + W W = W + fr W = W + lit8 fr = C + fr + W W = C + W + fr fr = 0 fr - W lit8 - W if (fr - W) = 0 then skip if (lit8 - W) = 0 then skip if (fr - W) != 0 then skip then skip
Description Add fr,W into fr Add W,fr into W Add W,literal into W Add carry,fr,W into fr Add carry,W,fr into W Clear fr Compare W,fr then update STATUS Compare W,literal then update STATUS Compare W,fr then skip if equal Compare W,literal then skip if equal Compare W,fr then skip if not equal Compare W,literal then skip if not equal Clear Watchdog Timer Decrement fr into fr Decrement fr into W Decrement fr into fr then skip if not zero (STATUS not updated)
Core Cycles 1 1 1 1 1 1 1 1
Opcode
0001 111f ffff ffff 0001 110f ffff ffff 0111 1011 kkkk kkkk 0101 111f ffff ffff 0101 110f ffff ffff 0000 011f ffff ffff 0000 010f ffff ffff 0111 1001 kkkk kkkk
Flags Affected C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z Z C, DC, Z C, DC, Z None None None None None Z Z None
0100 001f ffff ffff 1 or 2 (skip) 0111 0111 kkkk kkkk 1 or 2 (skip) 0100 000f ffff ffff 1 or 2 (skip) 0111 0110 kkkk kkkk 1 or 2 (skip)
csne w,#lit8 if (lit8 - W) != 0 cwdt dec fr dec w,fr decsnz fr
WDT = 0 fr = fr - 1 W = fr -1 fr = fr - 1 if fr != 0 then skip
1 1 1
0000 0000 0000 0100 0000 111f ffff ffff 0000 110f ffff ffff
0100 111f ffff ffff 1 or 2 (skip)
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IP2012 / IP2022 Data Sheet
Table 4-3 Arithmetic and Shift Instructions (continued) Assembler Syntax
decsnz w,fr decsz fr decsz w,fr inc fr inc w,fr incsnz fr incsnz w,fr incsz fr incsz w,fr muls w,fr
Pseudocode Definition W = fr - 1 if fr != 0 then skip fr = fr - 1 if fr = 0 then skip W = fr - 1 if fr = 0 then skip fr = fr + 1 W = fr + 1 fr = fr + 1 if fr != 0 then skip W = fr + 1 if fr != 0 then skip fr = fr + 1 if fr = 0 then skip W = fr + 1 if fr = 0 then skip
Description Decrement fr into W then skip if not zero (STATUS not updated) Decrement fr into fr then skip if zero (STATUS not updated) Decrement fr into W then skip if zero (STATUS not updated) Increment fr into fr Increment fr into W Increment fr into fr then skip if not zero (STATUS not updated) Increment fr into W then skip if not zero (STATUS not updated) Increment fr into fr then skip if zero (STATUS not updated) Increment fr into W then skip if zero (STATUS not updated)
Core Cycles
Opcode
Flags Affected None None None Z Z None None None None None
0100 110f ffff ffff 1 or 2 (skip) 0010 111f ffff ffff 1 or 2 (skip) 0010 110f ffff ffff 1 or 2 (skip)
1 1
0010 101f ffff ffff 0010 100f ffff ffff
0101 101f ffff ffff 1 or 2 (skip) 0101 100f ffff ffff 1 or 2 (skip) 0011 111f ffff ffff 1 or 2 (skip) 0011 110f ffff ffff 1 or 2 (skip)
MULH || W = W fr Signed 8 8 multiply (bit 7 = sign); W x fr into MULH || W (bit 7 of MULH is result sign) sign); W x literal into MULH || W (bit 7 of MULH is result sign)
1
0101 010f ffff ffff
muls w,#lit8 MULH || W = W lit8 Signed 8 8 multiply (bit 7 =
1
0111 0011 kkkk kkkk
None
mulu w,fr
MULH || W = W fr Unsigned 8 8 multiply; W x fr into MULH || W eral into MULH || W
1 1 1 1 1 1 1 1 1 1 1
0101 000f ffff ffff 0111 0010 kkkk kkkk 0011 011f ffff ffff 0011 010f ffff ffff 0011 001f ffff ffff 0011 000f ffff ffff 0000 101f ffff ffff 0000 100f ffff ffff 0111 1010 kkkk kkkk 0100 101f ffff ffff 0100 100f ffff ffff
None None C C C C C, DC, Z C, DC, Z C, DC, Z C, DC, Z C, DC, Z
mulu w,#lit8 MULH || W = W lit8 Unsigned 8 8 multiply; W x litrl fr rl w,fr rr fr rr w,fr sub fr,w sub w,fr sub w,#lit8 subc fr,w subc w,fr
fr || C = C || fr W || C = C || fr C || fr = fr || C C || W = fr || C fr = fr - W W = fr - W W = lit8 - W fr = fr - C - W W = fr - C - W
Rotate fr left through carry into fr Rotate fr left through carry into W Rotate fr right through carry into fr Rotate fr right through carry into W Subtract W from fr into fr Subtract W from fr into W Subtract W from literal into W Subtract carry,W from fr into fr Subtract carry,W from fr into W
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IP2012 / IP2022 Data Sheet
Table 4-3 Arithmetic and Shift Instructions (continued) Assembler Syntax
swap fr swap w,fr test fr
Pseudocode Definition fr = fr3:0 || fr7:4 W = fr3:0 || fr7:4 if fr = 0 then Z = 1 else Z = 0
Description Swap high,low nibbles of fr into fr Swap high,low nibbles of fr into W Test fr for zero and update Z
Core Cycles 1 1 1
Opcode
0011 101f ffff ffff 0011 100f ffff ffff 0010 001f ffff ffff
Flags Affected None None Z
Table 4-4 Bit Operation Instructions Assembler Syntax
clrb fr,bit sb fr,bit setb fr,bit snb fr,bit
Pseudocode Definition fr,bit = 0
Description Clear bit in fr
Core Cycles 1
Opcode
1000 bbbf ffff ffff
Flags Affected None None None None
if fr,bit = 1 then skip Test bit in fr then skip if set fr,bit = 1 Set bit in fr
1011 bbbf ffff ffff 1 or 2 (skip)
1
1001 bbbf ffff ffff
if fr,bit = 0 then skip Test bit in fr then skip if clear
1010 bbbf ffff ffff 1 or 2 (skip)
Table 4-5 Data Movement Instructions Assembler Syntax
mov fr,w mov w,fr mov w,#lit8 push fr push #lit8 pop fr
Pseudocode Definition fr = W W = fr W = lit8 (SP) = fr, then SP = SP - 1 (SP) = lit8, then SP = SP - 1
Description Move W into fr Move fr into W Move literal into W Move fr onto top of stack Move literal onto top of stack
Core Cycles 1 1 1 1 1 1
Opcode
0000 001f ffff ffff 0010 000f ffff ffff 0111 1100 kkkk kkkk 0100 010f ffff ffff 0111 0100 kkkk kkkk 0100 011f ffff ffff
Flags Affected None Z None None None None
fr = (SP + 1), then Move top of stack + 1 into fr SP = SP + 1
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IP2012 / IP2022 Data Sheet
Table 4-6 Program Control Instructions Assembler Syntax
call addr13 jmp addr13 int nop ret retnp reti #lit3 retw #lit8
Description Call subroutine Jump Software interrupt No operation Return from subroutine Return from subroutine, without updating page bits Return from interrupt (see Section 3.7.4) Return from subroutine with literal into W
Core Cycles 3 3 3 1 3 3 3 3
Opcode
110k kkkk kkkk kkkk 111k kkkk kkkk kkkk 0000 0000 0000 0110 0000 0000 0000 0000 0000 0000 0000 0111 0000 0000 0000 0010 0000 0000 0000 1nnn 0111 1000 kkkk kkkk
Flags Affected None None None None PA2:0 None All PA2:0
Table 4-7 System Control Instructions Assembler Syntax
break
Description Software breakpoint. Keeps PC from advancing and stops timers, including the Watchdog Timer Software breakpoint, extending the skip Erase a 256 word flash block Read flash memory Write flash memory Read external/program memory Read program memory and increment ADDRL to next even ADDRL Write into external memory/program RAM Write into program RAM and increment ADDRL to next even ADDRL Load high data address into DPH Load low data address into DPL Load page bits from program address into PA2:0 of the STATUS register Change CPU speed by writing into the SPDREG register
Core Cycles 1
Opcode
0000 0000 0000 0001
Flags Affected None
breakx ferase fread fwrite iread ireadi iwrite iwritei loadh addr8 loadl addr8 page addr3 speed #lit8
1 1 1 1 4(blocking), 1(nonblocking) 4(blocking), 1(nonblocking) 4(blocking), 1(nonblocking) 4(blocking), 1(nonblocking) 1 1 1 1
0000 0000 0000 0101 0000 0000 0000 0011 0000 0000 0001 1011 0000 0000 0001 1010 0000 0000 0001 1001 0000 0000 0001 1101 0000 0000 0001 1000 0000 0000 0001 1100 0111 0000 kkkk kkkk 0111 0001 kkkk kkkk 0000 0000 0001 0nnn 0000 0001 nnnn nnnn
None None None None None None None None None None PA2:0 None
. Only occupies the CPU pipeline for 1 cycle, but the operation is not complete until XCFG:0 = 0. (Refer to Section 4.7)
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IP2012 / IP2022 Data Sheet
4.7
Program Memory Self-Programming and Read Instructions
Table 4-8 Instructions Used for Self-Programming Operation Read Program RAM (ADDRX = 00) Flash (ADDRX =01) External Memory (ADDRX = 80 or 81)
iread (Blocking) ireadi (Blocking) iwrite (Blocking) iwritei (Blocking)
N/A
fread (Nonblocking) 1 iread2 ireadi2 fwrite (Nonblocking) 3 ferase (Nonblocking) 3
iread (Nonblocking)
Write Erase
iwrite (Nonblocking)
N/A
1 -- Rules 1, 2, 3, 5, 7, and 10 below apply. 2 -- Rules 2, 3, 5, 7, and 10 below apply. If executed from program RAM, the instruction is nonblocking; if executed from flash, it is blocking. 3 -- Rules 1, 2, and 4-10 below apply.
The IP2012 / IP2022 has several instructions used to read and write the program RAM and the program flash memory. These instructions allow the program flash memory to be read and written through special-purpose registers in the data memory space, which allows the flash memory to be used to store both program code and data. Because no special programming voltage is required to write to the flash memory, any application may take advantage of this feature at run-time. Typical uses include saving phone numbers and passwords, downloading new or updated software, and logging infrequent events such as errors and Watchdog Timer overflow. The self-programming instructions are not affected by the code-protection flag (the CP bit of the FUSE1 register), so the entire program memory is readable and writable by any software running on the IP2012 / IP2022. Note: It is highly recommended to enable the brown-out reset feature if self-programming instructions are being used in user program code (see Section 3.8.1 for more information about BOR). This will avoid corruption of flash memory during power down. There are seven instructions used for self-programming, as shown in Table 4-8. Certain uses of the instructions are not valid. In these cases, the instruction is executed as though it were a nop instruction (i.e. the program counter is incremented, but no other registers or bits are affected). Blocking instructions take 4 cycles to complete, and prevent other instructions from executing. Non-blocking instructions occupy the CPU pipeline for only one cycle, but they launch a multi-cycle operation which is not
complete until indicated by the FBUSY bit in the XCFG register becoming clear. The DATAH/DATAL register is a 16-bit data buffer used for loading or unloading data in program memory. The ADDRX/ADDRH/ADDRL register holds a 24-bit byte address used to specify the low-byte of the desired word location in program memory. Like the other pointer registers (IPH/IPL, DPH/DPL, and SPH/SPL), addition to the low byte of the register that results in carry will cause the high part of the register (ADDRX/ADDRH) to be incremented. Subtraction from the low byte of the register that results in borrow will cause the high part of the register to be decremented. Note: If ADDRSEL is modified in the ISR, it must first be shadowed in software, and restored before reti. Note: ADDRL bit 0 is ignored as the A0 address bit is handled automatically in hardware. Software should use the FBUSY bit to check that a previous flash write or erase operation has completed before executing another instruction that accesses flash memory, before jumping to or calling program code in flash memory, and before changing the CPU core speed. It is not necessary to check the FBUSY bit if enough cycles are allowed for the flash operation to complete. See description of FRDTS1:0, FRDTC1:0 and FWRT3:0 in Section 7.1.5 for more details. Software must not attempt to execute out of flash memory while the FBUSY bit is set, because the flash memory is unreadable during that time. Therefore, code which reads, writes, or erases flash memory, using the fread, fwrite or ferase instructions, must execute from program RAM. Software must provide at least four cycles between an fread and
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IP2012 / IP2022 Data Sheet
reading DATAH/DATAL, or ensure that the minimum flash read time is met. Unlike RAM, flash memory requires an explicit erase operation before being written. The ferase instruction is used to erase a 512-byte (256-word) block of flash memory (it brings all bits to 1, see Table 4-9). After the block has been erased, individual words can be written with the fwrite instruction (fwrite will not change a 0 to 1). For example, an ferase instruction executed on any byte address from 0x10000 to 0x100FE erases the whole block spanning those addresses. The selfprogramming instructions have no access to the flash memory bits in the configuration block. Table 4-9 ferase Addresses (ADDRX=01, ADDRL=xx) ADDRH 0x00 0x02 ... 0xFE Flash Byte Addresses 0x10000 - 0x101FE 0x10200 - 0x102FE ... 0x1FE00 - 0x1FFFE
10. Wait 1 cycle after changing ADDRX bit 7, EMCFG bit 7, or ADDRSEL before executing an fread, fwrite, ferase, iread, ireadi, iwrite, or iwritei instruction. 11. Do not write to DATAH at the same time an iread of External Memory is causing a write of DATAL.
4.7.1
Flash Timing Control
The FCFG register controls the timing of flash memory operations. See Section 7.1.5 for a description of the FCFG register.
4.7.2
Interrupts During Flash Operations
Before starting a flash write or erase operation, the FCFG register (see Section 7.1.5) must be set up properly for the current speed. The CPU core clock is the time base for the flash write timing compensation, so it is critical that the CPU core clock speed is not changed during a flash write or erase operation. Interrupts may be taken during a flash write or erase operation, if the INTSPD register is set up so the speed does not change when an interrupt occurs. If the flash read timing compensation is set up for a clock divisor of 1 (i.e. fastest speed), interrupts will not cause fread/iread instructions to fail, so no special precautions need to be taken to avoid violating the flash read access time.
Rules/Troubleshooting for fread/fwrite/ferase and iread/ireadi of flash: 1. Must be executing out of program RAM, with ADDRX = 01. 2. FCFG register must be correctly configured (refer to Section 7.1.5). 3. For an fread or iread/ireadi of flash, there must be at least 3 core cycles between the read instruction and a read of DATAH or DATAL, or the minimum flash read time must be met. 4. No speed commands while fread, fwrite or ferase are busy (while XCFG bit 0 = 1). 5. Do not jump to flash memory while executing fread/fwrite/ferase. If INTVEC is in flash, ensure interrupts are disabled. 6. fwrite will not change a 0 to a 1 (use ferase first). 7. XCFG bit 0 = 0 before execution (even during ISR) or sufficient time is allowed to complete previous operations on flash. 8. XCFG bit 6 = 1, otherwise fwrite and ferase behave as nop. 9. Make sure interrupts are disabled or that the INTSPD value matches the SPDREG value. For iread or ireadi of flash from flash, a more practical solution is to jump to a routine in program RAM.
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5.0
Peripherals
The IP2012 / IP2022 provides an array of on-chip peripherals needed to support a broad range of embedded Internet applications: * * * * * * * * * 2 Serializer/Deserializer (SerDes) units (IP2012 has one unit) Real-time timer T0 timer 2 General-purpose timers with compare and capture Registers Watchdog timer 10-bit, 8-channel A/D converter Analog comparator Parallel slave peripheral interface External memory interface (IP2022 only)
IP2012). Port G supports the analog to digital converter (ADC) and the analog comparator. Before enabling a hardware peripheral, configure the port pins for input or output as required by the peripheral. Note: There is positive-feedback circuitry present on the I/O ports when configured as input. This causes an input that was previously high, then subsequently tri-stated (i.e. not driven), to be actively driven by the IP2012 / IP2022 to a voltage level of approximately 1.7V, or one diode drop below (IOVdd). See Section 8.2 for details. Figure 5-1 shows the internal hardware structure and configuration registers for each pin of a port.
All of the peripherals except the Watchdog Timer and the Real-Time Timer use alternate functions of the I/O port pins to interface with external signals.
RxDIR Register 0 = Output 1 = Hi-Z Input RxOUT Register Port Pin
The IP2022 contains one 4-bit I/O port (Port A) and six 8bit I/O ports (Port B through Port G). The IP2012 contains one 4-bit I/O port (Port A), two 6-bit I/O ports (Ports D and F) and four 8-bit I/O ports (Ports B, C, E, and G). The four Port A pins have 24 mA current drive capability. All the ports have symmetrical drive. Inputs are 5V-tolerant. Outputs can use the same 2.3-2.7V power supply used for the CPU core and peripheral logic, or they can use a higher voltage (up to 3.6V). The IOVdd pins are provided for the I/O port pin output drivers. Port G has a separate GVdd pin which can be used to run the Port G output drivers at a voltage different from that used for the other ports, since Port G must run from a 2.3-2.7V power supply. Each port has separate input (RxIN), output (RxOUT), and direction (RxDIR) registers, which are memory mapped. The numbers in the pin names correspond to the bit positions in these registers. These registers allow each port bit to be individually configured as a general-purpose input or output under software control. Unused pins should be configured as outputs, to prevent them from floating. Port B has three additional registers for supporting external interrupts (see Section 5.1.1). Each port pin has an alternate function used to support the on-chip hardware peripherals, as listed in Table 2-1. Port A and Port B support the multi-function timers Timer 1 and Timer 2. On the IP2022, Port B, Port C, and Port D support the Parallel Slave Peripheral (PSP) and external memory functions. On the IP2012, Port B and Port C support the PSP. Port E and Port F support the serializer/deserializer (SERDES) units (only Port E on the
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Data Bus
5.1
I/O Ports
SYNC bit (FUSE1) SYNC bit set
1
RxIN Register
M U X
0
SYNC bit clear FF FF
515-030a.eps
Core Clock
Figure 5-1 Port Pin Block Diagram
5.1.1
Port B Interrupts
Any of the 8 Port B pins can be configured as an external interrupt input. Logic on these inputs can be programmed to sense rising or falling edges. When an edge is detected, the interrupt flag for the port pin is set. The recommended initialization sequence is: 1. Configure the port pins used for interrupts as inputs by programming the RBDIR register. 2. Be sure all enabled interrupt pins are driven to valid logic levels, not floating. 3. Select the desired edge for triggering the interrupt by programming the INTED register. This may set interrupt flags. 4. nop, nop. 5. Clear the interrupt flags in the INTF register.
6. nop
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IP2012 / IP2022 Data Sheet
7. Enable the interrupt input(s) by setting the corresponding bit(s) in the INTE register. 8. Set the GIE bit. Figure 5-2 shows the Port B interrupt logic. Port B has three registers for supporting external interrupts, the INTED (Section 5.1.6), INTF (Section 5.1.7), and INTE (Section 5.1.8) registers. The INTED register controls the logic which selects the edge sensitivity (i.e. rising or falling
edge) of the Port B pins. When an edge of the selected type occurs, the corresponding flag in the INTF register is set, whether or not the interrupt is enabled. The interrupt signal passed to the system interrupt logic is the OR function of the AND of each interrupt flag in the INTF register with its corresponding enable bit in the INTE register. See Section 5.1.8.
RB7
RB6
RB1
RB0 INTED Register INTF Register
Data Bus
Port B Interrupt INTE Register
515-031.eps
Figure 5-2 Port B Interrupt Logic
5.1.2
Reading and Writing the Ports
5.1.3
RxIN Registers
The port registers are memory-mapped into the data memory address space between 0x020 and 0x03A. In addition, Port B has three extra registers located at 0x017 through 0x019 (INTED, INTF, and INTE), which support external interrupt inputs. Generally, successive read and write operations on the same I/O port is not an issue, as there are separate IN an OUT registers for each I/O port. Care must be given to ensure that enough time is allowed for data written to the OUT register to propagate to the IN register on a given port. If this is an issue, two instructions (or four instructions if the SYNC bit in the FUSE1 register is clear) should be inserted between any read-modify-write instruction sequences (or more nop instructions if the pin is capacitively loaded).
The RxIN registers are virtual registers that provide readonly access to the physical I/O pins. Reading these registers returns the states on the pins, which may be driven either by the IP2012 / IP2022 or an external device. If the SYNC bit in the FUSE1 register is clear, the states are read from a synchronization register. If an application reads data from a device running asynchronously to the IP2012 / IP2022, the SYNC bit should be cleared to avoid the occurrence of metastable states (i.e. corrupt data caused by an input which fails to meet the setup time before the sampling clock edge, which theoretically could interfere with the operation of the CPU).
5.1.4
RxOUT Registers
The RxOUT registers are data output buffer registers. The data in these registers is driven on any I/O pins that are configured as outputs. On reads, the RxOUT registers return the data previously written to the data output buffer registers, which might not correspond to the states
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actually present on pins configured as inputs or pins forced to another state by an external device.
5.1.7
INTF Register
5.1.5
RxDIR Registers
The RxDIR registers select the direction of the port pins. For each output port pin, clear the corresponding RxDIR bit. For each input port pin, set the corresponding RxDIR bit. Unused pins that are left open-circuit should be configured as outputs, to keep them from floating. For example, to configure Port A pins RA3 and RA2 as outputs and RA1 and RA0 as inputs, the following code could be used:
mov w,#0x03 ;load W with the value 0x03 ;(bits 3:2 low, and bits 1:0 ;high) ;write 0x03 to RADIR ;register
The INTF register consists of 8 interrupt flags that correspond to the 8 pins of Port B. If the trigger condition for a Port B pin occurs, the corresponding bit in the INTF register is set. The bit is set even if the port pin is not enabled as a source of interrupts. The interrupt service routine (ISR) can check this register to determine the source of an external interrupt. If a Port B pin enabled for generating interrupts has a set bit in the INTF register, software must clear the bit prior to exiting to prevent repeated calls to the ISR. The Port B interrupt logic is asynchronous (e.g. functions without a clock in clock-stop mode). A side effect is that there is a 2-cycle delay between the instruction that clears a INTF bit and the bit being cleared. This means that software must clear the bit at least 2 cycles before executing a return from interrupt (reti) instruction.
mov
0x022,w
The second move instruction in this example writes the RADIR register, located at address 0x022. Because Port A has only four I/O pins, only the four least significant bits of this register are used. To drive the RA1 pin low and the RA0 pin high, the following code then could be executed:
mov w,#0x01 ;load W with the value 0x01 ;(bits 3:1 low, and bit 0 ;high) ;write 0x01 to RAOUT ;register
5.1.8
INTE Register
The INTE register consists of 8 interrupt enable bits that correspond to the 8 pins of Port B. A Port B pin is enabled as a source of interrupts by setting the corresponding bit in the INTE register. The pin is disabled as an interrupt source by clearing the corresponding INTE bit, but takes up to 1 core clock cycle for the interrupt to be disabled.
mov
0x021,w
5.1.9
Port Configuration Upon Power-Up
The second move instruction shown above writes the RAOUT register, located at address 0x021. When reading the Port A pins through the RAIN register (0x020), the upper four bits always read as zero. When a write is performed to the RxOUT register of a port pin that has been configured as an input, the write is performed but it has no immediate effect on the pin. If that pin is later configured as an output, the pin will be driven with the data that had been previously written to the RxOUT register.
On power-up, all the port control registers (RxDIR) are initialized to 0xFF. Therefore, each port pin is configured as a high-impedance input. This prevents any false signalling to external components which could occur if the ports were allowed to assume a random configuration at power-up.
5.2
Timer 0
5.1.6
INTED Register
The INTED register consists of 8 edge detection bits that correspond to the 8 pins of Port B. A set bit in the INTED register makes the corresponding port pin trigger on falling edges, while a clear bit makes the pin trigger on rising edges.
Timer 0 is an 8-bit timer with an 8-bit prescaler intended to generate periodic interrupts for ipModuleTM instances that require being called at a constant rate, such as UART and DTMF functions. When the T0TMR register counts up to FF and rolls over to 00, the T0IF flag in the T0CFG register will be set, and an interrupt will occur if the T0IE and T0EN bit are set (see T0CFG register description in Section 7.1.20). To clear the interrupt, either the T0IE or T0EN bit should be cleared, and then the T0IF flag must be cleared. Note: If T0IF is not cleared after disabling the Timer0 interrupt (T0IE = 0) or disabling Timer0 (T0EN = 0), it is assumed that another interrupt has occurred, and the
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IP2012 / IP2022 Data Sheet
interrupt will occur on the next return, or when GIE is set (enabling nested interrupts - see Section 3.7.2). The Timer 0 interrupt is also supported in the instruction set by an option for the reti instruction which adds the W register to the T0TMR register when returning from an interrupt. Figure 5-3 shows the Timer 0 logic. Operation of Timer 0 to generate periodic interrupts: * * * T0TMR = 00 when entering ISR from T0 interrupt Keeps counting up while in ISR Add W to T0TMR with execution of reti (refer to Table 3-5). Interrupt frequency is adjusted by adjusting value loaded in W, and depending on core clock divider, since T0TMR runs on the system clock. If W added to T0TMR exceeds 0xFF, no interrupt is taken until the T0TMR rolls over from 0xFF to 0x00 again. If the T0TMR rolls over during the 3 core cycles in the return from interrupt, the ISR is executed again (and never again returns to mainline code as long as the ISR executes the same).
from the Real-Time Timer. By using an interrupt rather than reset, more of the CPU state is preserved and some reset procedures such as initializing the port direction registers can be skipped. Figure 5-4 shows the Real-Time Timer logic. (When RTCLK1 is not used, it should be tied to GND.) When the RTTMR register counts up to FF and rolls over to 00, the RTIF flag in the RTCFG register will be set, and an interrupt will occur if the RTIE and RTEN bit are set (see RTCFG register description in Section 7.1.9). To clear the interrupt, either the RTIE or RTEN bit should be cleared, and then the RTIF flag be cleared. Note: A nop is required between a speed instruction and an instruction that enables or writes to RTTMR. Note: If RTIF is not cleared after disabling the Real-Time Timer interrupt (RTIE = 0) or disabling the Real-Time Timer (RTEN = 0), it is assumed that another interrupt has occurred, and the interrupt will occur on the next return, or when GIE is set (enabling nested interrupts - see Section 3.7.2). Note: The system clock must be slower or equal to the RTCLK clock, for a write to the RTTMR to work correctly. The real-time timer is readable and writable as the RTTMR register. The control and status register for the timer is the RTCFG register, as described in Section 7.1.9. The RTEOS bit (XCFG bit 5, see Section 7.1.26) selects the sampling mode for the external input. If the RTEOS bit is set, the external input is over-sampled with the system clock. The CPU can always read the value in the RTTMR register, if the system clock is at least twice the frequency of the external input. If the system clock source is changed to RTCLK or turned off, then the RTEOS bit must be clear for the Real-Time Timer to function. Note: if the RTEOS bit is cleared, expect a 3 cycle system clock delay for the overflow interrupt, due to synchronization circuitry. If the RTEOS bit is clear then the external input directly clocks the Real-Time Timer (i.e. RTCLK is not oversampled). The Real-Time Timer will always function whether the clock input is synchronous or asynchronous. However, the CPU cannot reliably read the value in the RTTMR register unless the RTCLK clock is synchronous to the system clock (RTEOS=1). If the value in the RTTMR register does not need to be used by the CPU (i.e. only the interrupt flag is of interest), then the RTEOS bit should be clear (i.e. RTCLK not oversampled), which allows the Real-Time Timer to function for any configuration of the system clock.
Note: Do not enable Timer 0 interrupt before enabling the Timer 0 itself.
T0PS 3:0 T0EN T0IE
System Clock
8-Bit Prescaler
8-bit T0TMR Register 8
T0IF
Data Bus
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Figure 5-3 Timer 0 Block Diagram The control and status register for Timer 0 is the T0CFG register, described in detail in Section 7.1.20. Note: T0IF can only be asserted when T0IE = 1, T0EN = 1 and T0TMR overflow occurs.
5.3
Real-Time Timer (RTTMR)
The Real-Time Timer is an 8-bit timer intended to provide a periodic system wake-up interrupt. Unlike the other peripherals (except the Watchdog Timer and Port B interrupts), the Real-Time Timer continues to function when the system clock is disabled. For those applications which spend much of their time with the OSC clock oscillator turned off to conserve power, there are 5 available mechanisms to exit this mode: external reset (RST pin), reset from the Watchdog Timer, reset from Brown-out, interrupt from a Port B input, and interrupt
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If the value in the RTTMR register needs to be used by the CPU, but the Real-Time Timer is not required to function when the system clock is set to RTCLK or turned off, then the RTEOS bit should be set to ensure the CPU can reliably read the RTTMR register. If the value in the RTTMR register needs to be used by the CPU and the Real-Time Timer is required to function when the system clock is set to RTCLK or off, then software must change the RTEOS bit when changing the system clock source. To read the RTTMR register when the system clock is not synchronous to the RTCLK, the RTEOS bit must be set to ensure reliable operation. Before the system clock is changed to RTCLK or turned off, the RTEOS bit must be clear (i.e. RTCLK not oversampled) for the Real-Time Timer to continue to function. Note: When using development tools in single stepping mode, the RTSS bit must be cleared and RTEOS must be set, otherwise the counter will behave erratically. Note: Care must be exercised if Port B interrupts and RTTMR interrupts are enabled, because the RTTMR may receive sporadic clocks during crystal startup while the system clock is waiting for WUDX2:0 (see Figure 3-17).
RTEOS "1" RTSS OSC1 0 0 RTCLK1 1 1 System Clock RTEOS One Shot 0 1
Enable CLK RTTMR
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Figure 5-4 Real-Time Timer Block Diagram
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5.4
Multi-Function Timers (T1 and T2)
System Clock RA2 for T1 RB2 for T2 TxCLK D System Clock Q TxCNTH/TxCNTL Register TxCFG1L bit 6 (OEN) RAOUT bit 3 for T1 RBOUT bit 3 for T2 0 TxCPI1 RA0 for T1 RB0 for T2 TxOUT TxCAP1H/TxCAP1L Register TxCMP1H/TxCMP1L Register 1 TxCAP2H/TxCAP2L or TxCMP2H/TxCMP2L Register
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15-Bit Prescaler
RA3 for T1 RB3 for T2
TxCPI2 RA1 for T1 RB1 for T2
Figure 5-5 Multifunction Timer Block Diagram The IP2012 / IP2022 contains two independent 16-bit multi-function timers, called T1 and T2 (notated below as Tx). These versatile, programmable timers reduce the software burden on the CPU in real-time control applications such as PWM generation, motor control, triac control, variable-brightness display control, sine-wave generation, and data acquisition. Each timer consists of a 16-bit counter register supported by a dedicated 16-bit capture register and two 16-bit compare registers. The second compare register can also serve as capture register. Each timer may use up to four external pins: TxCPI1 (Capture Input), TxCPI2 (Capture Input), TxCLK (Clock Input), TxOUT (Output). These pins are multiplexed with general-purpose I/O port pins. The port direction register has priority over the timer configuration, so the port direction register must be programmed appropriately for each of these four signals if their associated timer functions are used. Figure 5-5 is a block diagram showing the registers and I/O pins of one timer. Each timer is based on a 16-bit counter/timer driven by a 15-bit prescaler. The input of the prescaler can be either the system clock or an external clock signal which is internally synchronized to the system clock. The counter cannot be directly written by software, but it may be cleared by writing to the TxRST bit in the TxCTRL register. * * * Pulse-Width Modulation (PWM) Timer Capture/Compare
PWM Mode In PWM Mode, the timer can generate a pulse-width modulated signal on its output pin, TxOUT. The period of the PWM cycle (high + low), in number of system clocks, is specified by the value in the TxCAP2H/TxCAP2L register. The high time of the pulse is specified by the value in the TxCMP1H/TxCMP1L register. PWM mode can be used to generate an external clock signal that is synchronous to the IP2012 / IP2022 system clock. For example, by loading TxCMP1H/TxCMP1L with 1 and TxCAP2H/TxCAP2L with 2 (the high registers must be written last for this to work), a symmetric external clock can be generated at the frequency of the system clock. In some applications, this can eliminate crystals or oscillators required to produce clock signals for other components in the system. SerDes GPSI mode can also produce clock outputs. The 16-bit counter/timer counts upward, starting with the TxOUT output driven high. After reaching the value stored in the TxCMP1H/TxCMP1L register minus one, at the next clock edge the TxOUT pin is driven low. The counter/timer is unaffected by this event and continues to increment. After reaching the value stored in the TxCAP2H/TxCAP2L register minus one, at the next clock edge the timer is cleared. When the counter is cleared, the TxOUT output is driven high, unless the TxCMP1H/TxCMP1L register is clear, in which case the TxOUT pin is driven low.
5.4.1
Timers T1, T2 Operating Modes
Each timer can be configured to operate in one of the following modes:
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There are two special cases. When the TxCMP1H/TxCMP1L register is clear, the TxOUT pin is driven with a continuous low, corresponding to a dutycycle of 0%. When the value in the TxCMP1H/TxCMP1L register is equal to the value in the TxCAP2H/TxCAP2L register, the TxOUT output is driven with a continuous high, corresponding to a duty-cycle of 100%. The behavior of the timers is undefined when the value in the TxCMP1H/TxCMP1L register is greater than the value in the TxCAP2H/TxCAP2L register. The timer is glitch-free no matter when the TxCMP1H/TxCMP1L register or the TxCMP2H/TxCMP2L register are changed relative to the value of the internal counter/timer. The new duty cycle or period values do not take effect until the current PWM cycle is completed (the counter/timer is reset). Interrupts, if enabled through the TxCFG1H register, can be generated whenever the timer output is set or cleared. If the TxCMP1H/TxCMP1L register is clear, or if the value in the TxCMP1H/TxCMP1L register is equal to the value in the TxCAP2H/TxCAP2L register, an interrupt can be generated each time the counter/timer is reset to zero. In PWM mode, the Capture 1 input remains active (if enabled by the CPI1EN bit in the TxCFG1L register) and, when triggered, captures the current counter/timer value into the TxCAP1 register. The multifunction timers can be configured to interrupt on a Capture 1 event and reset the counter/timer on the event. For PWM operation without Capture 1, software must disable the Capture 1 input by clearing the CPI1EN bit in the TxCFG1L register. Timer Mode This is not a separate timer mode (from the hardware point of view), but is a conceptual mode for programmers. It is the PWM mode, except that software disables the timer output by clearing the OEN bit in the TxCFG register. Capture/Compare Mode In Capture/Compare mode, one or both of the timer capture inputs (TxCPI1 and TxCPI2) may be used. Their pin functions must be enabled in the TxCFG1 register. Each capture input can be programmed in the TxCFG2 register to trigger on a rising edge, falling edge, or both rising and falling edges. When a trigger event occurs on either capture pin, the current value of the counter/timer is captured into the TxCAP1H/TxCAP1L register or the TxCAP2H/TxCAP2L register for that input pin. The counter/timers can also be configured to reset on a TxCPI1 input event, in which case the value of the
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counter/timer before it was reset is captured in the TxCAP1H/TxCAP1L register and the counter/timer is reset to zero. This mode is useful for measuring the frequency (or width) of external signals. By using both capture inputs and configuring them for opposite edges, the duty cycle of a signal can also be measured. To avoid wasting I/O port pins in this configuration, the CPI2EN bit in the TxCFG1L register is provided to internally tie the TxCPI1 and TxCPI2 inputs together, which frees the TxCPI2 pin to be used as a general-purpose I/O port pin. An interrupt can be generated for any capture event and for counter/timer overflows. This mode also features an output-compare function. The TxCMP1H/TCMP1L register is constantly compared against the internal counter/timer. When the counter/timer reaches the value of the TxCMP1H/TxCMP1L register minus one, at the next counter clock the TxOUT output is toggled. The TxOUT output, if enabled via the OEN bit, can be driven high or low by writing to the TOUTSET and TOUTCLR bits in the TxCFG2L register. An interrupt can be enabled for this event. Interrupts When a Multi-Function Timer interrupt occurs, the corresponding interrupt flag (depending on the mode; OFIF, CAP2IF/CMP2IF, CAP1IF or CMP1IF) in the TxCFG1H register will be set, and an interrupt will occur if the TMREN bit (TxCFG1L register), the TxIE bit (TCTRL register) and an interrupt source is enabled (depending on the mode; OFIE, CAP2IE/CMP2IE, CAP1IE or CMP1IE) are set (TxCFG1H register). To clear the interrupt, either the TMREN bit, TxIE bit or the interrupt source (OFIE, CAP2IE/CMP2IE, CAP1IE or CMP1IE) should be cleared, and then the interrupt flag (OFIF, CAP2IF/CMP2IF, CAP1IF or CMP1IF) should be cleared. Note: The interrupt flag can only be asserted when the multi-function timers are enabled, the timer interrupts are enabled, an interrupt source is enabled, and timer event occurs. Note: If the interrupt flag is not cleared after disabling either the interrupt enable or the Multi-Function Timer enable (TMREN = 0), it is assumed that another interrupt has occurred, and the interrupt will occur on the next return, or when GIE is set (enabling nested interrupts see Section 3.7.2).
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5.4.2
T1 and T2 Timer Pin Assignments
TxCAP1H/TxCAP1L Register The TxCAP1H/TxCAP1L register captures the value of the counter/timer when the TxCPI1 input is triggered. This register is read-only. Reading the TxCAP1L register returns the leastsignificant 8 bits of an internal capture register and causes the most-significant 8-bits of the register to be latched into the TxCAP1H register. This allows software to read the TxCAP1H register later and still be assured of atomicity. TxCMP1H/TxCMP1L Register In Capture/Compare mode, the TxOUT output pin is toggled (if enabled by the OEN bit in the TxCFG1 register) when the counter/timer increments to the value in the TxCMP1 register. In this mode, the value written to the TxCMP1 register takes effect immediately. Writing to the TxCMP1L register causes the value to be stored in the TxCMP1L register with no other effect. Writing to the TxCMP1H register causes an internal compare register to be loaded with a 16-bit value in which the low 8 bits come from the TxCMP1L register and high 8 bits come from the value being written to the TxCMP1H register. Software should write the TxCMP1L register before writing the TxCMP1H register, because writing to the TxCMP1H register is used as an indication that a new compare value has been written. Writing to the TxCMP1H register is required for the new compare value to take effect - this means that TxCMP1H must be written AFTER TxCMP1L for the value to have any effect. In PWM mode, the 16-bit number latched into the internal compare register by writing to the TxCMP1H register does not take effect until the end of the current PWM cycle. Reading the TxCMP1H or TxCMP1L registers returns the previously written value whether or not the value stored in these registers has been transferred to the internal compare register by writing to the TxCMP1H register. TxCAP2H/TxCAP2L or TxCMP2H/TxCMP2L Register This register may be called the TxCAP2H/TxCAP2L register or TxCMP2H/TxCMP2L register. In PWM mode, this register determines the period of the PWM signal. In this mode, this register is both readable and writable. However, on writes the value is not applied until the end of the current PWM cycle. Writing to the TxCAP2L register causes the value to be stored in the TxCAP2L register with no other effect. Writing to the TxCAP2H register causes an internal compare register to be loaded with a 16-bit value in which the low 8 bits come from the TxCAP2L register and the high 8 bits come from the value being written to the TxCAP2H register. Software should write the TxCAP2L
The following table lists the I/O port pins associated with the Timer T1 and Timer T2 I/O functions. Table 5-1 Timer T1/T2 Pin Assignments I/O Pin RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 Timer T1/T2 Function Timer T1 Capture 1 Input Timer T1 Capture 2 Input Timer T1 External Event Clock Source Timer T1 Output Timer T2 Capture 1 Input Timer T2 Capture 2 Input Timer T2 External Event Clock Source Timer T2 Output
5.4.3
T1 and T2 Timer Registers
Each timer has six 16-bit register pairs, which are accessed as 8-bit registers in the special-purpose register space. There is also one 8-bit register shared by both timers. TxCNTH/TxCNTL Register The TxCNTH/TxCNTL register indicates the value of the counter/timer and increments synchronously with the rising edge of the system clock. This register is read-only. The timer counter may be cleared by writing to the TxRST bit in the TCTRL register. Reading the TxCNTL register returns the least-significant 8 bits of the internal TxCNT counter and causes the mostsignificant 8 bits of the counter to be latched into the TxCNTH register. This allows software to read the TxCNTH register later and still be assured of atomicity.
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register before writing the TxCAP2H register, because writing to the TxCAP2H register is used as an indication that a new compare value has been written. Writing to the TxCAP2H register is required for the new compare value to take effect. In PWM mode, the 16-bit number latched into the internal compare register by writing to the TxCAP2H register does not take effect until the end of the current PWM cycle. Reading the TxCAP2H or TxCAP2L registers returns the previously written value regardless of whether the value stored in these registers has been transferred to the internal compare register by writing to the TxCAP2H register. In Capture/Compare mode, this register captures the value of the counter/timer when the TxCPI2 input is triggered. In this mode, this register is read-only. Reading the TxCAP2L register returns the leastsignificant 8 bits of an internal capture register and causes the most-significant 8-bits to be latched into the TxCAP2H register. This allows software to read the TxCAP2H register later and still be assured of atomicity. TxCFG1H/TxCFG1L Register Selects timer operation mode, pin functions, interrupts and other configuration settings. See Section 7.1.21 for the description of TxCFG1H and Section 7.1.23 for the description of TxCFG1L. TxCFG2H/TxCFG2L Register Selects capture input trigger edges, prescaler setting, and other configuration settings. See Section 7.1.22 for the description of TxCFG2H and Section 7.1.24 for the description of TxCFG2L. TCTRL Register Unlike the other timer control registers, one TCTRL register is used to synchronize both timers. Setting the TxRST bit clears the TxCNTH/TxCNTL register pair and the prescaler counter, which allows global synchronization of all timers on the device. There are also individual timer interrupt-enable bits. See Section 7.1.25 for description.
5.5
Watchdog Timer (WDT)
A Watchdog Timer (WDT) is available for recovering from unexpected system software hang-ups. When the Watchdog Timer is enabled, software must periodically clear the timer by executing a cwdt instruction. Otherwise, the timer will overflow, which resets the IP2012 / IP2022 but doesn't clear the WD bit in the PSPCFG register (this bit should be set before the first cwdt instruction is executed). Any other source of reset clears the WD bit, so software can use this bit to identify a reset caused by the Watchdog Timer. The Watchdog Timer is shown in Figure 5-6.
WDTE
WDPS 2:0
cwdt Instruction
Internal RC Clock (14 kHz)
Prescaler
8-Bit Timer
Watchdog Timer Reset
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Figure 5-6 Watchdog Timer The Watchdog Timer is enabled by setting the WDTE bit in the FUSE1 register. The time period between coming out of reset or clearing the timer and timer overflow is controlled by the WDPS2:0 bits in the FUSE1 register, as discussed in Section 3.10.2. Since the watchdog timer period varies by up to 50% over temperature and voltage, the minimum timeout period selected in FUSE1 that works in nominal conditions, should not be used. For instance, if the 640ms setting works in nominal conditions, the 1280ms setting should be used in production. The Watchdog Timer register is not visible to software. The only feature of the Watchdog Timer visible to software is the WD bit in the PSPCFG register (see Section 7.1.8). Note: When using the development tools, the watchdog timer is disabled while in debug mode, except when "Run" command is issued. The break and breakx instructions suspend the Watchdog Timer, so that debug mode works correctly. Therefore, if the watchdog feature is used, the break and breakx instructions should not be used, and the program RAM should be initialized to instructions that do not include break and breakx.
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5.6
Serializer/Deserializer (SERDES)
Regardless of the number of bits to be transmitted, both the high and low registers need to be written to initiate transmission.
There are two SERDES units in the IP2022 (one unit in the IP2012), which support a variety of serial communication protocols, including GPSI, SPI, UART, USB, and 10Base-T Ethernet. By performing data serialization/deserialization in hardware, the CPU bandwidth needed to support serial communication is greatly reduced, especially at high baud rates. Providing two units allows easy implementation of protocol conversion or bridging functions between the two highspeed serial interfaces, such as a USB to 10Base-T Ethernet bridge. Each SERDES unit uses up to 8 external digital signals: SxCLK, SxRXD, SxRXM, SxRXP, SxTXM, SxTXME, SxTXP, and SxTXPE/SxOE. The signals for SERDES1 are multiplexed with the Port E pins, and the signals for SERDES2 are multiplexed with the Port F pins (IP2022 only). The port direction bits must be set appropriately for each pin that is used. Not all signals are used in all protocol modes. See Table 5-3 for details on signal port pin usage in various protocol modes. In addition to the digital signals, there are also two analog signals only used in 10Base-T Ethernet mode: SxRX+ and SxRX-. Note: Proper operation of the SERDES requires that the core-clock be present -- don't turn off core clock while SERDES is still transmitting. SERDES Configuration Registers The descriptions for the SxMODE, SxRSYNC, SxSMASK, SxRCFG, SxRCNT, SxTCFG, SxTMRH/SxTMRL and SxINTE/SxINTF registers can be found in Section 7.1. Note: A one cycle delay is required between consecutive read-modify-write instructions to the same SERDES register (for example, clrb reg and setb reg)
5.6.2
SERDES Configuration
Software prepares a SERDES unit to receive data by programming the receive shift count register (SxRCFG) and the clock select bits in the SxMODE register appropriately for the selected protocol. The SxRCFG register is copied to an internal counter, and when that number of bits of data has been received, the received data is loaded into the SxRBUF register. In 10Base-T, GPSI, or USB mode, when an EOP is detected, the SxRCNT register is loaded with the number of bits actually received, the EOP bit of the SxINTF register is set, and the data bits are loaded into the SxRBUF register. The RXBF bit in the SxINTE register can be set to enable an interrupt on this event. The SxTXP and SxTXM pins correspond to the differential outputs of the USB or Ethernet bus. Other serial protocols require only one output pin, which is SxTXP by default. The SxTXP and SxTXM pins have high current outputs for driving Ethernet magnetics directly without the use of transceivers. When the clock select register is programmed with the value for 10Base-T, the transmit pre-emphasis requirement enables the SxTXPE and SxTXME outputs, which have a 50ns-delayed version of the transmit output that is resistively combined outside the chip before driving the magnetics. For transmitting, software must specify the number of bits to transmit (specified in the SxTCFG register) and load the data in the SxTBUF register. This data is then transferred to an internal register, from which it is serially shifted out to the transmit logic. The TXBE bit in the SxINTE register can be set to enable an interrupt when the data has been transferred from the SxTBUF register. When there is a transmit buffer underrun event (i.e. all of the data has been shifted out from the internal register, but the SxTBUF register has not been reloaded), an EOP condition is generated on the SxTXP and SxTXM outputs after an internal counter decrements to zero. The TXEOP bit in the SxINTE register can be set to enable an interrupt when an underrun event occurs. For protocols other than USB and Ethernet, the EOP generator is bypassed.
5.6.1
SERDES TX/RX Buffers
SxRBUFH/SxRBUFL Registers 16-bit register pair for unloading received data. The RXBF bit in the SxINTF register indicates when new data has been loaded into this register. If the corresponding bit in the SxINTE register is set, an interrupt is generated. SxTBUFH/SxTBUFL Registers 16-bit register pair for loading data to be transmitted. The TXBE bit in the SxINTF register indicates when the data has been transmitted and the register is ready to be loaded with new data. If the corresponding bit in the SxINTE register is set, an interrupt is generated.
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5.6.3
SERDES Interrupts
Figure 5-7 shows the interrupt logic for the two SERDES units. For a detailed description of the SxINTE/SxINTF register bits, refer to Section 7.1.10.
S0INTF Register
S0INTE Register
S1INTF Register
Serializer/ Deserializer Interrupt S1INTE Register
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Figure 5-7 SERDES Interrupt Logic
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5.6.4
Protocol Modes
Table 5-2 shows the features which are enabled for each protocol, as controlled by the PRS3:0 bits in the SxMODE
register. These features affect which registers and register fields are used, for example the SxRSYNC register is only used in the USB and 10Base-T modes. The protocol mode also affects the signal usage, as shown in Table 5-3.
Table 5-2 Protocol Features PRS3:0 0001 0010 0011 0101 0110 Mode Encoding Method EOP Differential or Synchronization Generation/ Register Single-Ended? Enabled? Detection? Differential Differential Single-Ended Single-Ended Single-Ended Yes Yes No No No Yes Yes N/A Yes Yes Bit Pre-Emphasis Stuffing/ Outputs Unstuffing? Enabled? N/A Yes N/A N/A N/A Yes N/A N/A N/A N/A
10Base-T Manchester USB Bus UART SPI GPSI NRZI None None None
Table 5-3 SERDES Protocol Modes And Pin Usage Signal Names SERDES1 Pins SERDES2 Pins (IP2022 only) 10Base-T Ethernet USB Bus UART Mode SPI Master Slave Master GPSI Slave SxCLK RE0 RF4 Optional Optional SCLK SCLK RxCLK (I) SxRXP RE1 RF5 VP (I) SS (I) TxEN (O) TxEN (O) SxRXM SxRXD SxTXPE SxTXP RE2 RF6 VM (I) RE3 RF7 RXD Note 1 RCV (I) RXD DI (I) DI (I) TxD (O) TxD (O) RE4 RF0 TxD+ (O) RxEN (I) RxEN (I) RE5 RF1 Tx+ (O) TXD DO (O) DO (O) RxD (I) RxD (I) SxTXM RE6 RF2 Tx(O) SxTXME SxRX+ SxRXRE7 RF3 TxD(O) RG5 RG7 RX+ (I) RG4 RG6 RX(I) -
OE (O) VPO (O) VMO (O)
TxCLK/ TxBUSY RxCLK (O) (I) TxCLK (I) TxBUSY (I)
1. Used in comparator mode only. I. Input O. Output
Pins not used for protocols can be used for general I/O. * SxCLK - Serial Clock in SPI or GPSI Slave modes, optional external SERDES clock input for USB or UART modes. SxRXP - Positive-side differential input (USB only), Slave Select (for SPI Slave), or data valid (GPSI). SxRXM - Negative-side differential input (USB only). SxRXD - Serial data for USB, UART, SPI and GPSI modes (10base-T Ethernet only when comparator is used). SxTXPE - Positive-side delayed differential output for pre-emphasis (10base-T Ethernet), output enable for external transceiver (USB), or data valid for GPSI mode.
*
*
* * *
*
* *
*
SxTXP - Positive-side differential output (10base-T Ethernet and USB modes), or serial data (UART, SPI and GPSI modes). SxTXM - Negative-side differential output (10base-T Ethernet and USB modes), transmit clock (GPSI Slave), or transmit and receive clock (GPSI Master). SxTXME - Negative-side delayed differential output for pre-emphasis (10base-T Ethernet), or TxBUSY in GPSI mode. SxRX+ - Positive-side analog differential input, used for 10base-T Ethernet squelch function. SxRX- - Negative-side analog differential input, used for 10base-T Ethernet squelch function.
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5.6.5
10base-T Ethernet
Hardware Each SERDES unit provides 4 transmission digital signals: SxTXM, SxTXME, SxTXP, and SxTXPE. These signals for SERDES1 are multiplexed with the Port E pins, and the signals for SERDES2 (IP2022 only) are multiplexed with the Port F pins. The differential receive signals are multiplexed on port G pins for 10Base-T Ethernet mode: SxRX+ and SxRX-. The port direction bits must be set appropriately for each pin that is used. Other unused pins from SERDES and port G remain available for other functions usage. See Table 5-4 for details on signal port pin usage in various protocol modes. Note: Proper operation of the 10Base-T requires that the core-clock be present as SERDES master clock is derived from it - don't turn off core clock while SERDES is still transmitting. Figure 5-8 shows the clock/data separation and End-ofPacket (EOP) detection logic of a 10Base-T receiver unit. The SxRXP and SxRXM pins correspond to the differential inputs. Providing both inputs allows sensing of an EOP condition. To set up a SERDES unit for 10Base-T Ethernet, the input data from a differential line receiver is connected to the SxRX+ and SxRX- input. The signals designated Tx+, Tx-, TxD+, and TxD- correspond to the SxTXP, SxTXM, SxTXPE, and SxTXME pins of the corresponding SERDES. These pins are connected to an RJ45 jack through a transformer with terminations.
Receive Polarity Reversal Bit SxRXD Input post-PLL Clock OSC Clock SxCLK Data Receive Data
For 10Base-T Ethernet operation, each SERDES is equipped with a squelch circuit for discriminating between noise, link pulses, and data. Link pulses are sent periodically to keep the channel open when no data is being transmitted. The squelch circuit handles link pulse detection, link pulse polarity detection, carrier sense, and EOP detection. The 10Base-T mode requires only a fixed SFD (start of frame) pattern, so the SFD pattern for 10Base-T is hardwired to be 11010101 and the synchronization pattern register (SxRSYNC) is used to configure features of 10Base-T other than SFD pattern. Refer to Section 7.1.14 for detailed information. The incoming data stream, after passing through the polarity inversion logic (which can be turned on or off under software control) is compared to the synchronization pattern. Once a match is found, an internal counter is set to zero and data is shifted into a shift register. The synchronization matching operation is then disabled until an EOP condition is detected, because the synchronization pattern potentially could be embedded in the data stream as valid data.
SxMODE
Clock/Data Separation and Start Condition Detection
SxRx+ SxRx-
Ethernet Squelch Circuit
Synchronization Pattern Register (SxRSYNC) EOP
515-003e.eps
EOP Detection
Figure 5-8 Clock/Data Separation and EOP Detection Figure 5-9 shows an example circuit. RTXPE, RTXME, RTXP, RTXM and RL values vary depending on the Ethernet magnetics used. Please refer to IP2022 Native Ethernet application notes for more details.
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IP2012 / IP2022 Data Sheet
Table 5-4 10base-T Ethernet Interface Signal and Port Pin Usage 10base-T Signal Name Tx+ TxTxD+ TxDRx+ RxSERDES2 SERDES SERDES1P Pin Name Signal Name in Name (IP2022 only) SxTXP SxTXM SxTXPE SxTXME SxRX+ SxRXRE5 RE6 RE4 RE7 RG5 RG4 RF1 RF2 RF0 RF3 RG7 RG6 Direction Output Output Output Output Input Input Description Plus-side differential output Minus-side differential output Plus-side differential output with preemphasis Minus-side differential output with preemphasis Plus-side analog differential input, used for 10base-T Ethernet squelch function Minus-side analog differential input, used for 10base-T Ethernet squelch function
IP2022 or IP2012
Serializer/Deserializer Manchester coding Data Encoder SxTXPE TxD+ Rtxpe SxTXP Tx+ Rtxp Ethernet Magnetics (LPF required)
RL
RJ45
SxTXME TxD- Rtxme SxTXM TxRtxm
Clock recovery Data Manchester Decoder decoding
SxRX+ Squelch SxRX-
Rx+ Rx515-064d.eps
Figure 5-9 Ethernet Interface Example Figure 5-10 shows the receive data paths. When an EOP is detected the SxRCNT register is loaded with the number of bits actually received, the EOP bit of the SxINTF register is set, and the data bits are loaded into the SxRBUF register. The RXBF bit in the SxINTE register can be set to enable an interrupt on this event. The data encode block performs 10Base-T Manchester encoding. The encoded TX signal are sent to TX pins in a differential mode. The encode block is bypassed for all other protocols. The SxTXP and SxTXM pins have high current outputs for driving Ethernet magnetics directly without the use of transceivers. The pre-emphasis TX outputs are enabled on SxTXPE and SxTXME outputs, which have a 50ns-delayed and inverted version of the transmit outputs. The resistively combined TX outputs outside the chip are used to drive the magnetics. The output pins of the serializer are driven low when not transmitting. Figure 5-11 shows the transmit data paths. For transmitting, software must specify the number of bits to transmit (specified in the SxTCFG register) and load the data in the SxTBUF register. This data is then transferred to an internal register, from which it is serially shifted out to the transmit logic. The TXBE bit in the SxINTE register can be set to enable an interrupt when the data has been transferred from the SxTBUF register. When there is a transmit buffer underrun event (i.e. all of the data has been shifted out from the internal register, but the SxTBUF register has not been reloaded), an EOP condition is automatically generated on the TX output pins after an internal counter decrements to zero. The TXEOP bit in the SxINTE register can be set to enable an interrupt when an underrun event occurs.
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IP2012 / IP2022 Data Sheet
Software
RXBF EOP Receive Count Register (SxRCNT) Receive Buffer Register (SxRBUF) Receive Interrupt
Receive Data Receive Clock
The SERDES 10Base-T mode is designed to run at a fixed 8x oversampling for line receiver. So a fixed 80MHz master must be configured through SxMODE. The core PLL clock multiplier must be programmed to be an integer multiple of 80MHz for 10Base-T operation. The received data stream is used, together with the clock recovery circuit, to recover the original transmit clock and data. Typical operation with Ubicom's SDK uses a 4.8 MHz crystal with a PLL post-divide by 2 to yield 120 MHz core operation, or a 3.2 MHz crystal with no PLL post-divide to yield 160 MHz operation.
Data Bus
515-004.eps
Software must perform the following functions: * * * * * * Polarity detection and reversal. Carrier sense. Jabber detection. Link integrity test and link pulse generation. Random back off in case of collision. When a collision is detected, sending a 32-bit jam sequence. Collisions can be detected by positive detection of carrier sense during active transmission. Formation of Ethernet packet by putting the preamble, SFD, destination address, source address, length/type, MAC client data into the transmit buffer. Frame check computation can be done in software or through the LFSR units (see Section 5.9). MAC layer functions.
Figure 5-10 Receive Data Paths
TXBE, TXEOP Transmit Configuration Register (SxTCFG) Transmit Buffer Register (SxTBUF) Transmit Interrupt
*
Data Encoder SxTXPE Pre-Emphasis SxTXME
Transmit Clock
*
SxTXP SxTXM
515-018a.eps
Data Bus EOP Generator
Figure 5-11 Transmit Data Paths
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IP2012 / IP2022 Data Sheet
5.6.6
USB
Each SERDES provides support for USB revision 1.1 host and device modes of operation. Hardware To set up a SERDES unit for USB mode, the received data output of the USB transceiver should be connected to SxRXD. The VP and VM pins of the transceiver are connected to the SxRXP and SxRXM pins to allow detection of the EOP condition. Figure 5-12 shows the connections required between an external USB transceiver and the IP2012 / IP2022. Table 5-6 shows the mapping of USB signals to the SERDES pins. If desired, an external clock source can be connected to the SxCLK pin. For additional hardware configuration information, please refer to USB reference design available. Software The SxMODE register must be programmed with values for the desired USB mode, Full Speed or Low Speed. Serdes clock dividers, SxTMRH and SxTMRL, also need to be programmed to generate the appropriate frequency according to the USB submode selection. Table 5-7 shows the PLL clock frequencies required for the low and full speed modes of the USB mode. For example, if the PLL clock is 240 MHz, it can be programmed at 48 MHz for full speed with a divisor of 4 (=5). A divisor of 39 will make it suitable for low-speed operation. If external clock mode is selected, the clock divisor value is ignored and the clock is used directly for USB operation. In USB mode, the SerDes uses two registers, SxRSYNC and SxSMASK, to detect the sync pattern marking the beginning of a USB data stream. This sequence is defined to be "7 zeros and a single 1" by the USB specification, and only the last 3 bits need to be matched to start receiving data, also defined in the specification. In order to achieve this, SxRSYNC needs to be programmed with 0x80 and SxSMASK needs to be programmed with 0xE0. Receive behavior is controlled by the SxRCFG and SxRCNT registers. For USB operation, the higher 3 bits of SxRCFG should be set to zero, and the lower 5 bits should be set to the desired number of bits received, usually 8 or 16. SxRCNT should be cleared to make sure receive is performed LSB first. Once the SerDes matches the USB SYNC pattern, the internal receive count is reset to zero and the SerDes receives bits from the line until either the desired count is received or an EOP is encountered, at which point the received data is transferred to the Serdes Rx Data registers. If more data is coming in, the procedure will be repeated. Software is responsible for reading the data from the data registers before the next write by the hardware. Notice that this will be a short time, if RxCFG is configured with a small receive count, or an EOP is
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received before the desired count is reached. When the EOP is received, the SerDes remains idle until the next match of the SYNC pattern. Transmit behavior is controlled by the SxTCFG register. For proper USB operation, the higher 3 bits should be set to 100, and the lower 5 bits should be set to the desired number of bits transmitted. Transmit can be initiated by writing to the SerDes Tx Data registers. Notice that both registers must be written even if the number of bits to transmit is less than 8. If the transmit count needs to be changed, it must be changed before the Tx Data registers are written. For continued transmission, Tx Data registers have to be written before the Tx bit count is reached. Otherwise, the SerDes automatically inserts the EOP signaling. While receiving data, the clock/data separation circuit performs NRZI decoding, after which bit unstuffing is performed. This means every bit after a series of six consecutive ones is dropped. On transmit, the SerDes performs bit stuffing, and the clock/data separation circuit NRZI encodes the data. Note: While configured for USB mode, the SerDes cannot be configured to interrupt on carrier status (RxCRS, SxRCNT bit 5; see Section 7.1.13). Table 5-5 shows the function of SerDes status flags in USB Mode. See also Section 7.1.10. Table 5-5 Summary of Status Flags in USB Mode Flag USB Mode Function RXERROR This bit indicates the presence of 7 ones in the USB bit stream. RXEOP This bit indicates the presence of EOP signaling, which is 2 bit times of SE0 and 1 bit time of J condition on the bus. SYND This bit indicates that SerDes successfully matched a USB SYNC pattern as configured in the SxSYNC register. TXBE This bit indicates that new data can be written to the Tx Data registers to continue uninterrupted data stream. TXEOP This bit indicates that an EOP condition was generated to signal the end of the USB data stream. Tx Data registers should be written with the sync pattern to start a new stream once this condition occurs.
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IP2012 / IP2022 Data Sheet
Table 5-5 Summary of Status Flags in USB Mode Flag USB Mode Function SXLINK- TxIdle in USB mode. This bit indicates PULSE whether the SerDes is actively transmitting data. RXBF This bit indicates that Rx data registers are written with new data and should be read before the next desired amount of bits are received. RXXCRS This bit is a live status indicator in USB mode. If set, the SerDes is receiving data into the shift register, but there might not be any data in the data registers yet.
*
*
*
Detecting the suspend state, which is indicated by more than 3 milliseconds of idle. Software muse make sure that the suspend current of 500 uA will be drawn after 10 milliseconds of bus inactivity. Formation of the USB packet by putting the sync, pid, and data into the transmit data registers and setting the proper count. Endpoint and device management and other higher level protocol tasks.
Timing Considerations USB relies on certain timing limitations for error detection and recovery. Response time requirements are specifically harder to meet. ISR for USB needs to be carefully structured to satisfy these requirements, and this is possible because of IP2012 / IP2022's deterministic ISR execution times. The time from the SE0 on bus to the RXEOP indication is about 208 ns. The time from writing to TX data registers and the data put on the bus is about 125 ns. Software tasks like address, error, CRC checking, and determining the endpoint response have to be carefully timed and cycle counted to assure the required timing limitations are satisfied.
Software must perform the following functions to implement the USB protocol for a device: * * CRC generation and checking (can be done using the LFSR, Section 5.9). Detecting reset of the device function, which is indicated by 10 milliseconds of a single-ended zero (SE0) condition on the bus.
PDIUSBP11A SxRXP VP
SxRXM IP2022 or IP2012
VM
SxRXD
RCV
+ D+ USB Bus D-
SxTXP SxTXM SxTXPE
VPO VMO OE
515-034c.eps
Figure 5-12 USB Interface Example Table 5-6 USB Interface Signal Usage USB Signal Name VP VM VPO VMO SERDES Signal Name SxRXP SxRXM SxTXP SxTXM SERDES1 Pin Name RE1 RE2 RE5 RE6 SERDES2 Pin Name (IP2022 only) RF5 RF6 RF1 RF2 Direction Input Input Output Output Description Plus-side differential input Minus-side differential input Plus-side differential output Minus-side differential output
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IP2012 / IP2022 Data Sheet
Table 5-6 USB Interface Signal Usage (continued) USB Signal Name OE RCV Clock SERDES Signal Name SxTXPE SxRXD SxCLK SERDES1 Pin Name RE4 RE3 RE0 SERDES2 Pin Name (IP2022 only) RF0 RF7 RF4 Direction Output Input Input Description Output enable Receive data External clock input (optional)
Table 5-7 Required Clock Frequencies from SerDes Clock in USB Mode Protocol USB 1.1 Full Speed USB 1.1 Low Speed Receive 48 MHz 6 MHz
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IP2012 / IP2022 Data Sheet
5.6.7
UART
For UART operation, two internal divide-by-16 circuits are used. Based on the clock source (either internal or external), the receive section and the transmit section use two divided-by-16 clocks that potentially can be out of phase. This is due to the nature of the UART bus transfers. The receive logic, based on the 16x bit clock (the clock source chosen by user), will sample the incoming data for an falling edge. Once the edge is detected, the receive logic counts 8 clock cycles and samples the number of bits specified in the SxRCNT register using the bit clock (which is obtained by dividing the clock source by 16). Hardware Figure 5-13 shows an example circuit to connect the SERDES in UART mode. Table 5-8 shows the UART signal to port pin usage. Software To set up a SERDES unit for UART mode, select UART mode in the PRS3:0 bits of the SxMODE register. This causes the data to be clocked in after a valid start bit is
detected. Make sure that the polarity selected by the RPOREV bit in the SxRCFG register and the TPOREV bit in the SxTCFG register match the polarity provided by the RS-232 transceiver. (Most of them are inverted.) Make sure the bit order is compatible with the data format (RS232 uses LSB-first bit order). The receiver uses 16X oversampling, so select a SERDES clock divisor (see Section 7.1.17 for information on the SxTMRH/L registers) that is 16 times the desired baud rate. To operate in UART mode, depending on the application, either transmit or receive can be performed first. In both cases, the configuration register needs to be programmed with a bit count that is appropriate for the format. The bit count depends on the number of data bits, stop bits, and parity bits. The start bit is included in the bit count. The receiver does not check for the presence of stop bits. To detect framing errors caused by missing stop bits, increase the receiver's bit count (i.e. the RXSCNT field in the SxRCFG register) and test the trailing bit(s) in software.
RS-232 Transceiver IP2022 or IP2012
SxRXD
RxOUT
RxIN RS-232
SxTXP
TxIN
TxOUT
515-094a.eps
Figure 5-13 UART Interface Example Table 5-8 UART Interface Signal Usage UART Signal Name RXD TXD SERDES Signal Name SxRXD SxTXP SERDES1 Pin Name RE3 RE5 SERDES2 Pin Name (IP2022 only) RF7 RF1 Direction Input Output Description Receive data Transmit data
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IP2012 / IP2022 Data Sheet
5.6.8
SPI
sampled by this device (the slave) on the second edge (transition). Note: The use of the term "edge" in the above paragraphs implies any transition, not a specific type (i.e. rising or falling) of transition. Therefore, "first edge" implies a rising edge when CPOL=0, and implies a falling edge when CPOL=1. In the SPI scheme implemented by Motorola, which the IP2012 / IP2022 follows, data being output on SDO and data being sampled on SDI always occur on opposing edges of the clock, on either master or slave. Transmitting and sampling on the same-edge of the clock is not supported by the SERDES. CPOL, in conjunction with CPHA, determines which clock edges the SERDES will be using to output and sample data on, as given by Table 5-9. Table 5-9 SERDES Output and Sample Configuration CPOL 0 0 1 1 CPHA 0 1 0 1 output on falling, sample on rising output on rising, sample on falling output on rising, sample on falling output on falling, sample on rising
Hardware Figure 5-14 shows example circuits to connect the SERDES in SPI mode. Table 5-10 and Table 5-11 show the SPI signal to port pin usage. Configuration The SERDES can be configured for either master or slave mode: SxRCFG[7] = 0: slave SxRCFG[7] = 1: master The SERDES SCK idle-level (i.e. when SS is de-asserted) can be configured: SxMode[4] (CPOL) = 0: idle is low SxMode[4] (CPOL) = 1: idle is high Finally, the SERDES can be configured for the phase relationship of the SDO/SDI pins with respect to the SCK edge: SxMode[3] (CPHA) = 0: SDO is set up by the other device a half clock period before the first edge following the assertion of SS*. Therefore SDI will be sampled by this device (the slave) on the first edge (transition). SxMode[3] (CPHA) = 1: SDO is set up by the other device on the first edge following the assertion of SS*. Therefore SDI will be
When the SERDES is configured as a slave, the state of the SDO line when SS* is de-asserted will be determined by the value in the RxOUT GPIO register for that pin, which the user can configure.
IP2022 or IP2012 (SPI Master) GPIO SxCLK SxRXD(DI) SxTXP(DO) SS SCLK DI DO SS SCLK DO DI
SPI Slave
OR IP2022 or IP2012 (SPI Slave) SxRXP SxCLK SxRXD(DI) SxTXP(DO) SS SCLK DI DO SS SCLK DO DI
515-095b.eps
SPI Master
Figure 5-14 SPI Interface Examples
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IP2012 / IP2022 Data Sheet
Table 5-10 SPI Master Interface Signal Usage SPI Device Signal Name SCLK IP2012 / IP2022 SPI Signal Name SCLK SERDES SERDES1 SERDES2 Pin Name Signal Name Pin Name (IP2022 only) Direction SxCLK RE0 RF4 Output Description Serial clock output in master mode, input in slave mode Receive data Transmit data Slave select pin used in slave mode only (Master select handled by software)
DO DI SS
DI DO SS
SxRXD SxTXP GPIO
RE3 RE5 RE1
RF7 RF1 RF5
Input Output Output
Table 5-11 SPI Slave Signal Usage SPI Device Signal Name SCLK IP2012 / IP2022 SPI SIgnal Name SCLK SERDES2 SERDES SERDES1 Pin Name Signal Name Pin Name (IP2022 only) Direction SxCLK RE0 RF4 Input Description Serial clock output in master mode, input in slave mode Receive data Transmit data Slave select pin used in slave mode only (Master select handled by software)
DO DI SS
DI DO SS
SxRXD SxTXP SxRXP
RE3 RE5 RE1
RF7 RF1 RF5
Input Output Input
SCK CYCLE #
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT (CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT (CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE) 515-098.eps
Figure 5-15 SPI Signal Timing
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IP2012 / IP2022 Data Sheet
5.6.9
GPSI
Hardware Figure 5-16 shows example circuits to connect the SERDES in GPSI (General Purpose Serial Interface) mode. Table 5-12 shows the GPSI signal to port pin mapping in Master mode, and Table 5-13 shows the GPSI signal to port pin mapping in Slave mode. Software GPSI is a general-purpose, point-to-point, full-duplex serial bus protocol. Only two devices are allowed to exist on a bus. The GPSI PHY device is responsible for maintaining bus timing by driving two continuously running clocks, TxClk and RxClk. The device that does not drive the clocks is the MAC device. The TxEn and TxD signals are synchronized to the TxClk clock. The RxD and RxEn signals are synchronized to the RxClk clock.
The COLLISION and TxBUSY signals do not participate in actual data transfer on the GPSI bus. COLLISION and TxBUSY provide additional flow control capabilities for the software device driver. The COLLISION signal is used to indicate that a PHY device has detected a collision condition. This signal is only useful when the SERDES is connected to a PHY device or acting as a PHY device. The TxBUSY signal is used by a GPSI device to indicate that the device is currently busy, and that another device should not attempt to start a data transfer. Refer to SxRCNT register bit 5. Refer to Section 7.1.10 through Section 7.1.17 for detailed configurations. Example: To get the PLL clock divided by 2 out on RE6: S1MODE=63 S1RCFG=80 S1TCFG=80
RxCLK SxTXPE SxTXP IP2022 SxRXP or IP2012 SxRXD (GPSI Master) SxTXM GPIO GPIO TxEN TxD RxEN RxD TxCLK/RxCLK TxBUSY COL OR SxCLK SxRXP SxRXD IP2022 SxTXPE or IP2012 SxTXP (GPSI Slave) SxTXM SxTXME GPIO RxCLK RxEN RxD TxEN TxD TxCLK TxBUSY COL
RxCLK RxEN RxD TxEN TxD TxCLK TxBUSY COL GPSI Slave
TxCLK TxEN TxD RxEN RxD RxCLK TxBUSY COL
515-096c.eps
GPSI Master
Figure 5-16 GPSI Interface Examples
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IP2012 / IP2022 Data Sheet
Table 5-12 IP2012 / IP2022 GPSI Master Interface Signal Usage GPSI Slave Signal Name TxCLK and RxCLK TxD TxEN RxD RxEN TxBUSY IP2012 / IP2022 GPSI Signal Name TxCLK and RxCLK RxD RxEN TxD TxEN TxBUSY SERDES2 SERDES SERDES1 Pin Name Signal Name Pin Name (IP2022 only) SxTXM SxRXD SxRXP SxTXP SxTXPE GPIO RE6 RE3 RE1 RE5 RE4 RF2 RF7 RF5 RF1 RF0 IP2012 / IP2022's Direction Output Input Input Output Output Output Description Transmit and Receive clock Transmit data Transmit data valid Receive data Receive data valid Indicates a data transfer in progress (handled by software) Indicates a collision at PHY layer (handled by software)
COLLISION
COLLISION
GPIO
-
-
Output
Table 5-13 IP2012 / IP2022 GPSI Slave Interface Signal Usage GPSI Master Signal Name TxCLK RxD RxEN TxCLK TxD TxEN TxBUSY IP2012 / IP2022 GPSI Signal Name RxCLK TxD TxEN RxCLK RxD RxEN TxBUSY SERDES2 SERDES SERDES1 Pin Name Signal Name Pin Name (IP2022 only) SxTXM SxTXP SxTXPE SxCLK SxRXD SxRXP SxTXME RE6 RE5 RE4 RE0 RE3 RE1 RE7 RF2 RF1 RF0 RF4 RF7 RF5 RF3 IP2012 / IP2022's Direction Input Output Output Input Input Input Input Description Transmit clock Transmit data Transmit data valid Receive clock Receive data Receive data valid Indicates a data transfer in progress (handled by software) Indicates a collision at PHY layer (handled by software)
COLLISION
COLLISION
GPIO
-
-
Input
Note: In GPSI master mode, the SxTXM SERDES pin should be used by the GPSI slave for both TxCLK and RxCLK inputs
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IP2012 / IP2022 Data Sheet
5.7
* * * * * * *
Analog to Digital Converter (ADC)
10-bit ADC (when Vref > 2.3V) 8 input channels 48 kHz maximum sampling rate One-shot conversion. Optional external reference voltage Vmax = AVdd (max 2.7V) Result returned in the ADCH and ADCL registers
5.7.1
ADC Reference Voltage
The on-chip A/D converter has the following features:
The reference voltage (Vref) can come from either the RG3 port pin or from the AVdd supply voltage. If AVdd is used, the RG3 port pin may be used as a channel of analog input or as a general-purpose port pin. Vref defines a voltage level which reads as one increment of resolution below the full-scale voltage. The full-scale voltage reads as 0x3FF, so the Vref voltage reads as 0x3FE and the A/D converter resolution is 10 bits. Table 5-14 shows the values reported at the upper and lower limits of the ADC input voltage range.
Figure 5-17 shows the A/D converter circuitry. The ADC input pins use alternate functions of the Port G pins. The result of an ADC sample is the analog value measured on the selected pin. To correctly read an external voltage, the pin being sampled must be configured as an input in the port direction register (i.e. the RGDIR register). If the pin is configured as an output, then the result will indicate the voltage level being driven by the output buffer. The RG1 and RG2 port pins are also used as the analog comparator input pins. The result of sampling the RG1 or RG2 pins will be correct whether or not the comparator is operating. The RG0 pin is also used as the comparator output pin. If the comparator is enabled, then sampling the RG0 pin will indicate the voltage level being driven by the comparator. The RG3 pin is multiplexed with the external reference voltage.
ADCREF AVdd RG3 ADCS2:0 ADCGO RG7:0 A/D 10 7 ADCH 8 07 ADCL 8 0 Vref Reference Voltage
5.7.2
A/D Converter Registers
ADCTMR Register The ADCTMR register (see Section 7.1.2) is used to specify the number of system clock cycles required for a delay of 1736 ns, which is used to provide the 1.152MHz (48 kHz 24) clock period reference clock for the A/D converter. For example, at a system clock frequency of 120 MHz, the timer register should be set to 53 ((120 MHz/1.152 MHz)/2). The minimum value that may be loaded into the ADCTMR register is 2, so the system clock must be at least 24 times the ADC sampling frequency for the ADC to function. ADCCFG Register The A/D converter configuration register (ADCCFG) provides the control and status bits for the A/D converter, as shown in Section 7.1.1. Table 5-14 ADC Values Vin Voltage 0V Vref/0x3FE Vref Vref + (Vref/0x3FE) ADC Value 0x000 0x001 0x3FE 0x3FF
Data Bus System Clock ADC Timer
Data Bus
515-016.eps
Figure 5-17 A/D Converter Block Diagram
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IP2012 / IP2022 Data Sheet
5.7.3
Using the A/D Converter
5.7.4
ADC Result Justification
The following sequence is recommended: 1. Set the ADCTMR register to the correct value for the system clock speed. 2. Load the ADCCFG register to specify the channel and set the ADCGO bit. Setting the ADCGO bit enables and resets the ADC timer. 3. After a period of time (24 timer overflows = 20.8 s) the conversion will complete, the ADCGO bit will be cleared, and the ADC timer will be disabled. 4. A timer-based interrupt service routine can detect or assume the ADCGO bit has been cleared and read the ADC value. 5. Another load to the ADCCFG register can then be used to start another conversion.
The 10 bits of the ADC value can be mapped to the 16 bits of the ADCH/ADCL register pair in three different ways, as shown in Table 5-15. In this table, the numbers in the cells represent bit positions in the 10-bit ADC value, Z represents zero (as opposed to bit position 0), and -9 represents the inversion of bit position 9.
Table 5-15 Justification of the ADC Value Mode Left Justified Right Justified Signed ADCH Register Bits 7 9 Z -9 6 8 Z -9 5 7 Z -9 4 6 Z -9 3 5 Z -9 2 4 Z -9 1 3 9 -9 0 2 8 8 7 1 7 7 6 0 6 6 ADCL Register Bits 5 Z 5 5 4 Z 4 4 3 Z 3 3 2 Z 2 2 1 Z 1 1 0 Z 0 0
5.8
Comparator
hysteresis is applied between the inputs, when the CMPHYS bit is set in the CMPCFG register.
The IP2012 / IP2022 has an on-chip analog comparator which uses alternate functions of the RG0, RG1, and RG2 port pins. The RG1 and RG2 pins are the comparator negative and positive inputs, respectively, while the RG0 pin is the comparator output pin. To use the comparator, software must program the port direction register (RGDIR) so that RG1 and RG2 are inputs. RG0 may be set up as a comparator output pin.
CMPEN, CMPHYS CMPRES RG0 RG2 RG1 + 515-017.eps
5.8.1
CMPCFG Register
The CMPCFG register is used to enable the comparator, to read the output of the comparator internally, to enable the output of the comparator to the comparator output pin, and to enable the hysteresis. Section 7.1.3 shows the bits in this register.
CMPOE
Figure 5-18 Analog Comparator The comparator enable bits are cleared on reset, which disables the comparator. To avoid drawing additional current during power-down mode, the comparator should be disabled before entering power-down mode. A 50 mV
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IP2012 / IP2022 Data Sheet
5.9
Linear Feedback Shift Register (LFSR)
DATAIN Register DIN 1 Polynomial Register (POLYx) 0 1..39 D0 Source Gating POLY Source Gating 0..38 D0 39 POLY_XOR_EN 39
1
0 39
0 1..39 Residue Register (RESx) 0..39 40
FB1 40:1
0..39 FB2 1 40:1
0..39 FB3 1 40:1
0..39 FB4 1 40:1
0..39 DOUT 40:1 1
0..39 1
DOUT DOUT Source 1 Gating
16-bit DATAOUT Register
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Figure 5-19 LFSR Block Diagram Four linear feedback shift register (LFSR) units provide hardware support for the computation-intensive inner loops of algorithms commonly used in data communications, such as: * * * * * Cyclic Redundancy Check (CRC) Data Scrambling Data Whitening Encryption/Decryption Hashing output (DOUT) bit streams. A fifth multiplexer is only used for generating the output bit stream. The polynomial and residue registers are mapped as five 8-bit registers. The mapping of the residue register is controlled by the ML_OUT bit of the LFSRCFG3 register, as shown in Figure 5-20.
7 39 0 07 07 07 07 0 0 39
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RES0
RES1
RES2
RES3
RES4
The LFSR units implement a programmable architecture, which can be adapted for algorithms used by the Bluetooth, Ethernet, Homeplug, HomePNA, HomeRF, IEEE 802.11, and USB communication protocols. Figure 5-19 is a block diagram of the LFSR architecture. The 40-bit residue register and its surrounding circuits are the computational core of an LFSR unit. On every clock cycle, 39 output bits from the register are available at the input for performing a shift operation or a polynomial add/subtract-and-shift operation. Four 40-bit multiplexers at the output of the residue register allow selecting up to four terms of the register for feedback into the input (D0), polynomial operation control (POLY_XOR_EN), and
Residue Register (ML_OUT = 0) Residue Register (ML_OUT = 1)
Figure 5-20 Mapping of the Residue Register Input data is shifted serially out of the 16-bit DATAIN register, which can be programmed to provide the data LSB-first or MSB-first. Output data is shifted serially LSBfirst into the 16-bit DATAOUT register.
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IP2012 / IP2022 Data Sheet
A 32-bit RESCMP register (not shown) can be used to compare the result in the residue register against an expected value. When ML_OUT is set, residue register bits 0:31 are compared against RESCMP bits 0:31. When ML_OUT is clear, residue register bits 39:8 are compared to RESCMP bits 0:31, respectively. If there are bits in the residue register which do not participate in the programmed LFSR operation, be sure that the corresponding bits in the RESCMP register are initialized to the same values as these non-participating bits. Each LFSR unit has three configuration registers (LFSRCFG1, LFSRCFG2, and LFSRCFG3) for various control and status bits. The HL_TRIGGER bit in the LFSRCFG3 register controls whether operation of the LFSR unit is triggered by a write to the high byte or the low byte of the DATAIN register (i.e. DATAINH or DATAINL). The operation then proceeds for some number of cycles programmed in the SHIFT_COUNT3:0 field of the LFSRCFG1 register. Completion of the operation is indicated when the DONE bit in the LFSRCFG1 register is set. (Alternatively, software can wait 1 cycle/bit of DATAIN before reading the result.) An autoloading option is available for each LFSR unit to load the DATAIN register automatically from the SERDES RX buffers (SxRBUF register of the corresponding SERDES unit). LFSR0 and LFSR2 are paired with SERDES1, and LFSR1 and LFSR3 are paired with SERDES2. Three registers in data memory are used to access the LFSR register banks, as shown in Table 5-16. Table 5-16 LFSR Registers in Data Memory Address 0x23 0x27 0x2B Name LFSRH LFSRL LFSRA Description High data byte Low data byte Address register * * * *
Table 5-17 LFSRA Register INDEX Encoding INDEX3:0 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC High Byte (LFSRH) Low Byte (LFSRL) DATAINH DATAOUTH FB2 LFSRCFG2 RES3 RES1 FB4 LFSRCFG3 LFSRCFG1 POLY3 POLY1 RESCMP3 RESCMP1 DATAINL DATAOUTL FB1 RES4 RES2 RES0 FB3 DOUT POLY4 POLY2 POLY0 RESCMP2 RESCMP0
All registers initialized to 0x00 upon reset, except RESx = 0xFF, RESCMPx = 0xFF, and LFSRCFG1 = 0x10).
The LFSR registers do not support consecutive readmodify-write operations. For example, the following instruction sequence loads unpredictable values:
clrb lfsrh,7 clrb lfsrh,4
5.9.1
7
LFSRCFG1 Register
6 5 4 3 0
Rsvd SET_RES DONE CMP_RES SHIFT_COUNT3:0 Figure 5-22 LFSRCFG1 Register SET_RES--set to initialize the residue register to all ones (write-only, reads as zero). DONE--clear while the LFSR is busy, set when the operation is completed (read only). CMP_RES--set if last LFSR operation result matched contents of RESCMP register (read only). SHIFT_COUNT3:0--specifies number of bits to shift, load with N for an operation of N+1 shifts.
The LFSRA register is loaded to point to a specific LFSR unit and a register pair within the unit. The LFSRA register has the format shown in Figure 5-21 7 UNIT3:0 4 3 INDEX3:0 0
Figure 5-21 LFSRA Register Only 0, 1, 2, and 3 are valid as the UNIT, LFSRA bits 7 and 6 = don't care. The valid encodings for the index are shown in Table 5-17.
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IP2012 / IP2022 Data Sheet
5.9.2
7 DOUT_DOUT_EN
LFSRCFG2 Register
6 5 4 3 2 1 0 DATA_IN_POLYXOR_EN
* * *
HL_TRIGGER--set to trigger operation start on loading DATAINH register, clear to trigger on DATAINL. FB3_D0_EN--set to enable FB3 signal in source gating for D0 node. FB4_D0_EN--set to enable FB4 signal in source gating for D0 node.
FB1_DOUT_EN
FB2_DOUT_EN
DIN_DOUT_EN
FB1_D0_EN
FB2_D0_EN
DIN_D0_EN
5.9.4
DATAIN Register
Figure 5-23 LFSRCFG2 Register * * * * * * * * DOUT_DOUT_EN--set to enable DOUT multiplexer output in source gating for DOUT node. DIN_DOUT_EN--set to enable DIN signal in source gating for DOUT node. FB1_DOUT_EN--set to enable FB1 signal in source gating for DOUT node. FB2_DOUT_EN--set to enable FB2 signal in source gating for DOUT node. DIN_D0_EN--set to enable DIN signal in source gating for D0 node. FB1_D0_EN--set to enable FB1 signal in source gating for D0 node. FB2_D0_EN--set to enable FB2 signal in source gating for D0 node. DATA_IN_POLYXOR_EN--set to enable DIN signal in source gating for POLY_XOR_EN node.
The 8-bit DATAINH and DATAINL registers together comprise the 16-bit DATAIN register. For LFSR0 and LFSR2, the AUTOLOAD_EN bit in the LFSRCFG3 register can be used to enable automatic loading from SERDES1. For LFSR1 and LFSR3, the AUTOLOAD_EN bit in the LFSRCFG3 register can be used to enable automatic loading from SERDES2. The HL_TRIGGER bit in the LFSRCFG3 register controls whether loading the DATAINH or DATAINL register triggers the start of the LFSR operation. The ML_IN bit in the LFSRCFG3 register controls whether data is shifted MSB-first or LSB-first from the DATAIN register to the DIN node.
5.9.5
DATAOUT Register
The 8-bit DATAOUTH and DATAOUTL registers together comprise the 16-bit DATAOUT register. Data shifted out of the residue register is shifted LSB-first into the DATAOUT register.
5.9.6
DOUT Register
5.9.3
7
LFSRCFG3 Register
6 5 AUTOLOAD_EN 4 ML_OUT 3 2 HL_TRIGGER 1 FB3_D0_EN 0 FB4_D0_EN
The DOUT register controls a 40:1 multiplexer on the residue register outputs. It selects a term which can be used in the source gating for the DOUT bit stream.
5.9.7
FBx Registers
Reserved
The four FBx registers control four 40:1 multiplexers on the residue register outputs. They select feedback terms which can be used in the source gating for the D0, POLY_XOR_EN, and DOUT bit streams.
ML_IN
Figure 5-24 LFSRCFG3 Register * AUTOLOAD_EN--set to enable autoloading DATAIN register when SxRBUF register of corresponding SERDES unit is loaded. ML_OUT--set to shift data out of residue register LSB, and into MSB, clear to shift data out of residue register MSB, and into LSB. See Figure 5-20 for effect on RESx mapping. ML_IN--set to shift data from DATAIN register MSBfirst to DIN node, clear to shift data LSB-first.
5.9.8
POLYx Registers
The five POLYx registers hold the 40-bit polynomial used in the LFSR operation.
*
5.9.9
RESx Registers
*
The five RESx registers hold the 40-bit residue used in the LFSR operation. The ML_OUT bit controls the mapping of the residue register to the RESx registers, as shown in
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IP2012 / IP2022 Data Sheet
Figure 5-20. The residue register can be initialized to all ones by setting the SET_RES bit in the LFSRCFG1 register.
5.9.10 RESCMPx Registers
The four RESCMPx registers hold a 32-bit value for comparison with the contents of the residue register. After an LFSR operation is completed, the CMP_RES bit in the LFSRCFG1 register indicates whether the result of the operation matched the 32-bit value. When the ML_OUT bit in the LFSRCFG3 register is clear, bits 39:8 of the residue register are compared against bits 0:31 of the RESCMP register. When ML_OUT is set, bits 0:31 of the residue register are compared against bits 0:31 of RESCMP.
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IP2012 / IP2022 Data Sheet
5.9.11 LFSR Configuration
The LFSR units were designed with the following communication protocols in mind: Bluetooth, Ethernet, Homeplug, HomePNA, HomeRF, IEEE 802.11, and USB. Table 5-18 shows the LFSR configurations used to support these protocols.
Table 5-18 LFSR Configurations for Various Protocols Protocol USB Ethernet Subfunction CRC16 CRC5 CRC32 Scrambler Descrambler HomePlug CRC8 CRC16 Scrambler HomePNA CRC8 CRC16 Scrambler 802.11 CRC32 (FCS) CRC16 (HEC) Data Whitening CRC16 (CRC) Scrambler Descrambler Home-RF CRC Scrambler Descrambler Bluetooth FEC HEC CRC16 Data Whitening Encryption Din^D15 Din^D4 Din^D31 Din^D17^D22 Din Din^D7 Din^D15 D6^D3 Din^D7 Din^D15 D17^D22 Din^D31 Din^D15 D3^D6 Din^D15 Din^D3^D6 Din Din^D31 Din Din Din^D4 Din^D7 Din^D15 D6 Din^D8^D12^D20^D25 Din^D12^D16^D24^D31 Din^D4^D24^D28^D33 Din^D4^D28^D36^D39 Din^D4 Din^D7 Din^D15 D6 Din^D6 D24 D24 D32 D32 Din^D31 Din^D3^D8 Din^D3^D8 Din^D15 Din^D3^D6 Din^D3^D6 Din^D31 Din^D15 Din^D3^D6 Din^D7 Din^D15 Din^D17^D22 Din^D7 Din^D15 Din^D6^D3 D0 In Feedback Din^D15 Din^D4 Din^D31 Din^D17^D22 Din^D17^D22 D Out
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IP2012 / IP2022 Data Sheet
5.10
Parallel Slave Peripheral (PSP)
The Parallel Slave Peripheral allows the IP2012 / IP2022 to operate as an 8- or 16-bit slave to an external device, much like a memory chip. The IP2022 supports either 8bit or 16-bit wide bus operation, while the IP2012 is 8-bit wide bus only. Alternate functions of Port C and Port D are used for transferring data, and alternate functions of Port B are used for control signals. Figure 5-25 shows the connections between an external master and the Parallel Slave Peripheral interface.
R1 CS R/W HOLD External Master Data Data R1 CS R/W HOLD External Master Data RB7 RB6 RB5 IP2012 Slave RC7:0 RB7 RB6 RB5 IP2022 Slave RC7:0 RD7:0
HOLD signal is in high-impedance mode. The HOLD signal should have an external pullup resistor (R1 = 10K is recommended). The CS signal must not be allowed to float. When CS is asserted, an interrupt is generated and HOLD (if enabled) is automatically asserted. If the data transfer is a write from the external master, software reads the Port C, Port D, or both. If the data transfer is a read, software writes the data to the port or ports. Finally, if HOLD is asserted, software releases assertion of HOLD by writing to the PSPRDY bit in the PSPCFG register. The Parallel Slave Peripheral does not generate interrupts by itself. Software is required to enable port pin RB7 (the CS input) as a falling-edge interrupt input for the Parallel Slave Peripheral to function. The CS signal must go high, then back low, for each data transfer. RB6 (the R/W input) must also be configured as an input. The setting in the RBDIR register for RB5 (the HOLD output) is overridden by the programming of the Parallel Slave Peripheral.
IOVDD
5.10.1 PSPCFG Register
The PSPCFG register is used to enable the Parallel Slave Peripheral, select which ports are used for data transfer, enable the HOLD output, and release the HOLD output when the data transfer is ready to complete. 7 6 5 4 32 1 0 PSPEN2 PSPEN1 PSPHEN PSPRDY Res WD BO Table 5-19 PSPCFG Register * PSPEN2--set to enable Port D for data transfer, clear to disable. (If this bit is set, the Parallel Slave Peripheral overrides the RDDIR register.) PSPEN1--set to enable Port C for data transfer, clear to disable. (If this bit is set, the Parallel Slave Peripheral will immediately override the RCDIR register.) PSPHEN--set to enable HOLD output, clear to disable. (If this bit is set, the Parallel Slave Peripheral will immediately override bit 5 of the RBDIR register.) PSPRDY--set to release HOLD. This bit always reads as 0. WD--Watchdog time-out bit. Set at reset, if reset was triggered by Watchdog Timer overflow, otherwise cleared. BO--Brown-out reset bit. Set at reset, if reset was triggered by brown-out voltage level detection, otherwise cleared.
IOVDD
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Figure 5-25 Parallel Slave Peripheral To read or write through the Parallel Slave Peripheral interface, the external master asserts the chip select (CS) signal low. This signal is an alternate function of port pin RB7. The direction of transfer is indicated by the R/W signal, which is an alternate function of port pin RB6. When the R/W signal is high, the master is reading from the slave. When the R/W signal is low, the master is writing to the slave. Optionally, a HOLD signal may be enabled as an alternate function of port pin RB5. Assertion of HOLD indicates to the external master that the Parallel Slave Peripheral interface is not ready to allow the data transfer to complete. The HOLD signal is driven like an opencollector signal, i.e. low when asserted and highimpedance when not asserted. When the CS signal is not asserted (i.e. the IP2012 / IP2022 is not selected), the
*
*
* *
*
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IP2012 / IP2022 Data Sheet
5.11
External Memory Interface (IP2022 only)
Note: Wait one cycle after changing ADDRX bit 7, EMCFG bit 7, or ADDRSEL before executing an fread, fwrite, or ferase, or an iread or ireadi.
Byte Address 0x000000 0x003FFE 0x004000 0x00FFFE 0x010000 Flash Program Memory 0x01FFFE 0x020000
Port C and Port D can also be used for a parallel interface for up to 128K bytes of linear-addressed external memory, (not program memory) as shown in Figure 5-26. With additional software-based addressing on I/O, up to 2M bytes is possible. Port C implements the high address bits, and Port D is multiplexed between data and the low address bits. A level-triggered 8-bit latch (TI part number SN74AC573 or equivalent) is required for demultiplexing. This latch passes the RD7:0 data when LE is high, and holds the data when LE is low.
7 Program RAM Reserved
0
RC7:0
Address LE
A16:9
RB6
External Memory Latch
Reserved
IP2022
Addr
A8:1
0x7FFFFE 0x800000 External Memory 0x81FFFE
RD7:0
Data
D7:0
RB7 RB5 RB4
A0 RD WR
A0 RD WR
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Figure 5-27 External Memory Map Software is responsible for inserting a one-instruction delay between changing the address (i.e. the contents of the ADDRSEL, ADDRX, ADDRH, or ADDRL registers) and executing the iread or iwrite instruction, if required by the timing of the external latch. A read cycle to external memory has the timing shown in Figure 5-28. Write cycle timing is shown in Figure 5-29. The timings shown are recommended for 10ns and 12ns SRAMs. All external memory cycles are 16-bit transfers, with the low byte (A0 = 0) followed by the high byte (A0 = 1). The number of system clocks required for one read or write access cycle is programmable to meet the SRAM timing. Figure 5-28 shows a typical SRAM read access cycle, with EMCFG register set to C9h, that is used to access 10ns SRAM with a 120 MHz system clock. SRAM grade reflects SRAM access time (Taa) in nanoseconds and typically is a last digit of an SRAM part number. SRAM has several important parameters which should be taken into account when calculating EMCFG register settings (refer to Table 5-21). Table 5-20 shows maximum capacitance allowed on any SRAM controller signal line vs. a given SRAM grade and EMCFG setting that provides reliable access.
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Figure 5-26 External Memory Interface External memory is accessed as 16-bit words at wordaligned byte addresses 0x800000 to 0x81FFFE, as shown in Figure 5-27. External 8-bit memory can only be accessed through the current ADDRX/ADDRH/ADDRL pointer using the iread and iwrite instructions. Programs cannot execute directly out of external memory, and commands on the ISD/ISP interface cannot directly access external memory. Note: In order to use the external memory interface correctly, RB[4:7], RC[0:7] and RD[0:7] must ALL be configured as outputs through their respective portdirection configuration registers.
5.11.1 EMCFG Register (IP2022 only)
Refer to Section 7.1.4 for field definitions and other information about the EMCFG register. Note: When external memory is enabled (EMEN = 1), the RDDIR register value is overridden. PSP function will need to be disabled. Port B bits 4-7 interrupts need to be disabled.
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IP2012 / IP2022 Data Sheet
Table 5-20 EMCFG Settings IP2022 System CLK 120 120 120 160 160 Max Load Capacitance on LE, RD, WR, A0, and RD7:0(pF) 10 30 50 10 30 EMCFG Register Setting C9h C9h C9h D2h D2h
Software is responsible for allowing a memory cycle to complete before reading DATAH/DATAL registers by inserting instructions as follows: * * * Instructions between IREAD and read of DATAH = EMRDT + 1 Instructions between IREAD and read of DATAL = 2 * (EMRDT + 1) Instructions between consecutive IREADs (not including IREAD access cycles) =2 * ( EMRDT + 1)
Tipd (ns)
Taa (ns)
8 9 10 8 9
12 12 10 10 12
Note: The formulas and tables above assume that the address latch chip propagation delay is < Tsys_clk.
1st IREAD 0 System Clock* RC7:0 RD7:0 ADDR8:1 toe LE (RB6) ADDR16:9 th DATAH taa th DATAL ** tohz
ADDR8:1
2nd IREAD 6 7 8 0 1
1
2
3
4
5
ADDR16:9
RD (RB5) A0 (RB7)
IREAD ADDR Stable
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* System Clock is the IP2022's internal clock, and is shown for reference only. ** Setting EMBRT adds one extra Z state cycle on the RD7:0 bus between cycle 7 and cycle 0, and increases the IREAD cycle time from 8 to 9 cycles. Figure 5-28 SRAM Read Cycle (EMBRT=1; EMRDT=2 cycles)
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IP2012 / IP2022 Data Sheet
Table 5-21 Timing Requirements for SRAM IP2022's Timing Requirements Data Hold Time Signal Name th 0 Units ns Note
Set EMRDT and EMBRT in the EMCFG Register such that: SRAM Signal Description Output Enable to Output Data Address to Output Data Output Disable to Output in Hi-Z Signal Name toe (EMRDT+1)*Tsys_clk - tipd taa (EMRDT+1.5)*Tsys_clk - tipd tohz (EMBRT+1)*Tsys_clk - 6ns Units ns ns ns Note 1,2 1,2 1,2,3
Add instruction(s) after any ADDR change and before the IREAD or IWRITE in software, such that: Latch Signal Description Setup Time of Address Before LE Signal Name tsu (# of instructions added + 1) * Tsys_clk - 3ns
Notes: 1. IP2022's RD is connected to the external SRAM's OE pin. 2. Tsys_clk is the period of the IP2022 system clock, and tipd is the propagation delay internally in the IP2022, of the SRAM control signals (see Table 5-20). 3. The IP2022 should not output on RD7:0 before the SRAM tri-states this bus (set EMBRT = 1 if bus contention can exist with EMBRT = 0).
0 System Clock* RC7:0 RD7:0 LE (RB6)
1
2
3
4
5
6
7
0
1
ADDR16:9 ADDR8:1 DATAH DATAL
ADDR16:9 ADDR8:1 DATAH
WR (RB4) A0 (RB7)
IWRITE ADDR Stable
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* System Clock is the IP2022's internal clock, and is shown for reference only. Figure 5-29 SRAM Write Cycle (EMWRT=2 cycles)
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IP2012 / IP2022 Data Sheet
6.0
In-System Programming
Table 6-1 Connector Pin Assignments (continued) Pin 4 5 Name TSCK OSC Description Target Data Clock--Serial clock. Connect to pin 2 on the IP2012 / IP2022. Target Clock Oscillator--If the debugger/programmer is capable of supplying an OSC clock for the target system, then this clock must be configurable so that it can be disabled to prevent it from interfering with the target system (i.e. the OSC clock output is placed in a high-impedance state). Target Reset--The target system may use the TRST signal to reset the entire system, to reset only the IP2012 / IP2022, or it may ignore the TRST signal. The debugger/programmer may provide a 100-ms system reset signal (TRST) to the target system. If supported, the TRST output must be an open-collector driver to accommodate other sources of reset in the target system. The minimum source requirement for this driver is 6 mA. The debugger/programmer should not detect or be reset by the TRST signal being driven low by the target system. There is no requirement that the part be connected to the TRST signal, so the debugger/programmer cannot assume that the part has been reset if the target system pulls the TRST pin low. Target Serial Input--Sampled on the rising edge of TSCK. Connect to pin 3 on the IP2012 / IP2022. Power. 2.3 - 3.6V (optional) Target Serial Output--Driven by the IP2012 / IP2022 after the falling edge of TSCK. Connect to pin 4 on the part. The IP2012 / IP2022 drives this pin only if TSS is held low (TSO is tristated otherwise). The TSO pin is driven low if TSS is driven low while the part is in reset; TSO will be driven high as soon as the part is out of reset.
The IP2000 series devices provide a dedicated serial interface for in-system programming (ISP) of the flash program memory and configuration block. ISP allows designers to incorporate a small connector which can be used to interface to a device programmer for programming or reprogramming the part after it has been soldered to a circuit board. The interface used for in-system programming (ISP) and in-system debugging (ISD) is compatible with the SPI serial interface protocol. Whenever possible, a standard connector should be incorporated in the system design for in-system debugging and programming. The recommended connector layout for the ISD/ISP interface is shown in Figure 6-1. The connector is a male 10-pin connector with 100-mil pin spacing, whose pin assignments are listed in Table 6-1. The connector is keyed to prevent backward insertion.
6 7
Reserved Reserved TRST
1 3 5 7 9
2 4 6 8 10
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Figure 6-1 ISD/ISP Connector Signal levels on the connector are LVTTL-compatible. The target system provides the TSCK, TSI, TRST, and TSS signals with 10K ohm pullup resistors. For more information about the ISD/ISP interface and the interaction between the debugger/programmer and the target system, see the IP2000 Series User's Manual. Table 6-1 Connector Pin Assignments Pin 1 2 Name KEY TSS Description Key (not a signal) Target Slave Select--Active-low signal which enables the IP2012 / IP2022 to communicate on the SPI bus. Connect to pin 1 on the IP2012 / IP2022. Ground
8
TSI
9 10
VDD TSO
3
GND
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IP2012 / IP2022 Data Sheet
7.0
7.0.1
Memory Reference
Registers (sorted by address)
Table 7-1 shows the addresses and reset values of all special-purpose registers in data memory, sorted by their address. Table 7-1 Register Addresses and Reset State Address 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019
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Name Reserved ADDRSEL ADDRX IPH IPL SPH SPL PCH PCL WREG STATUS DPH DPL SPDREG MULH ADDRH ADDRL DATAH DATAL INTVECH INTVECL INTSPD INTF INTE INTED Reserved
Description
Register Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) Reserved 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 0000 0000 0000 1110 0000 0000 0000 0000 0000 1001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Undefined 0000 0000 0000 0000
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Selector for current external(IP2022 only)/program memory ADDRX/ADDRH/ADDRL External(IP2022 only)/program memory pointer (bits 23:16) Indirect Data RAM Pointer (high byte) Indirect Data RAM Pointer (low byte, see Section 4.1) Data RAM Stack Pointer (high byte) Data RAM Stack Pointer (low byte, see Section 4.1) Current PC (program counter) bits 15:8 (read-only) Virtual register for direct PC modification W (working) register STATUS register Data Pointer (high byte) Data Pointer (low byte, see Section 4.1) Current speed (read-only, see Section 3.5) Multiply result (high byte) External(IP2022 only)/program memory address (bits 15:8) External(IP2022 only)/program memory address (bits 7:0, see Section 5.11) External(IP2022 only)/program memory data (high byte) External(IP2022 only)/program memory data (low byte) Interrupt vector (high byte) Interrupt vector (low byte) Interrupt speed register Port B interrupt flags Port B interrupt enable bits Port B interrupt edge select bits
IP2012 / IP2022 Data Sheet
Table 7-1 Register Addresses and Reset State (continued) Address 0x01A 0x01B 0x01C FCFG TCTRL XCFG Name Description Flash configuration register Timer 1/2 common control register Extended configuration (bit 0 is read-only) Register Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) 0000 0000 0000 0000 0000 000x (See Section 7.1.26 for FBUSY)) 0000 0000 0000 0000 0000 0000 N/A 0000 0000 1111 1111 0000 0000 N/A 0000 0000 1111 1111 0000 0000 N/A 0000 0000 1111 1111 0000 0000 N/A 0000 0000 1111 1111 Reserved N/A 0000 0000 1111 1111 Reserved N/A 0000 0000 1111 1111 Reserved Reserved 0000 0000 1111 1111
0x01D 0x01E 0x01F 0x020 0x021 0x022 0x023 0x024 0x025 0x026 0x027 0x028 0x029 0x02A 0x02B 0x02C 0x02D 0x02E 0x02F 0x030 0x031 0x032 0x033 0x034 0x035 0x036 0x037 0x038 0x039 0x03A
EMCFG IPCH IPCL RAIN RAOUT RADIR LFSRH RBIN RBOUT RBDIR LFSRL RCIN RCOUT RCDIR LFSRA RDIN RDOUT RDDIR Reserved REIN REOUT REDIR Reserved RFIN RFOUT RFDIR Reserved Reserved RGOUT RGDIR
External memory configuration register (IP2022 only) Interrupt return address (high byte) Interrupt return address (low byte) Data on Port A pins Port A output latch Port A direction register LFSR data register (high byte) Data on Port B pins Port B output latch Port B direction register LFSR data register (low byte) Data on Port C pins Port C output latch Port C direction register LFSR address register Data on Port D pins Port D output latch Port D direction register Reserved Data on Port E pins Port E output latch Port E direction register Reserved Data on Port F pins Port F output latch Port F direction register Reserved Reserved Port G output latch Port G direction register
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IP2012 / IP2022 Data Sheet
Table 7-1 Register Addresses and Reset State (continued) Address 0x03B 0x03C 0x03D 0x03E 0x03F 0x040 0x041 0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B 0x04C 0x04D 0x04E 0x04F 0x050 0x051 0x052 0x053 0x054 0x055 0x056 0x057 0x058 0x059 0x05A 0x05B 0x05C 0x05D Name Reserved Reserved Reserved Reserved Reserved RTTMR RTCFG T0TMR T0CFG T1CNTH T1CNTL T1CAP1H T1CAP1L T1CAP2H/T1CMP2H T1CAP2L/T1CMP2L T1CMP1H T1CMP1L T1CFG1H T1CFG1L T1CFG2H T1CFG2L ADCH ADCL ADCCFG ADCTMR T2CNTH T2CNTL T2CAP1H T2CAP1L T2CAP2H/T2CMP2H T2CAP2L/T2CMP2L T2CMP1H T2CMP1L T2CFG1H T2CFG1L Reserved Reserved Reserved Reserved Reserved Real-time timer value Real-time timer configuration register Timer 0 value Timer 0 configuration register Timer 1 counter register high (read only) Timer 1 counter register low (read only) Timer 1 Capture 1 register high (read only) Timer 1 Capture 1 register low (read only) Timer 1 Capture 2/Compare 2 register high Timer 1 Capture 2/Compare 2 register low Timer 1 Compare 1 register high Timer 1 Compare 1 register low Timer 1 configuration register 1 high Timer 1 configuration register 1 low Timer 1 configuration register 2 high Timer 1 configuration register 2 low ADC value (high) (read only) ADC value (low) (read only) ADC configuration register ADC timer register Timer 2 counter register high (read only) Timer 2 counter register low (read only) Timer 2 Capture 1 register high (read only) Timer 2 Capture 1 register low (read only) Timer 2 Capture 2/Compare 2 register high Timer 2 Capture 2/Compare 2 register low Timer 2 Compare 1 register high Timer 2 Compare 1 register low Timer 2 configuration register 1 high Timer 2 configuration register 1 low Description Register Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) Reserved Reserved Reserved Reserved Reserved 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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IP2012 / IP2022 Data Sheet
Table 7-1 Register Addresses and Reset State (continued) Address 0x05E 0x05F 0x060 0x061 0x062 0x063 0x064 0x065 0x066 0x067 0x068 0x069 0x06A 0x06B 0x06C 0x06D 0x06E Name T2CFG2H T2CFG2L S1TMRH S1TMRL S1TBUFH S1TBUFL S1TCFG S1RCNT S1RBUFH S1RBUFL S1RCFG S1RSYNC S1INTF S1INTE S1MODE S1SMASK PSPCFG Description Timer 2 configuration register 2 high Timer 2 configuration register 2 low SERDES 1 clock timer register (high bits) SERDES 1 clock timer register (low bits) SERDES 1 transmit buffer (high bits) SERDES 1 transmit buffer (low bits) SERDES 1 transmit configuration SERDES 1 received bit count (actual) (read-only) SERDES 1 receive buffer (high bits) (read-only) SERDES 1 receive buffer (low bits) (read-only) SERDES 1 receive configuration SERDES 1 receive bit sync pattern SERDES 1 status/Interrupt flags SERDES 1 Interrupt enable bits SERDES 1 serial mode/clock select register SERDES 1 receive sync mask Parallel slave peripheral configuration register Register Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) 0000 0000 0000 0000 0000 0000 0000 0000 Undefined Undefined 0000 0000 0000 0000 Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00xx (See Section 7.1.8 for BO, WD) 0000 000X (See Section 7.1.3) 0000 0000 0000 0000 Undefined Undefined 0000 0000 0000 0000 Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000
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0x06F 0x070 0x071 0x072 0x073 0x074 0x075 0x076 0x077 0x078 0x079 0x07A 0x07B
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CMPCFG S2TMRH S2TMRL S2TBUFH S2TBUFL S2TCFG S2RCNT S2RBUFH S2RBUFL S2RCFG S2RSYNC S2INTF S2INTE
Comparator configuration register SERDES 2 clock timer register (high bits) (IP2022 only) SERDES 2 clock timer register (low bits) (IP2022 only) SERDES 2 transmit buffer (high bits) (IP2022 only) SERDES 2 transmit buffer (low bits) (IP2022 only) SERDES 2 transmit configuration (IP2022 only) SERDES 2 received bit count (actual) (read-only) (IP2022 only) SERDES 2 receive buffer (high bits) (read-only) (IP2022 only) SERDES 2 receive buffer (low bits) (read-only) (IP2022 only) SERDES 2 receive configuration (IP2022 only) SERDES 2 receive bit sync pattern (IP2022 only) SERDES 2 status/Interrupt flags (IP2022 only) SERDES 2 interrupt enable bits (IP2022 only)
IP2012 / IP2022 Data Sheet
Table 7-1 Register Addresses and Reset State (continued) Address 0x07C 0x07D 0x07E 0x07F 0x080 to 0x0FF Name S2MODE S2SMASK CALLH CALLL Description SERDES 2 serial mode/clock select register (IP2022 only) SERDES 2 receive sync mask (IP2022 only) Top of call stack (high 8 bits) Top of call stack (low 8 bits) Register Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) 0000 0000 0000 0000 1111 1111 1111 1111
Directly addressable general-purpose (global) reg- Undefined after power-on isters or brown-out reset, unchanged after RST or Watchdog Timer reset Data memory RAM Undefined after power-on or brown-out reset, unchanged after RST or Watchdog Timer reset
0x100 to 0xFFF
7.0.2
Program Memory
Table 7-2 shows the addresses and reset values of all program memory. Table 7-2 Program Memory Addresses Address 0x0000 to 0x1FFF (word addresses) 0x8000 to 0xFFFF (word addresses) Description Program Memory RAM Status Following Reset (Power-On, RST, Brown-Out RST, Watchdog RST) Undefined after power-on or brownout reset, unchanged after RST or Watchdog Timer reset Unchanged after power-on, brown-out reset, RST or Watchdog Timer reset (changes only during ISP programming, and during flash self-programming) Unchanged after power-on, brown-out reset, RST or Watchdog Timer reset (changes only during ISP programming, and during flash self-programming)
Program Memory Flash.
0x10000 to 0x1003F (word addresses)
Flash Configuration Block (see Section 3.10). Flash is factory programmed to: Word Address $ 10000 $ 10001 $ 10004 FUSE0 = 1000 FUSE1 = FFF7 TRIM0 = FBFE
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IP2012 / IP2022 Data Sheet
7.1
Register Bit Definitions
is used to provide the 1.152MHz (48 kHz 24) clock period reference clock for the A/D converter.
For those registers which have special functions assigned to bits or fields within the register, the definition of those bits and fields is described below. The registers are presented alphabetically.
7.1.3
CMPCFG Register
Comparator configuration. 7 CMPEN 6 CMPOE 5 CMPHYS 4 3 2 1 0 CMPRES
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7.1.1
ADCCFG Register
A/D converter configuration.
Reserved
7 ADCREF
6
5
4
3
2 ADCS2:0
0 Name CMPEN
ADCJST
Rsrvd. ADCGO
Description Comparator enable bit 0 = Comparator disabled 1 = Comparator enabled
Name ADCREF
Description A/D converter reference voltage select 0 = AVdd is the reference voltage 1 = RG3 port pin is used to receive an external reference voltage CMPOE
Comparator output enable bit 0 = Comparator output disabled. 1 = Comparator output enabled on port pin RG0.
ADCJST
A/D converter result justification mode select 00 = Right justified 01 = Signed 10 = Left justified 11 = Reserved
CMPHYS
Comparator hysteresis enable bit 0 = Hysteresis disabled 1 = Hysteresis enabled
CMPRES
Comparator result (read-only) 0 = RG2 voltage > RG1 1 = RG1 voltage > RG2
ADCGO
A/D converter GO/DONE bit 0 = When the last conversion has completed, this bit reads as 0. 1 = Write 1 to begin a new conversion. While the conversion is in progress, this bit reads as 1.
ADCS2:0
A/D converter input channel select 000 = Port pin RG0 001 = Port pin RG1 010 = Port pin RG2 011 = Port pin RG3 100 = Port pin RG4 101 = Port pin RG5 110 = Port pin RG6 111 = Port pin RG7
7.1.2
ADCTMR Register
The ADCTMR register is used to specify the number of system clock cycles required for a delay of 1736 ns, which
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IP2012 / IP2022 Data Sheet
7.1.4
EMCFG Register (IP2022 only)
External memory interface configuration. (Reserved in IP2012; value 0x00.) 7 6 5 EMWRT2:0 Description Enable external memory interface 0 = Port C, Port D and RB7:4 available for general-purpose I/O 1 = Port C, Port D and RB7:4 used for external memory interface EMBRT Enable bus release wait state 0 = No wait state 1 = One wait state cycle added to IREAD and IWRITE after read of DATAL and before ADDR8:1 is put on RD7:0 bus EMWRT2:0 WR pulse width, in system clock cycles 000 = 1 001 = 2 010 = 3 011 = 4 EMRDT2:0 000 = 1 001 = 2 010 = 3 011 = 4 100 = 5 101 = 6 110 = 7 111 = 8 100 = 5 101 = 6 110 = 7 111 = 8 3 2 EMRDT2:0 0
EMEN EMBRT Name EMEN
RD pulse width, in system clock cycles
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IP2012 / IP2022 Data Sheet
7.1.5
FCFG Register
Flash configuration. 7 6 5 4 3 2 1 0
FRDTS1:0 Name FRDTS1:0
FRDTC1:0
FWRT3:0 Description
The core clock frequency is automatically reduced (if necessary) when executing out of flash memory to prevent the flash memory access time from being too short. The FRDTS1:0 bits specify the minimum number of system clock cycles required for instruction execution from flash memory. The actual execution speed from flash memory will be the slower of the speed indicated in the SPDREG register and the speed specified by the FRDTS1:0 bits. The 11 setting can always be used, but it may cause slower flash operation than necessary. If System Clock Frequency (MHz) is Set to this: 120 MHz Part 00 01 10 11 0-40 40-80 80-120 reserved 160 MHz Part 0-53.3 53.3-106.7 106.7-160 reserved System Clock Cycles For Each Flash Instruction Cycle 1 cycle 2 cycles 3 cycles 4 cycles
Note FRDTC1:0
Flash instruction execution = 25ns minimum (18.75ns for 160MHz part) To prevent the flash memory access time from being too short, it is necessary to specify the number of CPU core cycles between reading the flash memory using an fread instruction (or an iread or ireadi instruction while executing from RAM to read flash) and the time that DATAH and DATAL are written by the IP2012 / IP2022. Because the CPU core is subject to changes in speed, the value programmed in these bits should be appropriate for the fastest speed that might be used (typically, the faster of the main line code and the interrupt service routine). The FRDTC1:0 bits specify the number of CPU core clock cycles required for flash read access. Even with this configured, enough cycles must be executed after the flash read instruction and before reading DATAH or DATAL to account for the minimum flash access time. Set to this: 00 01 10 11 If CPU Core Frequency (MHz) is 120 MHz Part 0-40 40-80 80-120 reserved 160 MHz Part 0-53.3 53.3-106.7 106.7-160 reserved Core Clock Cycles For Each Flash Read Cycle 1 cycle 2 cycles 3 cycles 4 cycles
Note FWRT3:0
fread/iread/ireadi of flash= 25ns minimum (18.75ns for 160MHz part) The flash memory ferase, fwrite and ISP flash write, flash block erase, or flash bulk erase timing
is derived from the CPU core clock through a programmable divider. The FWRT3:0 bits specify the divisor. The time base must be 1 to 2 microseconds. Below 1 microsecond, the flash memory will be underprogrammed, and data retention is not guaranteed. Above 2 microseconds, the flash memory will be overprogrammed, and reliability is not guaranteed. Set to this: 0000 0001 0010 0011 If CPU Core Frequency is: 1-2 MHz 2-3 MHz 3-4 MHz 4-6 MHz FWRT Frequency Divisor 2 3 4 6
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IP2012 / IP2022 Data Sheet
Name 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note: If FCFG & OSC1 are optimal:
Description 6-8 MHz 8-12 MHz 12-16 MHz 16-24 MHz 24-32 MHz 32-48 MHz 48-64 MHz 64-96 MHz 96-128 MHz 128-160 MHz Reserved Reserved 8 12 16 24 32 48 64 96 128 192 256 384
fwrite = 42us ferase = 20ms, because FPERT in TRIM0 should be 0
7.1.6
INTSPD Register
Name
Description 01 = OSC oscillator/external clock on OSC1 input 10 = RTCLK oscillator/external clock on RTCLK1 input 11 = System clock disabled (off) Note: If the OSC crystal driver is stopped (SPDREG bit 6 = 1) and Port B or Real Time Timer interrupts are enabled, then INTSPD bits 5 and 4 must not both be 0, because the crystal startup time plus PLL startup time may be greater than WUDP2:0 (see Figure 3-16).
Configuration of clock and PLL settings to be used during an interrupt service routine. INTSPD is copied to SPDREG when an interrupt occurs. See Table 3-5 for reti options. 7 PLL 6 OSC 5 4 3 CDIV3:0 Description Run-time control of PLL clock multiplier operation. If the PLL is not required, power consumption can be reduced by disabling it. 0 = PLL clock multiplier enabled 1 = PLL clock multiplier disabled OSC Run-time control of OSC oscillator operation. If the crystal oscillator is not required, power consumption can be reduced by disabling it (stops OSC oscillator and blocks propagation of OSC1 external clock input). 0 = OSC oscillator enabled 1 = OSC oscillator disabled CLK1:0 Selects the system clock source. 00 = PLL clock multiplier. Do not use if an interrupt can awaken the part from sleep (can use a speed instruction in the ISR instead). 0
CLK1:0
Name PLL
CDIV3:0 Selects the system clock divisor. 0000 = 1 0001 = 2 0010 = 3 0011 = 4 0100 = 5 0101 = 6 0110 = 8 0111 = 10 1000 = 12 1001 = 16 1010 = 24 1011 = 32 1100 = 48 1101 = 64 1110 = 128 1111 = System clock disabled (off)
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IP2012 / IP2022 Data Sheet
7.1.7
LFSRA Register
7.1.8
PSPCFG Register
Linear Feedback Shift Register configuration. 7 UNIT3:0 Name UNIT3:0 INDEX3:0 4 3 INDEX3:0 Description LFSR unit number (only 0, 1, 2, and 3 are valid) Index to the LFSR register being accessed (see Table 5-17) 0
Parallel Slave Peripheral configuration. 7 6 5 4 3 Res 1 0
PSPEN2 PSPEN1 PSPHEN PSPRDY Name PSPEN2
WD BO
Description Port D enable bit (IP2022 only) 0 = Port D is available for generalpurpose I/O 1 = Port D is configured for the Parallel Slave Peripheral interface
PSPEN1
Port C enable bit 0 = Port C is available for generalpurpose I/O 1 = Port C is configured for the Parallel Slave Peripheral interface
PSPHEN
HOLD output enable bit 0 = HOLD output disabled. Port pin RB5 available for general-purpose I/O. 1 = HOLD output enabled on port pin RB5.
PSPRDY
Ready bit 0 = This bit always reads as zero. 1 = Write 1 to release HOLD when the IP2012 / IP2022 is ready to allow the data transfer to complete.
WD
Watchdog time-out bit. If using the Watchdog feature, set this bit before the first cwdt instruction. Then this bit is not cleared by a Watchdog reset, but is cleared by all other reset sources. However, if WUDX in FUSE0 is more than 70ms longer than the watchdog timeout period in FUSE1, a Power-On Reset or a Brown-Out Reset may set this bit. (Do not use this bit if WUDX is more than 70ms longer than the watchdog timeout period). Brown-out reset bit. Set at reset, if reset was triggered by brown-out voltage level detection, otherwise cleared
BO
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IP2012 / IP2022 Data Sheet
7.1.9
RTCFG Register
Real-Time Timer configuration. 7 RTEN Name RTEN 6 RTPS3:0 3 2 1 0
RTSS RTIE RTIF Description
Real-Time Timer enable bit 0 = Real-Time Timer disabled 0 = Real-Time Timer enabled
RTPS3:0
Real-Time Timer prescaler divisor 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 = 256 1001 = 512 1010 = 1024 1011 = 2048 1100 = 4096 1101 = 8192 1110 = 16384 1111 = 32768
RTSS
Real-Time Timer clock source select 0 = external OSC clock 1 = external RTCLK clock
RTIE
Real-Time Timer interrupt enable bit 0 = Real-Time Timer interrupt disabled 1 = Real-Time Timer interrupt enabled
RTIF
Real-Time Timer interrupt flag 0 = No timer overflow has occurred since this bit was last cleared 1 = Timer overflow has occurred. This bit goes high two cycles after the actual overflow occurs.
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IP2012 / IP2022 Data Sheet
7.1.10 SxINTE/SxINTF Register
Indicates the SERDES conditions that may be enabled as interrupts. The SxINTE register has the same format as the SxINTF register. For each condition indicated by a flag in the SxINTF register, setting the corresponding bit in the SxINTE register enables the interrupt for that condition. 7 RXERROR 6 RXEOP 5 4 3 TXEOP 2 SXLINKPULSE 1 0 RXXCRS
Name TXEOP
Description Transmit underrun. This bit is set when the previous data in the transmit buffer register (SxTXBUF) has been transmitted and no new data has been loaded in the register. In USB and 10Base-T modes, this causes an EOP condition to be generated. 0 = Transmit underrun has not occurred since this bit was last cleared 1 = Transmit underrun has occurred
SYND
RXBF
TXBE
SXLINKPULSE Set after a link pulse of 60 to 200 ns duration is detected in Ethernet mode. Also known as TxIdle in USB mode. 0 = 10Base-T mode: No link pulse has been detected since this bit was last cleared USB mode: SERDES is transmitting 1 = 10Base-T mode: Link pulse detected USB mode: SERDES is not transmitting RXBF Receive buffer full interrupt flag 0 = Receive buffer has not been full since this bit was last cleared 1 = Receive buffer has been full RXXCRS Set while the carrier is sensed. 10bT mode: clear to 0 0 = USB mode: RxBUSY is detected - SERDES is receiving 1 = USB mode: RxBUSY is not detected - SERDES is not receiving
Name RXERROR
Description Receive error interrupt flag 10Base-T mode: Manchester encoding data phase error USB mode: bit unstuffing error (1111111 received) 0 = Receive error has not been detected since this bit was last cleared 1 = Receive error has been detected
RXEOP
End-of-Packet detection interrupt flag 10Base-T and USB modes: end-ofpacket detected GPSI mode: RxEN deasserted SPI mode: Set on rising edge. 0 = End-of-Packet has not been detected since this bit was last cleared 1 = End-of-Packet has been detected
SYND
Synchronization pattern detection interrupt flag (10Base-T and USB modes only) 0 = Synchronization pattern has not been detected since this bit was last cleared 1 = Synchronization pattern has been detected
TXBE
Transmit buffer empty interrupt flag 0 = Transmit buffer has not been empty since this bit was last cleared 1 = Transmit buffer has been empty
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IP2012 / IP2022 Data Sheet
7.1.11 SxMODE Register
SERDES protocol mode configuration. 7 REV Name REV PRS2:0 6 5 PRS2:0 4 3 2 1 0
Name CLKS1:0
Description Clock source select (see Figure 5-8). 00 = Clock disabled 01 = SxCLK input 10 = OSC clock oscillator 11 = post-PLL clock Note: When switching CLKS1:0 to 10, a delay is needed before reliable writes to SERDES registers can be made. The required delay, in number of core instructions, is (core clock frequency / new SERDES clock frequency) x 2.
SUBM1:0 Description
CLKS1:0
Read-only as "1" in latest revision. Refer to IP2022 silicon errata sheet. Protocol select (see Table 5-3). All other encodings are reserved. 000 = Disabled 001 = 10Base-T 010 = USB Bus 011 = UART 101 = SPI 110 = GPSI
7.1.12 SxRCFG Register
SERDES RX shift count, USB sync detect and data polarity configuration. 7 6 5 4 RXSCNT4:0 0
SUBM1:0
Submode select USB mode: 01 = Low-speed USB interface 10 = High-speed USB interface SPI mode: 00 = Positive clock polarity, receive on rising edge, transmit on falling edge 01 = Positive clock polarity, receive on falling edge, transmit on rising edge 10 = Negative clock polarity, receive on falling edge, transmit on rising edge 11 = Negative clock polarity, receive on rising edge, transmit on falling edge GPSI mode: 00 = Receive on rising edge, transmit on falling edge 01 = Receive on falling edge, transmit on falling edge 10 = Receive on rising edge, transmit on rising edge 11 = Receive on falling edge, transmit on rising edge
MASSEL SYNCDETEN RPOREV Name MASSEL
Description 10Base-T mode: 0 = Normal polarity detected 1 = Reverse polarity detected GPSI or SPI mode: 0 = Slave mode 1 = Master mode
SYNCDETEN
Synchronization byte detection enable (USB mode only) 0 = Synchronization byte detection enabled 1 = Synchronization byte detection disabled
RPOREV
Receive data polarity reversal select 0 = Data polarity uninverted 1 = Data polarity inverted
RXSCNT4:0
Receive shift count, specifies number of bits to receive
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IP2012 / IP2022 Data Sheet
7.1.13 SxRCNT Register
SERDES RX activity configuration. 7 6 5 4 RXACNT4:0 0
7.1.14 SxRSYNC Register
SERDES sync pattern configuration. 7 SYNCPAT7:2 Name SYNCPAT7:2 2 1 0
BITORDER RxCRSED RxCRS Name BITORDER
SQUELCHEN DRIBBITEN Description
Description Bit order for transmit and receive 0 = LSB first 1 = MSB first
Synchronization pattern, bits 7:2 (USB mode only)
RxCRSED
Not used for 10baseT mode. For GPSI Slave mode: 0 = Disable TxBUSY input 1 = Enable TxBUSY input
SQUELCHEN USB mode: synchronization pattern, bit 1 10Base-T mode: 0 = Squelch disabled 1 = Squelch enabled All other modes: 0 DRIBBITEN USB mode: synchronization pattern, bit 0 10Base-T mode: 0 = Hardware handles dribble bit 1 = Software is responsible for handling dribble bit
RxCRS RXACNT4:0
Carrier Sense Status: Current state of carrier Receive shift count, actual number of bits received (read-only). Exceptions occur during the last transfer: RXACNT = 0 if bit count is less than 8 RXACNT = 8 if bit count is greater than or equal to 8, but less than 16 RXACNT = 16 if bit count is greater than or equal to 16 and the RXSCNT4:0 field in the SxRCFG register is 16
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IP2012 / IP2022 Data Sheet
7.1.15 SxSMASK Register
SERDES sync-pattern configuration. 10Base-T mode: 7 6 3 2 1 0
7.1.16 SxTCFG Register
SERDES TX shift count configuration. 7 6 5 4 TXSCNT4:0 0
GLOBEN LPBACK TPOREV Name
Resrvd. PREAMCNT3:0 Resrvd. CONTPAIR Resrvd. Description Global enable bit 0 = Disable SERDES output 1 = Enable SERDES output (must use for TX). If enabling SERDES1, the REOUT port data are overridden by SERDES1 outputs. If enabling SERDES2 (IP2022 only), the RFOUT port data are overridden by SERDES2 outputs. LPBACK Loopback enable bit 0 = Normal operation 1 = Output is driven into input TPOREV Transmit data polarity reversal select (UART mode only) 0 = Data polarity uninverted 1 = Data polarity inverted TXSCNT4:0 Transmit shift count, specifies number of bits to transmit USB mode: 7 MASK7:0 Name PREAMCNT3:0 Description Preamble pair count (10Base-T mode only). All other encodings are reserved. 0000 = 24 pairs 0001 = 20 pairs 0010 = 16 pairs 0011 = 12 pairs 0100 = 8 pairs 0101 = 4 pairs CONTPAIR Configures the detection of consecutive pairs of "10" for sync detection. 0 = Sync detected if 6 "10" pairs + "11". 1 = Use PREAMCNT for number of "10" pairs MASK7:0 Mask bits for SxRSYNC (USB mode only) 0 = Ignore corresponding bit in SxRSYNC 1 = Use corresponding bit in search pattern for synchronization byte 0 GLOBEN
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IP2012 / IP2022 Data Sheet
7.1.17 SxTMRH/SxTMRL Register
Used to specify the divide value for the OSC clock, postPLL clock or SxCLK input (specified in the SxMode register bits CLKS1:0, Section 7.1.11) to generate the SERDES clock. The effective divide value = {SxTMRH, SxTMRL} + 1, except, in the case of SPI and GPSI Master, the effective divide value = {(SxTMRH/SxTMRL) + 1} x 2.
Name CDIV3:0
Description Selects the divisor which divides the system clock to give the core clock. 0000 = 1 0001 = 2 0010 = 3 0011 = 4 0100 = 5 0101 = 6 0110 = 8 0111 = 10 1000 = 12 1001 = 16 1010 = 24 1011 = 32 1100 = 48 1101 = 64 1110 = 128 1111 = System clock disabled (off)
7.1.18 SPDREG Register
Status of clock and PLL settings during run-time. Note: This is a read-only register, use speed instruction to change settings. 7 PLL 6 OSC 5 4 3 CDIV3:0 Description Run-time control of PLL clock multiplier operation. If the PLL is not required, power consumption can be reduced by disabling it, but a WUDP delay is required to start it again (controlled in FUSE0). 0 = PLL clock multiplier on 1 = PLL clock multiplier off OSC Run-time control of OSC oscillator operation. If the OSC clock is not required, power consumption can be reduced by disabling it (stops OSC crystal oscillator and blocks propagation of OSC1 external clock input). 0 = OSC oscillator enabled 1 = OSC oscillator disabled CLK1:0 Selects the system clock source. 00 = PLL clock multiplier 01 = OSC oscillator/external clock on OSC1 input 10 = RTCLK oscillator/external clock on RTCLK1 input 11 = System clock disabled (off) 0
CLK1:0
Name PLL
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IP2012 / IP2022 Data Sheet
7.1.19 STATUS Register
Condition flags for the results of arithmetic and logical operations, the page bits, and bits which indicate the skipping state of the core and control of continuation skip after return from interrupt. 7 PA2:0 Name PA2:0 5 4 SAR 3 SSF 2 Z 1 DC 0 C Z
Name
Description Zero bit. Affected by most logical, arithmetic, and data movement instructions (refer to "Flags Affected" column in Table 4-2 through Table 4-7). Set if the result was zero, otherwise cleared. 0 = Result of last ALU operation was non-zero. 1 = Result of last ALU operation was zero.
Description Program memory page select bits (read only). Used to extend the 13-bit address encoded in jump and call instructions (these 3 bits are written to the upper 3 bits of the program counter when a jump or call occurs). Modified using the page instruction. Skip After Return bit. Indicates if the core should be in the skipping/not state after the completion of a return instruction (ret, retnp, or retw instructions, but not reti). The return instruction will also clear the SAR bit to ensure correct behavior after the dynamic jump. 0 = The core should not be in a skipping state upon completion of the return. 1 = The core should be in a skipping state upon completion of the return. DC
Digit Carry bit. After addition, set if carry from bit 3 occurred, otherwise cleared. After subtraction, cleared if borrow from bit 3 occurred, otherwise set. 0 = Last addition did not generate carry out of bit 3, or last subtraction generated borrow out of bit 3. 1 = Last addition generated carry out of bit 3, or last subtraction did not generate borrow out of bit 3.
SAR
C
Carry bit. After addition, set if carry from bit 7 of the result occurred, otherwise cleared. After subtraction, cleared if borrow from bit 7 of the result occurred, otherwise set. After rotate (rr or rl) instructions, loaded with the LSB or MSB of the operand, respectively. 0 = Last addition did not generate carry out of bit 7, last subtraction generated borrow out of bit 7, or last rotate loaded a 0. 1 = Last addition generated carry out of bit 7, last subtraction did not generate borrow out of bit 7, or last rotate loaded a 1.
SSF
Shadowed Skipping/not state Flag. Gives the ISR the ability to know if the interrupt occurred immediately following a skip instruction. The software can choose either to clear the SSF flag in the ISR or to make the first instruction of the mainline context switching code a nop to flush out the skip state. 0 = The core was not in a skipping state when interrupted. 1 = The core was in a skipping state when interrupted.
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IP2012 / IP2022 Data Sheet
7.1.20 T0CFG Register
Timer 0 configuration. 7 T0EN Name T0EN 6 T0PS3:0 3 2 1 0 T0IF
Name CMP2IE
Description Capture/Compare mode: Capture 2 interrupt enable bit 0 = Capture/Compare 2 interrupt disabled 1 = Capture/Compare 2 interrupt enabled
Rsrvd. T0IE Description
Enables Timer 0 0 = Timer 0 disabled 1 = Timer 0 enabled
CAP1IE
Capture 1 interrupt enable bit 0 = Capture 1 interrupt disabled 1 = Capture 1 interrupt enabled
T0PS3:0
Specifies Timer 0 prescaler divisor 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 = 256 1001 to 1111 = Reserved
CMP1IE
Compare 1 interrupt enable bit 0 = Compare 1 interrupt disabled 1 = Compare 1 interrupt enabled
OFIF
Timer overflow interrupt flag 0 = No timer overflow has occurred since this bit was last cleared 1 = Timer overflow has occurred
CAP2IF or CMP2IF
PWM mode: Compare 2 interrupt flag (i.e. timer value matched TxCMP2 value) Capture/Compare mode: Capture 2 flag (i.e. TxCPI2 input triggered) 0 = No capture/compare 2 event has occurred since this bit was last cleared 1 = Capture/compare 2 event has occurred
T0IE
Timer 0 interrupt enable bit 0 = Timer 0 interrupt disabled 1 = Timer 0 interrupt enabled
T0IF
Timer 0 interrupt flag 0 = No timer overflow has occurred since this bit was last cleared 1 = Timer overflow has occurred
CAP1IF
Capture 1 interrupt flag 0 = No capture 1 event has occurred since this bit was last cleared 1 = Capture 1 event has occurred
7.1.21 TxCFG1H Register
Timer 1 and 2 configuration. 7 OFIE 6 CAP2IE CMP2IE 5 CAP1IE 4 CMP1IE 3 OFIF 2 CAP2IF CMP2IF 1 CAP1IF 0 CMP1IF
CMP1IF
Compare 1 interrupt flag 0 = No compare 1 event has occurred since this bit was last cleared 1 = Compare 1 event has occurred
Name OFIE
Description Timer overflow interrupt enable bit 0 = Overflow interrupt disabled 1 = Overflow interrupt enabled
CAP2IE or
PWM mode: Compare 2 interrupt enable bit
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IP2012 / IP2022 Data Sheet
7.1.22 TxCFG2H Register
Timer 1 and 2 configuration. 7 0 Name PS3:0 6 0 5 0 4 0 3 PS3:0 0
Name
Description 1 = TxCLK enabled as clock source for timer. Enabling this bit does not make any other restrictions on the use of the TxCLK port pin for general-purpose I/O.
Description Timer prescaler divisor 0000 = 1 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 = 256 1001 = 512 1010 = 1024 1011 = 2048 1100 = 4096 1101 = 8192 1110 = 16384 1111 = 32768
CPI2EN
TxCPI2 enable bit 0 = System clock enabled as clock source for timer. TxCPI2 port pin available for general-purpose I/O. 1 = TxCLK enabled as clock source for timer. Enabling this bit does not make any other restrictions on the use of the port pin for general-purpose I/O.
CPI1EN
TxCPI1 enable bit 0 = Capture 1 input disabled. TxCPI1 port pin available for general-purpose I/O.
7.1.23 TxCFG1L Register
Timer 1 and 2 configuration. 7 MODE 6 OEN 5 ECLKEN 4 CPI2EN 3 CPI1EN 2 ECLKEDG 1 CAP1RST 0 TMREN
1 = TxCPI1 enabled as capture 1 input. Enabling this bit does not make any other restrictions on the use of the port pin for general-purpose I/O. ECLKEDG TxCLK edge sensitivity select. (This bit is ignored if the ECLKEN bit is clear.) 0 = TxCLK increments timer on rising edge 1 = TxCLK increments timer on falling edge CAP1RST Reset timer on capture 1 event enable bit 0 = Timer value unchanged by occurrence of a capture 1 event 1 = Timer value cleared by occurrence of a capture 1 event TMREN Timer enable bit 0 = Timer disabled. Timer clock source shut off to reduce power consumption. 1 = Timer enabled
Name MODE
Description Timer mode select 0 = PWM/timer mode 1 = Capture/compare mode
OEN
TxOUT enable bit 0 = TxOUT disabled. Port pin available for general-purpose I/O. 1 = TxOUT enabled. Port pin must be configured for output in corresponding RxDIR register bit. Output is on RA3 for T1, RB3 for T2
ECLKEN
TxCLK enable bit 0 = TxCLK disabled. Port pin available for general-purpose I/O.
102
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IP2012 / IP2022 Data Sheet
7.1.24 TxCFG2L Register
Timer 1 and 2 configuration. 7 Reserved 6 TOUTSET 5 TOUTCLR 4 CPI2CPI1 3 CPI2EDG1:0 2 1 CPI1EDG1:0 0
Name
Description 00 = Falling edge on TXCPI1 recognized as capture 1 event 01 = Rising edge on TXCPI1 recognized as capture 1 event 10 = Any falling or rising edge on TXCPI1 recognized as capture 1 event 11 = Any falling or rising edge on TXCPI1 recognized as capture 1 event
CPI1EDG1:0 TxCPI1 edge sensitivity select
Name TOUTSET
Description Override bit to set the TxOUT output. This bit always reads as zero. 0 = Writing 0 to this bit has no effect 1 = Writing 1 to this bit forces the TxOUT signal high
TOUTCLR
Override bit to clear the TxOUT output. This bit always reads as zero. 0 = Writing 0 to this bit has no effect 1 = Writing 1 to this bit forces the TxOUT signal low
CPI2CPI1
Internally connect the TxCPI2 input to the TxCPI1 input. This makes the TxCPI2 port pin available for generalpurpose I/O. 0 = No internal connection between TxCPI1 and TxCPI2 1 = TxCPI1 and TxCPI2 internally connected
CPI2EDG1:0 TxCPI2 edge sensitivity select 00 = Falling edge on TXCPI2 recognized as capture 2 event 01 = Rising edge on TXCPI2 recognized as capture 2 event 10 = Any falling or rising edge on TXCPI2 recognized as capture 2 event 11 = Any falling or rising edge on TXCPI2 recognized as capture 2 event
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IP2012 / IP2022 Data Sheet
7.1.25 TCTRL Register
Timer 1 and 2 configuration. 7 0 6 0 5 T2IE 4 T1IE 3 0 2 0 1 0
7.1.26 XCFG Register
Extra configuration bits for various functions. 7 6 5 4 3 21 0
T2RST T1RST
GIE FWP RTEOS RTOSC_EN INT_EN Rsvd FBUSY Name GIE Description Global interrupt enable bit 0 = Interrupts disabled 1 = Interrupts enabled FWP Flash write protect bit. This bit only affects operation of fwrite and ferase self-programming instructions on flash, not programming through the ISD/ISP interface. Does not affect writes or erases of RAM. 0 = Writes to flash memory disabled (act as nop instructions) 1 = Writes to flash memory enabled RTEOS Real-time timer oversampling bit 0 = Oversampling disabled 1 = Oversampling enabled RTOSC_EN RTCLK oscillator enable bit 0 = RTCLK oscillator is operational 1 = RTCLK oscillator turned off INT_EN
Name T2IE
Description Timer 2 interrupt enable 0 = Timer 2 interrupt disabled 1 = Timer 2 interrupt enabled
T1IE
Timer 1 interrupt enable 0 = Timer 1 interrupt disabled 1 = Timer 1 interrupt enabled
T2RST
Timer 2 reset bit. This bit always reads as zero. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit clears Timer 2.
T1RST
Timer 1 reset bit. This bit always reads as zero. 0 = Writing 0 to this bit has no effect. 1 = Writing 1 to this bit clears Timer 1.
int instruction interrupt enable bit 0 = int instructions only increment the PC, like nop 1 = int instructions cause interrupts Flash memory busy bit (read-only). For more information about programming the flash memory, see Section 4.7. 0 = Flash memory is idle 1 = Fetching instructions out of flash memory or busy processing an iread, ireadi, fwrite, fread or ferase instruction on Flash
FBUSY
104
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IP2012 / IP2022 Data Sheet
8.0
8.1
Electrical Characteristics
Absolute Maximum Ratings (beyond which permanent damage may occur. Correct operation not guaranteed outside of DC specifications in Section 8.2) Parameter Minimum -40 -65 60 10 -0.5 -0.5 -0.5 -0.5 Maximum 85 150 2.5 110 3.0 40 5 3.5 4.5 5.7 3.5 1 400 400 160 160 20 160 160 200 48 37 20K 20K 2000 200 Units C C C/sec sec C/sec sec C/sec V V V V W mA mA mA mA mA mA mA mA C/W C/W Cycles Cycles V V
Ambient temperature under bias Storage temperature PQFP Soldering temperature ramp to 160-180C PQFP Soldering hold time at 160-180C PQFP Soldering temperature ramp from 160-180C to 240C maximum PQFP Soldering hold time at 240C maximum PQFP Soldering temperature ramp down to 180C Voltage on DVdd, XVdd, AVdd, and GVdd with respect to Vss Voltage on IOVdd with respect to Vss Voltage on Port A through Port F, OSC1, RST, RTCLK1, TSCK, TSI, and TSS inputs with respect to Vss Voltage on Port G inputs with respect to Vss Total power dissipation Maximum current out of all DVss pins Maximum current into all DVdd pins Maximum allowable sink current per I/O pin Maximum allowable source current per I/O pin (excluding port G) Maximum allowable source current per G pin Maximum allowable sink current per group of I/O pins between IOVss pins Maximum allowable source current per group of I/O pins between IOVdd pins (excluding port G) Latchup JA, 80-pin PQFP Package JA, 80-pin BGA Package Flash block erase cycle lifetime (if using 20ms block erases - Section 7.1.5) Flash bulk erase cycle lifetime ESD Human Body Model - all pins ESD Machine Model - all pins
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IP2012 / IP2022 Data Sheet
8.2
DC Specifications: IP2022-120, IP2012-120
Operating Temperature -40C < Ta < +85C Symbol DVdd AVdd GVdd XVdd IOVdd Idd Parameter Digital supply voltage Analog supply voltage Port G supply voltage PLL supply voltage I/O supply voltage (except Port G) Supply current, full operation DVdd + AVdd + GVdd + XVdd Min 2.3 2.3 2.3 2.3 Typ 2.5 2.5 2.5 2.5 Max 2.7 2.7 2.7 2.7 3.6 Units V V V V V mA = DVdd (filters between supplies) = DVdd (filters between supplies) = DVdd (filters between supplies) See note 4 DVdd = 2.3 - 2.7V, 120 MHz CPU core executing 100% of time (during ISR and main program code) DVdd = 2.5V, 120 MHz CPU core in ISR only, 40MHz CPU core in main program code (Webserver application) IOVdd = DVdd - 3.6V No loads, no floating inputs DVdd = 2.7V, PLL and oscillators off (XCFG bit 4 = 1, CMPCFG bit 7 = 0, ADCCFG bit 3 = 0, XCFG bit 0 = 0, FUSE1 bit 3 = 0) IOVdd = 3.6V, PLL and oscillators off, No loads, no floating inputs DVdd = 2.3 - 2.7V, IOVdd = DVdd - 3.6V Conditions
> DVdd 2.5/3.3 150
70
mA
IddIO Isleep
Supply current, full operation IOVdd only Supply current, sleep DVdd + AVdd + GVdd + XVdd Supply current, sleep IOVdd only Input high voltage, Port A through Port F Input high voltage, OSC1 and RTCLK1 inputs Input high voltage, RST, TSCK, TSI, and TSS inputs 1.8 1.8 2.25 5.5 DVdd 5.5 1.0 0.4 0.9 AVdd -1 0.001 1 200
mA A
IsleepIO
A
Vih
V V V V V V V A
Vil
Input low voltage, Port A through Port F Input low voltage, OSC1 and RTCLK1 inputs Input low voltage, RST, TSCK, TSI, and TSS inputs
DVdd = 2.3 - 2.7V, IOVdd = DVdd - 3.6V
Vina Iil
Analog input voltage (Port G) Input leakage current for Port A through Port G, RTCLK1, and TSO pins
See note 1 Port G = 0V or AVdd (see note 1), RTCLK1 = 0V or DVdd All other inputs = 0V or 5.5V TSO measured while TSS = 1 RTCLK1 measured in sleep mode and FUSE0 bit 14 = 1
106
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IP2012 / IP2022 Data Sheet
Symbol Iil
Parameter Input leakage current for OSC1 pin Input pull-up/down leakage current for Port A through Port F pins Input leakage current for RST, TSCK, TSI, TSS inputs
Min -1
Typ
Max 10
Units A
Conditions OSC1 = 0V or DVdd OSC1 measured in sleep mode and FUSE0 bit 15 = 1 See note 3.
Iil
-300
-
100
A
Iilt
-60
1
A
Vin = 0 to 5.5V. These pins have active internal pull-ups to a diode drop below IOVdd. See note 5. (60KOhm min., 103KOhm typ., 173KOhm max) Voh = 2.4V IOVdd = 3.0 to 3.6V
Ioh
Output high current from Port A pins and RE5, RE6, RF1 and RF2 pins Output high current from Port B pins and RE4:0, RE7, RF7:3, RF0, and TSO pins Output high current from Port C and Port D pins Output high current from Port G pins
24
60
96
mA
11
24
39
mA
8 4 25
18 12 40
29 24 50
mA mA mA Voh = 1.8V GVdd = 2.3 to 2.7V Vol = 0.4V IOVdd = 3.0 to 3.6V
Iol
Output low current from Port A pins and RE5, RE6, RF1 and RF2 pins Output low current from Port B pins and RE4:0, RE7, RF7:3, RF0, and TSO pins Output low current from Port C and Port D pins Output low current from Port G pins
9
16
24
mA
6 4
11 13
15 24
mA mA Vol = 0.4V GVdd = 2.3 to 2.7V
1. If Vref is used for the ADC reference voltage (see Section 5.7.1), then the maximum input voltage on a Port G input is Vref. 2. Data in the Typical ("Typ") column is at 2.5/3.3V, 25C unless otherwise stated. 3. The Port A through Port F pins have a weak latch, even when the pin is configured as an input, which drives floating I/O pins to 0V or to a diode drop below DVdd. Some current is required to toggle the state of the latch. 4. If IOVdd rises before DVdd, the IP2012 / IP2022 may drive the I/O pins to IOVdd before DVdd has stabilized. However, there is an internal diode from DVdd to IOVdd, so DVdd should never exceed IOVdd. 5. These pins are guaranteed to pull up above their Vih level, even if IOVdd = DVdd = 2.3V.
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IP2012 / IP2022 Data Sheet
8.3
DC Specifications: IP2022-160
Operating Temperature 0C < Ta < +55C Symbol DVdd AVdd GVdd XVdd IOVdd Idd Parameter Digital supply voltage Analog supply voltage Port G supply voltage PLL supply voltage I/O supply voltage (except Port G) Supply current, full operation DVdd + AVdd + GVdd + XVdd Min 2.55 2.55 2.55 2.55 > DVdd Typ 2.625 2.625 2.625 2.625 2.625/ 3.3 Max 2.70 2.70 2.70 2.70 3.6 Units V V V V V mA = DVdd (filters between supplies) = DVdd (filters between supplies) = DVdd (filters between supplies) See note 4 DVdd = 2.55 - 2.70V, 160 MHz CPU core executing 100% of time (during ISR and main program code) DVdd = 2.625V, 160 MHz CPU core in ISR only, 53.33MHz CPU core in main program code (Webserver application) IOVdd = DVdd - 3.6V No loads, no floating inputs DVdd = 2.70V, PLL and oscillators off (XCFG bit 4 = 1, CMPCFG bit 7 = 0, ADCCFG bit 3 = 0, XCFG bit 0 = 0, FUSE1 bit 3 = 0) IOVdd = 3.6V, PLL and oscillators off, No loads, no floating inputs DVdd = 2.55 - 2.70V, IOVdd = DVdd - 3.6V Conditions
mA
IddIO Isleep
Supply current, full operation IOVdd only Supply current, sleep DVdd + AVdd + GVdd + XVdd Supply current, sleep IOVdd only Input high voltage, Port A through Port F Input high voltage, OSC1 and RTCLK1 inputs Input high voltage, RST, TSCK, TSI, and TSS inputs 1.8 1.8 2.25 5.5 DVdd 5.5 1.0 0.4 0.9 AVdd -1 0.001 1 200
mA A
IsleepIO
A
Vih
V V V V V V V A
Vil
Input low voltage, Port A through Port F Input low voltage, OSC1 and RTCLK1 inputs Input low voltage, RST, TSCK, TSI, and TSS inputs
DVdd = 2.55 - 2.70V, IOVdd = DVdd - 3.6V
Vina Iil
Analog input voltage (Port G) Input leakage current for Port A through Port G, RTCLK1, and TSO pins
See note 1 Port G = 0V or AVdd (see note 1), RTCLK1 = 0V or DVdd All other inputs = 0V or 5.5V TSO measured while TSS = 1 RTCLK1 measured in sleep mode and FUSE0 bit 14 = 1
108
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IP2012 / IP2022 Data Sheet
Symbol Iil
Parameter Input leakage current for OSC1 pin Input pull-up/down leakage current for Port A through Port F pins Input leakage current for RST, TSCK, TSI, TSS inputs
Min -1
Typ
Max 10
Units A
Conditions OSC1 = 0V or DVdd OSC1 measured in sleep mode and FUSE0 bit 15 = 1 See note 3.
Iil
-80
-
80
A
Iilt
-60
1
A
Vin = 0 to 5.5V. These pins have active internal pull-ups to a diode drop below IOVdd. See note 5. (60KOhm min., 103KOhm typ., 173KOhm max) Voh = 2.4V IOVdd = 3.0 to 3.6V
Ioh
Output high current from Port A pins and RE5, RE6, RF1 and RF2 pins Output high current from Port B pins and RE4:0, RE7, RF7:3, RF0, and TSO pins Output high current from Port C and Port D pins Output high current from Port G pins
24
60
96
mA
11
24
39
mA
8 4 25
18 12 40
29 24 50
mA mA mA Voh = 1.8V GVdd = 2.55 to 2.70V Vol = 0.4V IOVdd = 3.0 to 3.6V
Iol
Output low current from Port A pins and RE5, RE6, RF1 and RF2 pins Output low current from Port B pins and RE4:0, RE7, RF7:3, RF0, and TSO pins Output low current from Port C and Port D pins Output low current from Port G pins
9
16
24
mA
6 4
11 13
15 24
mA mA Vol = 0.4V GVdd = 2.55 to 2.70V
1. If Vref is used for the ADC reference voltage (see Section 5.7.1), then the maximum input voltage on a Port G input is Vref. 2. Data in the Typical ("Typ") column is at 2.625/3.3V, 25C unless otherwise stated. 3. The Port A through Port F pins have a weak latch, even when the pin is configured as an input, which drives floating I/O pins to 0V or to a diode drop below DVdd. Some current is required to toggle the state of the latch. 4. If IOVdd rises before DVdd, the IP2022 may drive the I/O pins to IOVdd before DVdd has stabilized. However, there is an internal diode from DVdd to IOVdd, so DVdd should never exceed IOVdd. 5. These pins are guaranteed to pull up above their Vih level, even if IOVdd = DVdd = 2.55V.
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IP2012 / IP2022 Data Sheet
8.4
AC Specifications: IP2022-120, IP2012-120
Operating Temperature: -40C < Ta < +85C Symbol Fcore Fflash Fsys Fosc Foscr Fxo Fpll Fxr Tosl, Tosh Trl, Trh SVdd Parameter CPU core clock frequency CPU core clock frequency System clock frequency External clock frequency on OSC1 External clock frequency on RTCLK1 Crystal frequency, OSC PLL input frequency, after predivider Crystal frequency, RTCLK Clock in (OSC1) low or high time Clock in (RTCLK1) low or high time DVdd slew rate to ensure Power-On reset Min 0 0 0 0 0 4.75 4.75 32.765 3 3.5 0.05 4.8 4.8 32.768 Typ Max 120 40 120 120 120 5.0 5.0 32.771 Units MHz MHz MHz MHz MHz MHz MHz kHz ns ns V/ms See note 6. Ext. crystal, 100 ppm TRIM0=FBFE Ext. 32.768 KHz crystal, 100 ppm Conditions Execution from program RAM Execution from program flash
6. Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset circuitry. If power supply takes more than 50ms to rise from 0 to 2.5V, use RCs on RST pin (see Figure 3-16).
110
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IP2012 / IP2022 Data Sheet
8.5
AC Specifications: IP2022-160
Operating Temperature: 0C < Ta < +55C Symbol Fcore Fflash Fsys Fosc Foscr Fxo Fpll Fxr Trl, Trh SVdd Parameter CPU core clock frequency CPU core clock frequency System clock frequency External clock frequency on OSC1 External clock frequency on RTCLK1 Crystal frequency, OSC PLL input frequency, after predivider Crystal frequency, RTCLK Ext. clock in (RTCLK1) low or high time DVdd slew rate to ensure Power-On reset 32.765 3 3.5 0.05 Min 0 0 0 0 0 3.2 3.2 32.768 32.771 Typ Max 120 or 160 40 or 53.33 120 or 160 120 120 Units MHz MHz MHz MHz MHz MHz MHz kHz ns ns V/ms See Note 7. Ext. crystal, 100 ppm. See Note 8. TRIM0=FBFD. See Note 8. Ext. crystal, 100 ppm Conditions Execution from program RAM. See Note 8. Execution from program flash. See Note 8. See Note 8.
Tosl, Tosh Ext. clock in (OSC1) low or high time
7. Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset circuitry. If power supply takes more than 50ms to rise from 0 to 2.5V, use RCs on RST pin (see Figure 3-16). 8. The 160MHz part is specified for everything the 120MHz part is specified for (except temperature range), and it will also run at 160MHz. CPU core clock and system clock frequencies between 120 and 160MHz are not guaranteed, because the PLL input frequency is only specified for 4.75-5MHz (with TRIM0=FBFE) to get a system clock up to 120MHz, or at 3.2MHz (with TRIM0=FBFD) to get 160MHz. See Figure 3-18, and configure FUSE0, TRIM0, and FCFG correctly. Typically customers who buy 160MHz parts will only use a 3.2MHz crystal, giving 3.2MHz into the PLL, and a 160MHz system clock, with TRIM0=FBFD and FUSE0 bits 15, 11, 10, and 9 = 0.
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111
IP2012 / IP2022 Data Sheet
8.6
Comparator DC and AC Specifications
Operating Temperature: -40C < Ta < +85C for IP2022-120 and IP2012-120; 0C < Ta < +55C for IP2022-160. Parameter Input offset voltage Hysteresis, rising or falling edge Bandwidth Response time 20 Min Typ 10 50 15 100 Max 25 80 Units mV mV MHz ns min. 100 mV peak-to-peak Voverdrive = 50 mV Does not include comparator mode entry stabilization time Conditions CMPT2:0 bits in TRIM0 register are 111
Time from enabling comparator until output is valid Input voltage range 0.1
2000 AVdd - 0.1
ns V
8.7
ADC 10-bit Converter DC and AC Specifications
Vref = AVdd, -40C < Ta < +85C for IP2022-120, IP2012-120; 0C < Ta < +55C for IP2022-160 Parameter Sampling Rate Conversion Time Differential nonlinearity error (DNL) Integral nonlinearity error (INL) Offset error Full-scale error Min Typ Max 48 20.8 1.0 1.25 1.0 1.0 Units kHz s LSB LSB LSB LSB Conditions
112
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IP2012 / IP2022 Data Sheet
9.0
9.1
Package Dimensions
PQFP
80-pin, 14 mm 20 mm 2.8 mm body, 0.8 mm pitch, 17.9 mm 23.9 mm tip-to-tip. All dimensions in mm.
c
Pin
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c
Gauge Plane
113
IP2012 / IP2022 Data Sheet
9.2
BGA (available for IP2022-120 only)
80-pin, 9 mm 9 mm 0.95 mm body, 0.8 mm ball spacing
0.10 A D B DETAIL A 10 8 6 4 2 97531 A B C D E F G H J K e (D1) BOTTOM VIEW
E
(E1)
e
SIDE VIEW
D2 TOP VIEW
f f
NX
0.15 S 0.075
b C
S
A C
S
B
S
b
4
DETAIL B
ccc c C A2 DETAIL A A1 A aaa C bbb 6
C C
SEATING PLANE
DIMENSIONAL REFERENCE REF. MIN. NOM. MAX. 1.21 1.31 A 1.11 0.26 0.31 A1 0.21 0.75 A2 0.70 0.65 9.00 D 8.80 9.20 7.20 BSC D1 9.00 D2 8.80 9.20 E 9.00 8.80 9.20 7.20 BSC E1 E2 8.80 9.00 9.20 b 0.49 0.39 0.44 c 0.25 aaa 0.12 bbb 0.10 0.10 ccc e 0.80 BSC 1.00 0.80 0.90 f 10 M 80 N
5
1. All Dimensins are in millimeters. 2. 'e' represents the basic solder ball pitch. 3. 'M' represents the basic solder ball matrix size, and symbol 'N' is the number of balls after depopulating. 4. 'b' is measureable at the maximum solder ball diameter after reflow parallel to primary datum - C - . 5. Dimension 'aaa' is measured parallel to primary datum - C - . 6. Primary datum - C - and seating plane are defined by the spherical crowns of the solder balls. 7. Package surface shall be matte finish charmilles 24 to 27. 8. package centering to substrate shall be 0.0760mm maximum for both x and y direction respectively. 9. Package warp shall be 0.050mm maximum. 10. Substrate material base is BT resin. 11. The overall package thickness 'A' already considers collapse balls. 12. Dimensioning and tolerancing per ASME Y14.5-1994.
114
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IP2012 / IP2022 Data Sheet
10.0 Part Numbering
Table 10-1 Ordering Information Device Pins I/O Package 80 80 80 80 48 52 52 52 PQFP PQFP BGA PQFP Program Flash Program RAM Data RAM 4KBytes 4KBytes 4KBytes 4KBytes Temperature -40 to 85C -40 to 85C -40 to 85C 0 to 55C
IP2012/PQ80-120 IP2022/PQ80-120 IP2022/BG80-120 IP2022/PQ80-160
64KBytes (32K x 16) 16KBytes (8K x 16) 64KBytes (32K x 16) 16KBytes (8K x 16) 64KBytes (32K x 16) 16KBytes (8K x 16) 64KBytes (32K x 16) 16KBytes (8K x 16)
IP 2022 / xx80 - xxx
MIPS Rating Package Type, PQ80 = 80-pin PQFP, BG80 = 80-pin uBGA
Device Number Device Family
515-013e.eps
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115
Sales and Technical Support Contact Information
For the latest contact and support information on IP devices, please visit the Ubicom Web site at www.ubicom.com. The site contains technical literature, local sales contacts, tech support, and many other features. The Products are not authorized for use in life support systems or under conditions where failure of the Product would endanger the life or safety of the user, except when prior written approval is obtained from Ubicom, Inc. Ask your sales representive for details.
635 Clyde Avenue Mountain View, CA 94043 Tel: 650.210.1500 Fax: 650.210.8715 Email: sales@ubicom.com Web: www.ubicom.com
Ubicom, Inc. develops and markets wireless network processor and software platforms that enable all electronic devices to be connected to each other - securely, cost-effectively and transparently. With headquarters in Mountain View, California, Ubicom also has offices in Southern California as well as Belgium, Taiwan and Hong Kong. For more information, visit www.ubicom.com. Copyright (c) 2003 Ubicom, Inc. All rights reserved. Ubicom, IP2012, IP2022, and ipModule are trademarks of Ubicom, Inc. All other trademarks are the property of their respective holders. IP2K-DDS-2000-17 (3/17/2003)

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