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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33395/D Rev 2.0, 01/2004
Advance Information Three-Phase Gate Driver IC
The 33395 simplifies the design of high-power BLDC motor control design by combining the gate drive, charge pump, current sense, and protection circuitry necessary to drive a three-phase bridge configuration of six N-channel power MOSFETs. Mode logic is incorporated to route a pulse width modulation (PWM) signal to either the low-side MOSFETs or high-side MOSFETs of the bridge, or to provide complementary PWM outputs to both the low- and high-sides of the bridge.
33395 33395T
THREE-PHASE GATE DRIVER IC
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Detection and drive circuitry are also incorporated to control a reverse battery protection high-side MOSFET switch. PWM frequencies up to 28 kHz are possible. Built-in protection circuitry prevents damage to the MOSFET bridge as well as the drive IC and includes overvoltage shutdown, overtemperature shutdown, overcurrent shutdown, and undervoltage shutdown. The device is parametrically specified over an ambient temperature range of -40C TA 125C and 5.5 V VIGN 24 V supply. Features * Drives Six N-Channel Low RDS(ON) Power MOSFETs * Built-In Charge Pump Circuitry * Built-In Current Sense Comparator and Output Drive Current Limiting * Built-In PWM Mode Control Logic * Built-In Circuit Protection * Designed for Fractional to Integral HP BLDC Motors * 32-Terminal SOIC Wide Body Surface Mount Package * 33395 Incorporates a <5.0 s Shoot-Through Suppression Timer * 33395T Incorporates a <1.0 s Shoot-Through Suppression Timer
DWB SUFFIX CASE 1324-02 32-TERMINAL SOICW
ORDERING INFORMATION
Device MC33395DWB/R2 MC33395TDWB/R2 Temperature Range (TA) -40C to 125C Package
32 SOICW
33395 Simplified Application Diagram
VPWR
33395
VDD VGDH VIGN VDD CP1H CP1L CP2H CP2L CRES 3 2 3 VIGNP GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 N S N
H
S
H
H
MCU
HSE1-3 MODE0-1 GDL1 GDL2 PWM LSE1-3 GDL3 -ISENS AGND PGND +ISENS
VDD
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004
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VIGN VDD Low Low Voltage Reset Reset +ISENS Osc. Charge Charge Pump CP1H CP1L CP2H CP2L CPRES + Drive Limiting Drive Limiting L MODE0 MODE1 PWM HSE1 HSE2 HSE3 LSE1 LSE2 LSE3 AGND TEST PGND Overtemperature Shutdown Shutdown Control Control Logic Logic H VGDH VIGNP Gate Drive Gate Circuits Drive Circuits GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 GDL1 GDL2 GDL3
Overvoltage Overvoltage Shutdown
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-ISENS
Figure 1. 33395 Simplified Internal Block Diagram
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CP2H CPRES VIGN VGDH VIGNP SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CP2L CP1H CP1L LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD AGND +ISENS -ISENS
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TERMINAL FUNCTION DESCRIPTION
Terminal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Terminal Name CP2H CPRES VIGN VGDH VIGNP SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND Test -ISENS +ISENS AGND VDD PWM MODE1 MODE0 HSE3 Formal Name Charge Pump Cap Charge Pump Reserve Cap Input Voltage High-Side Gate Voltage Input Voltage Protected High-Side Sense Gate Drive High Output for Gate High-Side Sense Gate Drive High Output for Gate High-Side Sense Gate Drive High Gate Drive Low Power Ground Test Terminal IS Minus IS Plus Analog Ground Logic Supply Voltage Pulse Width Modulator Mode Control Bit 1 Mode Control Bit 0 High-Side Enable Definition High potential terminal connection for secondary charge pump capacitor Input from external reservoir capacitor for charge pump Input from ignition level supply voltage for power functions Output full-time gate drive for auxiliary high-side power MOSFET switch Input from protected ignition level supply for power functions Sense for high-side source voltage, phase 1 Output for gate high-side, phase 1 Output for gate drive low-side, phase 1 Sense for high-side source voltage, phase 2 Output for gate high-side, phase 2 Output for gate drive low-side, phase 2 Sense for high-side source voltage, phase 3 Output for gate drive high-side, phase 3 Output for gate drive low-side, phase 3 Ground terminals for power functions This should be connected to ground or left open Inverting input for current limit comparator Non-inverting input for current limit comparator Ground terminal for logic functions Supply voltage for logic functions Input for pulse width modulated driver duty cycle Input for mode control selection Input for mode control selection Input for high-side enable logic, phase 3
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal 25 26 27 28 29 30 31 32 Terminal Name HSE2 HSE1 LSE3 LSE2 LSE1 CP1L CP1H CP2L Formal Name High-Side Enable High-Side Enable Low-Side Enable Low-Side Enable Low-Side Enable External Pump Capacitor External Pump Capacitor Charge Pump Capacitor Definition Input for high-side enable logic, phase 2 Input for high-side enable logic, phase 1 Input for low-side enable logic, phase 3 Input for low-side enable logic, phase 2 Input for low-side enable logic, phase 1 Input from external pump capacitor for charge pump and secondary terminals Input from external pump capacitor for charge pump and secondary terminals Input from external reservoir, external pump capacitors for charge pump, and secondary terminals
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted
Rating VIGN Supply Voltage VIGNP Load Dump Survival VDD Logic Supply Voltage (Fail Safe) Logic Input Voltage (LSEn, HSEn, PWM, and MODEn) Start Up Current VIGNP ESD Voltage Human Body Model (Note 1) VESD1 VESD2 TSTG TA TC TJ PD TSOLDER RJA 500 200 -65 to 160 -40 to 125 -40 to 125 150 1.5 240 65 C C C C W C C/W V Symbol VIGN
IGNPLD
Value -15.5 to 40 -0.3 to 65 -0.3 to 7.0 0.3 to 7.0 100
Unit VDC VDC VDC VDC mA V
VDD VIN IVIGNStartUp
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Machine Model (Note 2) Storage Temperature Operating Ambient Temperature Operating Case Temperature Maximum Junction Temperature Power Dissipation (TA = 25C) Terminal Soldering Temperature Thermal Resistance, Junction-to-Ambient
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 2. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ).
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
VIGN Current @ 5.5 V-24 V, VDD = 5.5 V VIGNP Current @ 5.5 V-24 V, VDD = 5.5 V VIGNP Overvoltage Shutdown VIGNP Voltage VDD Current @ 5.5 VDC, 5.5 V VIGNP 24 V V IIGN IIGNP
IGNPSD
- - 25 5.5 - 2.5 7.0
0.2 - 33 - 1.8 3.2 -
1.0 100 36.5 24 4.0 4.0 -
mA mA V V mA V V
VIGNP IV
DD
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VDD Low-Voltage Reset Level VDD One-Time Fuse (Logic Supply)
VDD(RESET) -
INPUT/OUTPUT
Input Current at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn = 3.0 V Input Threshold at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn (Note 3) VSCRn Source Sense Voltage SRC1, SRC2, SRC3 Comparator Input Offset Voltage Comparator Input Bias Current Comparator Input Offset Current Common Mode Voltage (Note 4) Comparator Differential Input Voltage (Note 4) Charge Pump Voltage VIGN (Note 5) VIGNP = 5.5 V, ICRES = 1.0 mA VIGNP = 9.0 V, ICRES = 1.0 mA VIGNP = 12 V, ICRES = 5.0 mA VIGNP = 24 V, ICRES = 1.0 mA VIGNP = 24 V, ICRES = 5.0 mA VGDH Output Voltage with GDHn in ON State VIGNP = 5.5 V, IGDHn = 1.0 mA VIGNP = 12 V, IGDHn = 5.0 mA VIGNP = 24 V, IGDHn = 5.0 mA VGDH Output Voltage with GDHn in OFF State VIGNP = SRCn = 14 V, IGDHn = 1.0 mA VGDHn(off) -1.0 0.6 1.0 VGDHn(on) -V SRCn 4.0 4.0 4.5 5.2 9.0 11 18 18 18 V VINP(OFFSET) VINP(BIAS) IINP(OFFSET) VCMR VINPdiff VCRES -VIGNP 4.0 4.0 4.5 8.0 4.5 6.0 7.5 10 16 12 18 18 18 18 18 V VSCRn -0.3 5.0 -500 -300 0 -VDD VIGNP 14 -170 -3.0 - - 24 20 500 300 VDD -2.0 +VDD mV nA nA VDC V V VTH 1.0 2.0 3.0 V IIN 5.0 12 25 V A
Notes 3. Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 A internal sinks. 4. Guaranteed by design and characterization. Not production tested. 5. The Charge Pump has a positive temperature coefficient. Therefore the Min's occur at -40C, Typ's at 25C, and Max's at 125C.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
INPUT/OUTPUT (continued)
VGDL Low-Side Output Voltage GDHn in ON State VIGNP = 5.5 V, IGDLn = 1.0 mA VIGNP = 12 V, IGDLn = 5.0 mA VIGNP = 24 V, IGDLn = 0.0 mA VIGNP = 24 V, IGDLn = 5.0 mA VGDL Output Voltage GDHn in OFF State VGDL(off) -1.0 TLIM 160 0.3 - 1.0 190 VGDL(on) 5.0 8.0 8.0 8.0 8.0 14 17 16 18 18 19 19 V V
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VIGNP = 14 V, IGDLn = 1.0 mA Thermal Shutdown (Note 6)
C
Notes 6. Guaranteed by design and characterization. Not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time (25% to 75%), CISS Value = 2000 pF (Note 7) High-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time (75% to 25%), CISS Value = 2000 pF (Note 7) Shoot-Through Suppression Time Delay (33395) (Note 7), (Note 8) 33395 33395T Symbol t RH t FH - t D1, t D2 1.0 0.2 t ILIMDELAY 1.5 3.0 0.65 2.8 5.5 1.0 5.0 s 0.25 1.5 s Min - Typ 0.35 Max 1.5 s Unit s
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Current Limit Time Delay (Note 9)
Notes 7. See Figure 2, page 9. 8. Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being on simultaneously. 9. Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOW and sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay.
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Timing Diagram
GDHn SRCn (%)
100 75 25 0 tD1
tRH tFH
tD2
tRL
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GDLn, Gate V (%)
100 75 25 0
tFL
TIME
Figure 2. Shoot-Through Suppression
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SYSTEM /APPLICATION INFORMATION
INTRODUCTION
The 33395 and 33395T devices are designed to provide the necessary drive and control signal buffering and amplification to enable a DSP or MCU to control a three-phase array of power MOSFETs such as would be required to energize the windings of powerful brushless DC (BLDC) motors. It contains built-in charge pump circuitry so that the MOSFET array may consist entirely of N-Channel MOSFETs. It also contains feedback sensing circuitry and control circuitry to provide a robust overall motor control design.
FUNCTIONAL DESCRIPTION Gate Drive Circuits
By averaging these two values, the proper CPn value can be determined:
0.15 F 20 = 0.075 F, lower limit; and 0.15 F 10 = .015 F, upper limit
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The gate drive outputs (GDH1, GDH2, etc.) supply the peak currents required to turn ON and hold ON the MOSFETs, as well as turn OFF and hold OFF the MOSFETs.
Charge Pump
The current capability of the charge pump is sufficient to supply the gate drive circuit's demands when PWM'ing at up to 28 kHz. Two external charge pump capacitors and a reservoir capacitor are required to complete the charge pump's circuitry. Charge reservoir capacitance is a function of the total MOSFET gate charge (QG) gate drive voltage level relative to the source (VGS) and the allowable sag of the drive level during the turn-on interval (VSAG). CRES can be expressed by the following formula: CRES = QG x VGS 2 x VGS x VSAG - VSAG2 CP1 and CP2 =(0.0075 F + 0.015 F) / 2 = 0.01 F
Thermal Shutdown Function
The device has internal temperature sensing circuitry which activates a protective shutdown function should the die reach excessively elevated temperatures. This function effectively limits power dissipation and thus protects the device.
Overvoltage Shutdown Function
When the supply voltage (VIGN) exceeds the specified overvoltage shutdown level, the part will automatically shut down to protect both internal circuits as well as the load. Operation will resume upon return of VIGN to normal operating levels.
For example, for QG = 60 nC, VGS = 14 V, VSAG = 0.2 V: (60 nC) x (14 V) CRES = = 0.15 F 2 x (14 V) x (0.2 V) - (0.2)2 Proper charge pump capacitance is required to maintain, and provide for, adequate gate drive during high demand turnON intervals. Use the following formula to determine values for CP1 and CP2: For example, for the above determination of CRES = 0.15 F: CRES 20 < CP1 = CP2 < CRES 10
Low Voltage Reset Function
When the logic supply voltage (VDD) drops below the minimum voltage level or when the part is initially powered up, this function will turn OFF and hold OFF the external MOSFETs until the voltage increases above the minimum voltage level required for normal operation.
Control Logic
The control logic block controls when the low-side and highside drivers are enabled. The logic implements the Truth Table found in the specification and monitors the M0, M1, PWM, CL, OT, OV, LSE, and HSE terminals. Note that the drivers are enabled 3 s after the PWM edge. During complimentary chop mode the high-side and low-side drives are alternatively enabled and disabled during the PWM cycle. To prevent shootthrough current, the high-side drive turn-on is delayed by tD1, and the low-side drive turn on is delayed by tD2 (see Figure 2, page 9).
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Note that the drivers are disabled during an overtemperature or overvoltage fault. A flip-flop keeps the drive off until the following PWM cycle. This prevents erratic operation during fault conditions. The current limit circuit also uses a flip-flop for latching the drive off until the following PWM cycle. Note PWM must be toggled after POR, Thermal Limit, or overvoltage faults to re-enable the gate drivers.
sense resistor placed in series with the ground return of the three-phase output bridge. When triggered by the comparator, the CL (current limit) bit of the internal error register is set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 1, Truth Table, page 12).
VGDH
The VGDH terminal is used to provide a gate drive signal to a reverse battery protection MOSFET. If reverse battery protection is desired, VIGN would be applied to the source of an external MOSFET, and the drain of the MOSFET would then deliver a "protected" supply voltage (VIGNP) to the three phase array of external MOSFETs as well as the supply voltage to the VIGNP terminal of the IC. In a reverse polarity event (e.g., an erroneous installation of the system battery), the VGDH signal will not be supplied to the external protection MOSFET, and the MOSFET will remain off and thus prevent reverse polarity from being applied to the load and the VIGNP supply terminal of the IC.
Overtemperature and Overvoltage Shutdown Circuits
Internal monitoring is provided for both over temperature conditions and over voltage conditions. When any of these conditions presents itself to the IC, the corresponding internally set bits of the error register are set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 1).
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LSE and HSE Input Circuits
The low-side enable input terminals (LSE1, LSE2, LSE3) and high-side enable input terminals (HSE1, HSE2, HSE3) form the input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and LSE3) which set the logic states of the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3) in accordance with the logic set forth in the Truth Table (page 12). Typically these inputs are supplied from an MCU or DSP to provide the phasing of the currents applied to a brushless dc motor's stator coils via the output MOSFET pairs.
High-Side Gate Drive Circuits
Outputs GDH1, GDH2, and GDH3 provide the elevated drive voltage to the high-side external MOSFETs (HS1, HS2, and HS3; see Figure 3, page 13). These gate drive outputs supply the peak currents required to turn ON and hold ON the highside MOSFETs, as well as turn OFF the MOSFETs. These gate drive circuits are powered from an internal charge pump, and therefore compensate for voltage dropped across the load that is reflected to the source-gate circuits of the high-side MOSFETs.
PWM Input
The pulse width modulation input provides a single input terminal to accomplish PWM modulation of the output pairs in accordance with the states of the Mode 0 and Mode 1 inputs as set forth in the Truth Table (page 12).
Low-Side Gate Drive Circuits
Outputs GDL1, GDL2, and GDL3 provide the drive voltage to the low-side external MOSFETs (LS1, LS2, and LS3; see Figure 3). These gate drive outputs supply the peak currents required to turn ON and hold ON the low-side MOSFETs, as well as turn OFF the MOSFETs.
Mode Selection Inputs
The mode selection inputs (Mode 0 and Mode 1) determine the PWM implementation of the output pairs in accordance with the logic set forth in the Truth Table (page 12). PWM'ing can thus be set to occur either on the high-side MOSFETs or the low-side MOSFETs, or can be set to occur on both the high-side and low-side MOSFETs as "complementary chopping".
VDD Fuse
The VDD supply of the 33395 IC has an internal fuse, which will blow and set all outputs of the device to OFF, if the VDD voltage exceeds that stated in the maximum rating section of the data sheet. When this fuse blows, the device is permanently disabled.
Test Terminal
This terminal should be grounded or left floating (i.e., do not connect it to the printed circuit board). It is used by the automated test equipment to verify proper operation of the internal overtemperature shut down circuitry. This terminal is susceptible to latch-up and therefore may cause erroneous operation or device failure if connected to external circuitry.
ISENS Inputs
The +Isens and -Isens terminals are inputs to the internal current sense comparator. In a typical application, these would receive a a low-pass filtered voltage derived from a current
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Table 1. Truth Table The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn (n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT), overvoltage (OV), and current limit (CL) bits provided in this table.
NORMAL OPERATION Switching Modes MODE1 0 0 0 0 0 MODE0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Internally Set Bits OT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Input Pairs (e.g., LSE2 and HSE2) LSEn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HSEn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Pairs (e.g., GDL2 and GDH2) GDLn 0 0 PWM 0 0 0 PWM 0 0 0 1 0 0 PWM 1 0 GDHn 0 1 0 0 0 1 PWM 0 0 PWM 0 0 0 PWM 0 0
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0 0 0 1 1 1 1 1 1 1 1
FAULT MODE OPERATION Switching Modes MODE1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x x MODE0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x x Internally Set Bits OT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 OV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x CL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x Input Pairs (e.g., LSE2 and HSE2) LSEn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x x HSEn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x Output Pairs (e.g., GDL2 and GDH2) GDLn 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 GDHn 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
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+
12 V
HS1
HS2
HS3
+ -
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SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST
LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD AGND +ISENS -ISENS
MCU
5.0 V +
LS1
LS2
LS3
Figure 3. Typical Application Diagram
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RSENSE
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TO MOTOR
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CP2H CPRES VIGN VGDH VIGNP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CP2L CP1H CP1L
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PACKAGE DIMENSIONS
DWB SUFFIX 32-TERMINAL SOICW PLASTIC PACKAGE CASE 1324-02 ISSUE A
NOTES: 1. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
10.3 7.6 7.4 C 5
1 32
3.
4.
B 9
2.65 2.35
30X
5.
0.65
6.
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PIN 1 ID 4 B B 9 11.1 10.9 C L
7. 8.
9.
16
17
5.15
2X 16 TIPS
A
32X
SEATING PLANE
0.3
A
BC A (0.29)
BASE METAL
0.10 A
A
0.25 0.19 0.38 0.22
M
(0.203)
R0.08 MIN 0.25
GAUGE PLANE MIN
0
6 0.13
PLATING
0.29 0.13
CA
M
B
8 8 0 0.9 0.5 SECTION B-B
ROTATED 90 CLOCKWISE
SECTION A-A
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NOTES
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MC33395/D

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