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ACT5260PC-P10-POD FR4 Adapter
The Aeroflex ACT5260PC-P10-POD adapts a QED RM5260 MIPS microprocessor to an R4400PC, R4600 or R4700 processor's 179 pin PGA footprint. This product allows the evaluation of the latest MIPS IV 5XXX series performance in existing 4XXX series hardware. Some of the performance enhancements include:
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Allows potentially higher pipeline clock rates due to it multiplication of the input clock by 2,3,4,5,6,7 or 8 compared to the 4XXX series method of multiplying the input clock by only 2, then dividing it down by 2,3,4 etc for output system clock. The RM5260 is a 3.3 volt device with 5 volt tolerant I/O's. It has a fully operational IEEE 1149.1 JTAG boundary scan interface. On-board supply de-coupling capacitors and PLL filter network.
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ACT5260 DESCRIPTION:
The ACT5260 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5260 can issue both an integer and a floating point instruction in the same cycle. The ACT5260 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.
Integer Unit
Like the R5000, the ACT5260 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5260 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in a later section, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5260 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/ divide operations, and the program counter(PC).
HARDWARE OVERVIEW
The ACT5260 offers a high-level of integration targeted at high-performance embedded applications. Some of the key elements of the ACT5260 are briefly described below.
Register File
The ACT5260 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.
Superscalar Dispatch
The ACT5260 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5260 provides unparalleled price/performance in computationally intensive embedded applications.
ALU
The ACT5260 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle
CPU Registers
Like all MIPS ISA processors, the ACT5260 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. For Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMarkTM RM5260TM, 64-Bit Superscalar Microprocessor see the QED datasheet.
Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the ACT5260 uses the simple 5-stage pipeline also found in the circuits R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5260 uses an extended seven stage pipeline for floating-point operations. Like the R5000, the ACT5260 does virtual to physical translation in parallel with cache access.
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Application Considerations:
Although the device has a 4XXX PC 179 pin PGA compatible footprint, it is not a drop-in replacement since the RM5260 has a different clocking scheme. The RM5260 does not generate the system clocks the same as the R4400, R4600 and R4700. Instead, the system clock is an input, which is multiplied up to the pipeline rate. On the adapter, the Tclock and Rclock pins are floating; not connected to anything. SYNCout and IOout are connected to ground to commit possible unconnected CMOS inputs to a level. Depending on the system configuration, accommodating the clocking difference can be as simple as a few re-routing jumpers or generating divisors of the original MasterClock and the addition of some phase-skewing buffers to emulate the Rclock and Tclock system clocks. In addition, the boot time mode bit serial stream needs to be scrutinized before plugging in a RM5260 into an R4700 or R4400 socket. The R4700 is closest to the RM5260 whereas the R4400 is quite different. Figure 2 is an example of what had to be done to an Algorithmics P4000i (IDT79S460) Single Board Computer which was originally configured for an R4700 with a 50 MHz input clock (100 MHz pipeline) and a divide by 2 output clock (50 MHz bus rate). With three wire jumpers, the ACT5260PC-P10-POD was up and running with no changes to the boot and monitor PROM or any recompilation of application programs. In this case, the R4700's modebit stream happened to be compatible, where a board jumper used to change the output clocks (Tclock and Rclock) from divide by 2 to divide by 3 had the effect of changing the Pclock multiplier from 2 to 3, upping the pipeline rate up to 150 Mhz without changing the board oscillator.
R4700
MASTER CLOCK
ACT5260PC
SysClk
RCLK
TCLK
RCLK
Oscillator
50MHz
Oscillator
50MHz
From Figure 2 - Setup Example
To
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TCLK
Boot Time Mode Stream Comparison Chart - 5260 vs 4700
5260 Mode Bit 0 4..1 Description Reserved (must be zero) Write-back data rate 0 DDDD 1 DDxDDx 2 DDxxDDxx 3 DxDxDxDx 4 DDxxxDDxxx 5 DDxxxxDDxxxx 6 DxxDxxDxxDxx 7 DDxxxxxxDDxxxxxx 8 DxxxDxxxDxxxDxxx 9-15 reserved Pclock to SysClock Multiplier 0 Multiply by 2, 1 Multiply by 3 2 Multiply by 4, 3 Multiply by 5 4 Multiply by 6, 5 Multiply by 7 6 Multiply by 8, 7 reserved Specifies byte ordering. Logically ORed with BigEndian input signal. 0 Little endian 1 Big endian 00 R4000 compatible non-block writes, 01 reserved, 10 pipelined non-block writes, 11 non-block write re-issue 0 Enable the timer interrupt on Int[5], 1 Disable the timer interrupt on Int[5]. Reserved: Must be zero (0) Output driver strength 10 100% strength (fastest), 11 83% strength, 00 67% strength, 01 50% strength (slowest) Reserved: Must be zero (0) System configuration identifiers - software visible in processor Config[21..20] Mode Bit 0 4..1 4700 Description Reserved: Must be zero (0) Write-back data rate 0D 1 DDx 2 DDxx 3 DxDx 4 DDxxx 5 DDxxxx 6 DxxDxx 7 DDxxxxxx 8 DxxxDxxx 9-15 reserved Clock divisor 0 2,1 3 2 4, 3 5 4 6, 5 7 6 8, 7 reserved 0 Little endian 1 Big endian
7..5
7..5
8
8
10..9
10..9
00 R4000 compatible, 01 reserved, 10 pipelined writes, 11 write re-issue 0 Enable the timer interrupt on Int[5], 1 Disable the timer interrupt on Int[5]. Reserved: Must be zero (0) Output driver strength 10 100% strength (fastest), 11 83% strength, 00 67% strength, 01 50% strength (slowest) 0 TClock[0] enabled, 1 TClock[0] disabled 0 TClock[1] enabled, 1 TClock[1] disabled 0 RClock[0] enabled, 1 RClock[0] disabled 0 RClock[1] enabled, 1 RClock[1] disabled Reserved: Must be zero (0)
11 12 14..13
11 12 14..13
15 17..16
15 16 17
18 21..19 24..22 255..25
0 Set Timer/Counter to run at Pclock/2 1 Set Timer/Counter to run at Pclock Reserved: Must be zero (0) Write address to write data delay in P cycles 000 0 cycles(R5000), ..., 111 7 cycles Reserved: Must be zero (0)
18 255..19
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SysClock
tDO tDO
MIN
Data
Data
Data
Figure 3 - Output Timing
SysClock
tDS tDH
Data
Data
Figure 4 - Input Timing
SysClock
tSCRise tSCFall tSCP tJitterIn
Figure 5 - SysClock Timing
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Absolute Maximum Ratings1
Symbol VTERM TCASE TBIAS TSTG IIN IOUT Rating Terminal Voltage with respect to GND Operating Temperature Case Temperature under Bias Storage Temperature DC Input Current DC Output Current Range -0.5 to 4.6 0 to +85 -55 to +125 -55 to +125 203 50
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Units V C C C mA mA
Notes: 1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts. 3. When VIN < 0V or VIN > Vcc. 4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
Recommended Operating Conditions
Symbol VCC VIH VIL TC Parameter Power Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Case (Commercial) Minimum +3.135 0.7VCC -0.5 0 Maximum +3.465 VCC + 0.5 0.2VCC +85 Units V V V C
DC Characteristics
(VCC = 3.3V 5%; TCASE = 0C to +85C) Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Input High Voltage Input Low Voltage Input Current Input Current Input Current Input Capacitance Output Capacitance Sym VOL1 VOH1 VOL2 VOH2 VIH VIL IIN1 IIN2 IIN3 CIN COUT VIN = 0V VIN = VCC VIN = 5.5V IOL = 20 A IOL = 20 A IOL = 4 mA IOL = 4 mA 2.4 0.7VCC -0.5 -20 -20 -250 VCC + 0.5 0.2VCC +20 +20 +250 10 10 Vcc - 0.1 0.4 Conditions 133 / 150MHz Min Max 0.1 Units V V V V V V A A A pF pF
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Power Consumption
Parameter Active Operating Supply Current Symbol ICC1 ICC2 ICC3 Standby Current ISB1 ISB1 Conditions CL = 0pF, 150/75MHz, No SysAD activity CL = 50pF, 150/75MHz, R4000 write protocol without FPU operation CL = 50pF, 150/75MHz, write re-issue or pipelined writes CL = 0pF, 150/75MHz CL = 50pF, 150/75MHz 133MHz, 3.3V Typ
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150MHz, 3.3V Typ5 TBD 1150 1250 Max TBD 1950 2250 TBD TBD
Max TBD 1750 2000 TBD TBD
Units mA mA mA mA mA
TBD 1000 1100
Notes: 5. Typical integer instruction mix and cache miss rates.
AC Characteristics
(VCC = 3.3V 5%; TCASE = 0C to +85C)
Capacitive Load Deration
133 / 150MHz Symbol CLD Load Derate Parameter Minimum Maximum 2 ns/25pF Units
Clock Parameters
133/150MHz Parameter SysClock High SysClock Low SysClock Frequency6 SysClock Period Clock Jitter for SysClock SysClock Rise Time SysClock Fall Time ModeClock Period JTA Clock Period tSCP tJitterIn tSCRise tSCFall tModeCKP tJTAGCKP Symbol tSCHigh tSCLow Transition < 5ns Transition < 5ns Test Conditions Min 4 4 33 75 30 250 5 5 256*tSCP 4*tSCP Max ns ns MHz ns ps ns ns ns ns Units
Notes: 6. Operation of the ACT5260 is only guaranteed with the Phase Loop enabled.
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System Interface Parameters7
133MHz Parameter Data Output8 tDO mode14...13 = 00 mode14...13 = 01 (slowest) Data Setup Data Hold tDS tDH tRISE = 5ns tFALL= 5ns Symbol Test Conditions Min mode14...13 = 10 (fastest) mode14...13 = 11 TBD TBD 1.0 TBD 4.0 0 Max TBD TBD 8.0 TBD Min TBD TBD 1.0 TBD 4.0 0 Max TBD TBD 8.0 TBD ns ns ns ns ns ns 150MHz Units
Notes: 7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal. 8. Capacitive load for all output timing is 50pF.
Boot Time Interface Parameters
133/150MHz Parameter Mode Data Setup Mode Data Hold Symbol tDS tDH Test Conditions Min 4 0 Max SysClock cycles SysClock cycles Units
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ACT5260PC Adapter Pinouts
4XXX Signal
INT0 INT1 INT2 INT3 INT4 INT5 IOIN IOOUT JTCK JTDI JTDO JTMS MODECLK MODEIN MSTRCLK MSTROUT RCLK0 RCLK1 SYNCIN SYNCOUT SYSAD0 SYSAD1 SYSAD10 SYSAD11 SYSAD12 SYSAD13 SYSAD14 SYSAD15 SYSAD16 SYSAD17 SYSAD18 SYSAD19 SYSAD2 SYSAD20 SYSAD21 SYSAD22 SYSAD23 SYSAD24 SYSAD25 SYSAD26 SYSAD27 SYSAD28 SYSAD29 SYSAD3 SYSAD30 SYSAD31 SYSAD32 SYSAD33 SYSAD34 SYSAD35 SYSAD36 SYSAD37 SYSAD38 SYSAD39 SYSAD4 SYSAD40 SYSAD41 SYSAD42 SYSAD43 SYSAD44
PGA Pin
N2 L3 K3 J3 H3 F2 T13 U12 H17 G16 F16 E16 B4 U4 J17 P17 T17 R16 J16 P16 J2 G2 C12 B14 B15 C16 D17 E18 K2 M2 P1 P3 E1 T2 T4 U5 U6 U9 U11 T12 U14 U15 T16 E3 R17 M16 H2 G3 F3 D2 C3 B3 C6 C7 C2 C10 C11 B13 A15 C15
5260 Pin
93 94 95 96 97 98 NC GND 49 48 47 50 46 58 661 NC NC NC NC GND 189 193 26 28 32 36 38 42 114 118 120 124 197 128 130 134 138 140 144 148 150 163 165 199 169 173 190 194 198 200 7 9 13 17 6 19 23 27 29 33
4XXX Signal
SYSAD45 SYSAD46 SYSAD47 SYSAD48 SYSAD49 SYSAD5 SYSAD50 SYSAD51 SYSAD52 SYSAD53 SYSAD54 SYSAD55 SYSAD56 SYSAD57 SYSAD58 SYSAD59 SYSAD6 SYSAD60 SYSAD61 SYSAD62 SYSAD63 SYSAD7 SYSAD8 SYSAD9 SYSADC0 SYSADC1 SYSADC2 SYSADC3 SYSADC4 SYSADC5 SYSADC6 SYSADC7 SYSCMD0 SYSCMD1 SYSCMD2 SYSCMD3 SYSCMD4 SYSCMD5 SYSCMD6 SYSCMD7 SYSCMD8 SYSCMDP TCLK0 TCLK1 VCCOK CLDRST EXTRQST FAULT NMI RDRDY RELEASE RESET VALIDOUT VALIDIN WRRDY VCC VCC NC VCC VCC
PGA Pin
B17 E17 F17 L2 M3 C4 N3 R2 T3 U3 T6 T7 T10 T11 U13 V15 B5 T15 U17 N16 N17 B6 B9 B11 C8 G17 T8 L16 B8 H16 U8 L17 E2 D3 B2 A5 B7 C9 B10 B12 C13 C14 C17 D16 M17 T14 U2 B16 U7 T5 V5 U16 R3 P2 C5 A2 A4 A7 A9 A11
5260 Pin
37 39 43 115 119 8 121 125 129 131 135 139 141 145 149 151 12 164 166 170 174 16 18 22 183 187 175 179 184 188 176 180 73 74 75 76 79 80 83 84 85 86 NC NC 110 109 107 NC 106 59 63 108 62 61 60 VCC VCC NC VCC VCC
4XXX Signal
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSSP GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC
PGA Pin
A13 A16 B18 C1 D18 F1 G18 H1 J18 K1 K17 L18 M1 N18 R1 T18 U1 V3 V6 V8 V10 V12 V14 V17 T9 A3 A6 A8 A10 A12 A14 A17 A18 B1 C18 D1 F18 G1 H18 J1 K16 K18 L1 M18 N1 P18 R18 T1 U18 V1 V2 V4 V7 V9 V11 V13 V16 V18 U10
5260 Pin
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 64 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 65 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1112 NC
Notes: 1. 5260 pin function SysClk 2. 5260 pin function BigEndian
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C II R C U II T T E C H N O L O G Y C RCU T TECHNOLOGY
Ordering Information
Model Number ACT5260PC-P10-POD
Package Outline
Bottom View
1 V U T R P N M L K J H G F E D C B A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Side View
.180 .100 BSC
1.700 1.840 BSC 1.880
.018
1.700 BSC 1.840 1.880
.050 .375 MAX
Specification subject to change without notice
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