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| SigmaDSP(R) Multichannel Audio Processor with Embedded 2ADC/8DAC Codec ADAV400 FEATURES Fully programmable audio digital signal processing (DSP) for enhanced sound processing Features SigmaStudioTM, a proprietary graphical programming tool for fast development of custom signal flows Easy implementation of third party audio algorithms Scalable digital audio delay line Pool of 400 ms (for example, 200 ms for stereo channel) High performance integrated analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) 1 stereo analog input (ADC) 4 stereo analog inputs with mux to stereo ADC 4 stereo (8-channel) analog outputs (DACs) Dedicated headphone output with integrated amplifier Multichannel digital I/O 8-channel I2S input and output modes 8- and 16-channel TDM input and output modes 2-channel (1 stereo) asynchronous I2S input with integrated sample rate converter (SRC), supporting sample rates from 5 kHz to 50 kHz I2C(R) control interface Operates from 3.3 V (analog), 1.8 V (digital core), 3.3 V (digital interface) Features on-chip regulator for single 3.3 V operation 80-lead LQFP package (14 mm x 14 mm) Temperature range: 0C to +70C APPLICATIONS Advanced TV (ATV) audio processing Custom Audio Flows Sound Enhancement 3rd Party Audio Algorithms DVD Receiver and HTiB Virtualiser for 2.0 or 2.1 systems Post Processing FUNCTIONAL BLOCK DIAGRAM ADAU1421 ADAV400 MULTI-CHANNEL DIGITAL OUTPUTS SDO0 SDO1 SDO2 SDO3 LRCLK1 BCLK1 I2C INTERFACE PROGRAMMABLE AUDIO PROCESSOR CORE VOUT1 DAC VOUT2 VOUT3 DAC VOUT4 HPOUTL SDIN0 SDIN1 SDIN2 SDIN3 AINL1 AINR1 ADC AINL4 AINR4 SYNCHRONIZE MULTI-CHANNEL DIGITAL INPUT A-V SYNC DELAY MEMORY DAC HPOUTR AUXL1 AUXR1 AUXL2 DAC AUXR2 05621-001 MCLKI MCLKO SCL SDA AD0 BCLK0 LRCLK0 PLL SYSTEM CLOCKS SRC ASYNCHRONIZE DIGITAL INPUT Figure 1. Rev. PrG Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. ADAV400 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Digital Timing............................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 13 Analog Input Multiplexer.......................................................... 13 Sample Rate Converter Block ................................................... 13 PLL Block..................................................................................... 14 Analog Outputs........................................................................... 14 Headphone Amplifier ................................................................ 14 Voltage Regulator ....................................................................... 14 Signal Processing ............................................................................ 15 Numeric Formats........................................................................ 15 Programming.............................................................................. 15 Control Port .................................................................................... 16 I2C Port ........................................................................................ 16 RAMs and Registers....................................................................... 19 Control Port Addressing............................................................ 19 Parameter RAM Contents......................................................... 19 Recommended Program/Parameter Loading Procedures.... 20 Target/Slew RAM ....................................................................... 20 Safeload Registers....................................................................... 23 Data Capture Registers .............................................................. 23 Audio Core Control Register .................................................... 24 RAM Configuration Register ................................................... 25 Control Port Read/Write Data Formats .................................. 25 Serial Data Input/Output Ports .................................................... 27 Control Registers ............................................................................ 29 Serial Output Control Registers ............................................... 31 Serial Input Control Register .................................................... 31 Typical Application Diagram.................................................... 33 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY Preliminary Version Rev PrG Rev. PrG | Page 2 of 36 ADAV400 GENERAL DESCRIPTION The ADAV400 is an enhanced audio processor. Integrating high performance analog and digital I/O with a powerful audio specific programmable core enables designers to differentiate their products through audio performance. The audio processing core is based on Analog Devices SigmaDSP technology featuring full 28-bit processing (56-bit in double precision mode), a sophisticated, fully programmable, dynamics processor and delay memory. This technology allows the system designer to compensate for real world limitations of speakers, amplifiers, and listening environments. This compensation results in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression and limiting, and third party branded algorithms. The analog I/O integrates Analog Devices proprietary continuous time, multibit, sigma-delta (-) architecture. This integration brings a higher level of performance to systems that are required to meet system branding certification by third party algorithm providers. The analog inputs feature a 95 dB dynamic range ADC fed from a 4-stereo input mux. The main speaker outputs can be supplied as a voltage output from the integrated 95 dB dynamic range DAC channels. A dedicated headphone DAC with integrated amplifiers and additional auxiliary analog outputs is also available. The ADAV400 supports multichannel digital inputs and outputs. An integrated SRC on one channel provides the capability to support any input sample rates in the range from 5 kHz to 50 kHz, synchronizing this input to the internal DSP engine. The ADAV400 is supported by a powerful graphical programming tool that includes blocks such as general filters, EQ filters, dynamics processing, mixers, volume, and third party algorithms for fast development of custom signal flows. Rev. PrG | Page 3 of 36 ADAV400 SPECIFICATIONS AVDDn1 = 3.3 V, ODVDD = 3.3 V, DVDD = internal voltage regulator, temperature = 0C to +70C, master clock = 12.288 MHz, measurement bandwidth = 20 Hz to 20 kHz, ADC input signal = 1 kHz, DAC output signal = 1 kHz, unless otherwise noted. Table 1. Parameter REFERENCE SECTION Absolute Voltage VREF VREF Temperature Coefficient AUX ANALOG INPUTS (SINGLE-ENDED) Number of Channels Full-Scale Analog Input DC Offset ADC SECTION Resolution Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk Gain Error Power Supply Rejection ADC DIGITAL DECIMATOR FILTER CHARACTERISTICS @ 48 kHz Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC OUTPUTS (SINGLE-ENDED) Number of Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion + Noise2 Crosstalk Gain Error Interchannel Gain Mismatch DC Offset Power Supply Rejection DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS @ 48 kHz Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Min Typ 1.5 130 8 100 10 24 90 95 -93 0.1 -78 -6 -83 Max Units V ppm/C 4 stereo channels 2 V rms input with 20 k series resistor Relative to VREF Stereo ADC -60 dB with respect to full-scale analog input dB dB dB dB % dB -3 dB with respect to full-scale analog input Left and right channel gain mismatch Analog channel crosstalk (AINYm1 to AINYm1) One channel = -3 dB, other channel = 0 V 1 kHz, 300 mV p-p signal at AVDDn1 Test Conditions/Comments A rms mV Bits 22.5 0.0002 24 26.5 100 1040 8 24 1 90 95 -90 -100 5 0.1 1 -87 kHz dB kHz kHz dB s DAC amplifier register contents = 0x0010 4 stereo output channels Bits V rms -60 dB with respect to full-scale code input dB dB dB % dB mV dB -3 dB with respect to full-scale code input Analog channel crosstalk (VOUTm1 to VOUTm1) One channel = -3 dB, other channels = 0 V Left and right channel gain mismatch Relative to VREF 1 kHz, 300 mV p-p signal at AVDDn1 21.769 0.01 23.95 26.122 75 580 kHz dB kHz kHz dB s Rev.PrG | Page 4 of 36 ADAV400 Parameter HEADPHONE OUTPUT (SINGLE-ENDED) Number of Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion Plus Noise Gain Error Interchannel Gain Mismatch DC Offset Power Supply Rejection PLL SECTION3 Master Clock Input (MCLKI) SRC3 Dynamic Range A-Weighted Total Harmonic Distortion + Noise Sample Rate DIGITAL INPUT/OUTPUT Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = ODVDD) Input Leakage (IIL @ VIL = 0 V) Output Voltage HI (VOH @ IOH = 0.4 mA) Output Voltage LO (VOL @ IOL = -3.2 mA) Input Capacitance SUPPLIES Analog Supplies AVDDn1 Digital Supplies DVDD Interface Supply ODVDD Supply Current, Normal Mode Analog Current (AVDD1) Digital and Interface Current PLL Current Supply Current, Power-Down Mode Analog Current Digital and Interface Current PLL Current 1 2 Min Typ Max Units 2 24 1 92 -84 4 0.5 -200 -84 64 x fS 512 x fS Test Conditions/Comments Measured at headphone output with 32 load, headphone amplifier register contents = 0x0001 1 stereo channel Bits V rms -60 dBFS with respect to full-scale code input dB dB % dB mV dB MHz -60 dBFS input (worst-case input fS = 50 kHz) -3 dBFS with respect to full-scale code input Relative to VREF 1 kHz, 300 mV p-p signal at AVDDn1 115 -113 5 2.0 50 ODVDD 0.8 10 dB dB kHz V V A A V V pF V V V mA mA mA mA mA A 0 dBFS input (worst-case input fS = 50 kHz) -60 2.4 0.4 2 3.15 1.6 3.15 3.30 1.8 3.30 90 120 5 6 1.5 5 3.45 2.0 3.45 110 135 6 8.5 6 50 MCLK = 12.288 MHz, ADC and DACs active, headphone outputs active and driving a 32 load, Power control register = 0xFFFF RESET low, MCLK = 3.074 MHz, AINx = AGND, DAC and headphone outputs floating In this table, n refers to supply number, m refers to channel number, and Y refers to stereo channel identifier: L for left channel or R for right channel. Measured on one DAC with other DACs and ADCs off. 3 Guaranteed by design. Rev. PrG | Page 5 of 36 ADAV400 DIGITAL TIMING Table 2. Parameter MASTER CLOCK AND RESET fMCLKI (MCLKI Frequency) tMCH (MCLKI High) tMCL (MCLKI Low) tRLPW (RESET Low Pulse Width) I2C PORT fSCL (SCL Clock Frequency) tSCLH (SCL High) tSCLL (SCL Low) Start Condition tSCS (Setup Time) tSCH (Hold Time) tDS (Data Setup Time) tSCR (SCL Rise Time) tSCF (SCL Fall Time) tSDR (SDA Rise Time) tSDF (SDA Fall Time) STOP CONDITION tSCSH (Setup Time) SERIAL PORTS Slave Mode tSBH (BCLKx High) tSBL (BCLKx Low) fSBF (BCLKx Frequency) tSLS (LRCLKx Setup) tSLH (LRCLKx Hold) tSDS (SDINx Setup) tSDH (SDINx Hold) tSDD (SDOx Delay) Master Mode tMLD (LRCLKx Delay) tMDD (SDOx Delay) tMDS (SDINx Setup) tMDH (SDINx Hold) Min 3.024 10 10 20 Max 24.576 Unit MHz ns ns ns kHz s s s s ns ns ns ns ns s Relevant for repeated start condition The first clock is generated after this period Comments 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 40 40 64 x fS 10 10 10 10 40 5 40 10 10 ns ns ns ns ns ns ns ns ns ns ns To BCLK rising edge From BCLK rising edge To BCLK rising edge From BCLK rising edge From BCLK falling edge From BCLK falling edge From BCLK falling edge From BCLK rising edge From BCLK rising edge Rev.PrG | Page 6 of 36 ADAV400 Digital Timing Diagrams tSBH BCLKx tSBL tSLH LRCLKx tSLH tSDS SDINx LEFT-JUSTIFIED MODE MSB tSDH MSB-1 SDOx I2 S MODE MSB tMDO tSDO Figure 2. Serial Port Timing tSCH tSDR tDS tSCH tSDF SDA tSCR tSCLH tSCLL tSCF tSCS tSCSH Figure 3. I2C Port Timing tMP MCLK tRLPW Figure 4. Master Clock and Reset Timing Rev. PrG | Page 7 of 36 05621-004 RESET 05621-003 SCL 05621-002 ADAV400 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter DVDD to DGND ODVDD to DGND AVDD to AGND AGND to DGND Digital Inputs Analog Inputs Reference Voltage Soldering (10 sec) Rating 0 V to 2.2 V 0 V to 4.0 V 0 V to 4.0 V -0.3 V to +0.3 V DGND - 0.3 V to ODVDD + 0.3 V AGND - 0.3 V to ADVDD + 0.3 V Indefinite short-circuit to ground +300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev.PrG | Page 8 of 36 ADAV400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD5 AVDD4 AUXR2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FILTA 1 VREF 2 AGND 3 AVDD1 4 NC 5 NC 6 NC 7 NC 8 NC 9 NC 10 NC 11 NC 12 DGND 13 DVDD 14 AD0 15 SDA 16 SCL 17 TEST0 18 TEST1 19 DGND 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 VOUT4 60 59 58 57 56 AUXL2 TEST2 AINR4 AINR3 AINR2 AINR1 AGND AGND AINL4 AINL3 AINL2 AINL1 FILTD IDAC NC NC VOUT3 VOUT2 VOUT1 AUXR1 AUXL1 AVDD3 HPOUTR HPOUTL AGND AGND PLL_LF AVDD2 DGND DVDD RESET NC NC SDO3 SDO2 DGND ADAV400 TOP VIEW TOP VIEW (Not to Scale) 55 54 ADAU1421 53 52 51 50 49 48 47 46 45 44 43 42 41 (Not to Scale) VDRIVE SDO0 ODVDD SDIN0 SDIN1 SDIN2 SDIN3 SDO1 DVDD DVDD NC DGND DGND MCLKI MCLKO BCLK0 LRCLK0 BCLK1 LRCLK1 DVDD NC = NO CONNECT Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 to 12, 39, 44, 45, 65, 66 13, 20, 28, 32, 41, 48 14, 21, 31, 40, 47 15 16 17 18 19 22 to 25 Mnemonic FILTA VREF AGND AVDD1 NC I/O O Description ADC Filter Decoupling Node for the ADC. Decouple this pin with a 47 F capacitor and 0.1 F capacitor to AGND. Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin with a 47 F capacitor and 0.1 F capacitor to AGND. ADC Ground. Connect this pin to the analog ground plane. Analog Power Supply Pin. Connect this pin to +3.3 V and decouple it with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. Not Connected Internally. DGND Digital Ground. Connect this pin to the digital ground plane. DVDD Digital Power Supply Pins. Connect these pins to +1.8 V, either directly or by using the on-chip regulator. Decouple each pin with a 47 F capacitor and 0.1 F capacitor to DGND as close as possible to the pin. I I/0 I I2C Address Select. Tie to ODVDD or DGND. This pin selects the address for the communication of the ADAV400 with the control port. This allows two ADAV400s to be used with a single I2C port. Serial Data Input/Output for the I2C Control Port. Serial Clock for the I2C Control Port. Test Pin. Connect to ODVDD. Test Pin. Connect to ODVDD. Serial Data Inputs. These input pins provide the digital audio data to the signal processing core. Any one of the four inputs can be routed to the SRC for sample rate conversion; however, this input is not available to the core directly, but only as the output of the SRC. The serial format is selected by writing to Bits[2:0] of the input sport control register. The input serial port is always a synchronous slave device. The serial port uses BCLK1 and LRCLK1 from the output serial port as timing signals for SDIN0 to SDIN3. Rev. PrG | Page 9 of 36 AD0 SDA SCL TEST0 TEST1 SDIN[0:3] I 05621-005 ADAV400 Pin No. 26 27 29 30 33 34 Mnemonic LRCLK0 BCLK0 ODVDD VDRIVE MCLKI MCLKO I O I/O I I Description Left-Right Clock for SRC. This input frame synchronization signal is associated with the SDIN0 to SDIN3 signals when one of these channels is connected to the SRC. Bit Clock for SRC. This input clock is associated with the SDIN0 to SDIN3 signals when one of these channels is connected to the SRC. Digital Interface Supply (3.3 V) Pin. Connect this pin to a +3.3 V digital supply. Decouple the pin with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. Drive for External PNP Transistor. The base of the voltage regulator's external PNP transistor is driven from this pin. Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate the appropriate internal clock for the DSP core. Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock. This clock can be used elsewhere in the system if it is required to synchronize additional components with the ADAV400. Use Bit 5 to Bit 3 in User Control Register 1 to select the clock on this pin. Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices. Left-Right Clock for Serial Data Input/Output. This clock and the BCLK1 are used as clock and frame sync signals for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a slave and outputs when the port is configured as a master. On power up, these pins are set to slave mode to avoid conflicts with external master mode devices. Serial Data/TDM/Data Outputs. Use these pins for serial digital outputs. For non-TDM systems, these pins can output four channels of digital audio using a variety of standard two-channel formats. The configuration of the output port is set by the output sport control register. Active Low Reset Signal. After RESET goes high, all the circuit blocks of the ADAV400 are powered down. Individually power up the blocks by programming the appropriate bits in the power control register. When the audio processor core is powered up, it takes 3,072 MCLK cycles to initialize the internal circuitry. Do not attempt to load a new program during this period. When the core is powered up, it takes approximately 32,768 MCLK periods to initialize the data RAM. The data RAM is not available during this time. Analog Power Supply Pin for the PLL. Connect this pin to +3.3 V and decouple it with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL Block section for details of these components. PLL Ground. Connect this pin to the analog ground plane. Headphone Driver Ground. Connect this pin to the analog ground plane. Left Headphone Output. Analog output from the headphone amplifiers. Right Headphone Output. Analog output from the headphone amplifiers. Analog Power Supply Pin for the Headphone Driver. Connect this pin to +3.3 V and decouple it with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. Auxiliary DAC Output Left 1. Analog output from the on-chip auxiliary DACs. Auxiliary DAC Output Right 1. Analog output from the on-chip auxiliary DACs. Main DAC Output 1 to Output 4. Analog outputs from the on-chip DACs. Auxiliary DAC Output Left 2. Analog output from the on-chip auxiliary DACs. Auxiliary DAC Output Right 2. Analog output from the on-chip auxiliary DACs. Test Pin. This pin should be left unconnected. DAC Filter Decoupling Node. Decouple this pin with a 47 F capacitor and 0.1 F capacitor to AGND. Analog Power Supply Pin for the DAC. Connect this pin to +3.3 V and decouple it with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. DAC Ground. Connect this pin to the analog ground plane. Analog Power Supply Pin for the DAC. Connect this pin to +3.3 V and decouple it with a 47 F capacitor and 0.1 F capacitor to AGND as close as possible to the pin. Left Analog Input 1 to Input 4. The analog inputs are current inputs driven via a 20 k resistor as shown in Figure 17. Right Analog Input 1 to Input 4. The analog inputs are current inputs driven via a 20 k resistor as shown in Figure 17. DAC External Bias Resistor. This is an external bias pin for the DAC circuitry. Connect a 20 k resistor between this pin and AGND. Rev.PrG | Page 10 of 36 35 BCLK1 I/O 36 LRCLK1 I/O 37, 38, 42, 43 46 SDO[0:3] 0 RESET I 49 50 51 52 53 54 55 56 57 58 to 61 62 63 64 67 68 69, 70 71 72, 74, 76, 78 73, 75, 77, 79 80 AVDD2 PLL_LF AGND AGND HPOUTL HPOUTR AVDD3 AUXL1 AUXR1 VOUT[1:4] AUXL2 AUXR2 TEST2 FILTD AVDD4 AGND AVDD5 AINL[1:4] AINR[1:4] IDAC I I O O O O O O O ADAV400 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 -50 MAGNITUDE (dB) MAGNITUDE (dB) 05621-006 -50 -100 -150 -100 -200 -250 05621-009 -150 0 192 384 FREQUENCY (kHz) 576 -300 0 128 256 FREQUENCY (kHz) 768 384 Figure 6. DAC Composite Filter Response (48 kHz) Figure 9. ADC Composite Filter Response (48 kHz) 0 0 -50 MAGNITUDE (dB) 05621-007 MAGNITUDE (dB) -50 -100 -150 -100 -200 -150 0 24 48 FREQUENCY (kHz) 72 -300 0 24 48 FREQUENCY (kHz) 72 96 96 Figure 7. DAC Pass-Band Filter Response (48 kHz) 0.06 0.006 Figure 10. ADC Pass-Band Filter Response (48 kHz) 0.04 0.004 MAGNITUDE (dB) 0 MAGNITUDE (dB) 0.02 0.002 0 -0.02 -0.002 -0.04 05621-008 -0.004 05621-011 -0.06 0 8 16 FREQUENCY (kHz) 24 -0.006 0 8 16 FREQUENCY (kHz) 24 Figure 8. DAC Pass-Band Ripple (48 kHz) Figure 11. ADC Pass-Band Ripple (48 kHz) Rev. PrG | Page 11 of 36 05621-010 -250 ADAV400 0 DNR = 95dB (A-WEIGHTED) 0 THD+N = -93dB VIN = -3dBFS -20 -20 -40 MAGNITUDE (dB) -40 MAGNITUDE (dB) 05621-012 -60 -80 -100 -60 -80 -100 -140 0 8000 16000 FREQUENCY (Hz) -140 0 8000 16000 FREQUENCY (Hz) 24000 24000 Figure 12. DAC Dynamic Range 0 THD+N = -90dB INPUT = -3dBFS Figure 15. ADC Total Harmonic Distortion + Noise 0 -20 -5 -40 MAGNITUDE (dB) -60 -80 -100 MAGNITUDE (dB) -10 -15 05621-013 -140 0 8000 16000 FREQUENCY (Hz) -20 0 0.1 0.2 0.3 FS (Normalized) 0.4 24000 0.5 Figure 13. DAC Total Harmonic Distortion+ Noise 0 DNR = 95dB (A-WEIGHTED) Figure 16. Sample Rate Converter Transfer Function -20 -40 MAGNITUDE (dB) -60 -80 -100 -140 0 8000 16000 FREQUENCY (Hz) 24000 Figure 14. ADC Dynamic Range 05621-014 -120 Rev.PrG | Page 12 of 36 05621-037 -120 05621-015 -120 -120 ADAV400 THEORY OF OPERATION The ADAV400 is an enhanced audio processor containing an Analog Devices SigmaDSP digital processing core. The digital processor accepts digital inputs from up to four stereo channels, typically operating at 48 kHz. A sample rate converter (SRC) is included, allowing a single stereo channel that is not sampled at 48 kHz to be converted to 48 kHz before being processed. In addition, any of the four stereo analog sources can be processed by converting them to digital data via the high performance on-chip ADC. Processed data is available in digital form as a standard audio stream such as I2S or left/right justified. The processed audio data can also be converted to analog form by using the four high performance on-chip stereo DACs. The core of the ADAV400 is a 28-bit DSP (56-bit with double precision), optimized for audio processing. Signal processing parameters are stored in a 1024-location parameter RAM. The program RAM can be loaded with a custom program after power-up. New values are written to the program and parameter RAM using the control port. The values stored in the parameter RAM control individual signal processing blocks, such as IIR equalization filters, dynamics processors, audio delays, and mixer levels. A safeload feature allows transparent updating of the parameters without causing clicks on the output signals. The target/slew RAM contains 64 locations that can be used as channel volume controls or for other parameter updates. These RAM locations take a target value for a given parameter and ramp the current parameter value to the new value using a specified time constant and one of a selection of linear or logarithmic curves. The ADAV400 has a sophisticated control port that supports complete read/write capability of all memory locations except the target/slew RAM. The ADAV400 has very flexible serial data input/output ports that allow for glueless interconnection to a variety of ADCs, DACs, general-purpose DSPs, S/PDIF receivers, and sample rate converters. The digital inputs and outputs of the ADAV400 can be configured in I2S, left-justified or right-justified, or TDM serial port-compatible modes. It can support 16, 20, and 24 bits in all modes. The ADAV400 accepts serial audio data in MSB first and twos complement formats. The digital core of ADAV400 operates at 1.8 V and the other circuit blocks operate from a 3.3 V power supply. An on-board regulator allows a single 3.3 V supply for both digital supplies using the configuration shown in Figure 20. The ADAV400 is fabricated on a single monolithic integrated circuit and is housed in an 80-lead LQFP package for operation over the -40C to +105C automotive temperature range. ANALOG INPUT MULTIPLEXER The ADAV400 has eight analog input channels arranged as four stereo pairs. Any one of these stereo channels can be connected to a high performance ADC. The digital output of the ADC is then used by the audio processor core. The ADC multiplexer is controlled by Bit 3 to Bit 0 of the ADC input mux register. Set only one of these bits at a time. The ADC, ADC digital engine, and reference buffer must be powered up to use the ADC. This is achieved by setting Bit 14 and Bit 13 to 1 in the power control register. The analog input is a current input by default, but can be converted to a voltage input by using series resistors, as shown in Figure 17. 47F 20k AINLx 47F 20k AINRx 20k Figure 17. Analog Input Configuration SAMPLE RATE CONVERTER BLOCK The ADAV400 contains an SRC, allowing input sample rates other than 48 kHz to be used as digital inputs. The SRC is powered up by setting the SRC bit in the power control register (see Table 36). To use the SRC, the user programs Bit 6 and Bit 5 in the SRC serial port control register (see Table 34) to select which one of the four SDIN channels is connected to the input of the SRC. Using the SRC implies that one of the SDIN inputs is at a sample rate other than the default 48 kHz, therefore, it should not be used by the audio processor core. To prevent this input from being available to the core, set the SRC mux enable bit in the User Control Register 1. This bit enables the SRC input multiplexer and masks the selected input so that it is not available to the audio processor core. When the SRC mux enable bit is 0, SDIN3 appears at the output of the SRC. Figure 18 shows how the SRC block is configured. Note that the SRC has a filter cutoff frequency of 20 kHz for a 48 kHz sample rate. If a different sample rate is used, the cutoff frequency scales accordingly. LRCLK0 BCLK0 REG: 0x0000 BIT 5-4 REG: 0x0000 BIT 3 PU SRC AUDIO PROCESSOR CORE MULTICHANNEL DIGITAL INPUTS Figure 18. SRC Input Configuration Rev. PrG | Page 13 of 36 05621-017 SDIN0 SDIN1 SDIN2 SDIN3 05621-016 IDAC ADAV400 PLL BLOCK The ADAV400 contains a phase-locked loop (PLL) that generates all the clocks required by the system from a single input source. An input clock source is required. The clock frequency can be 64 x fS, 128 x fS, 256 x fS, or 512 x fS. Program Bit 2 and Bit 1 in User Control Register 1 for the appropriate clock frequency to ensure that the correct clock frequencies are generated. The PLL is powered down by default; Bit 15 in the power control register must be set to use the PLL (see Table 36). Bit 0 of User Control Register 1 determines whether the PLL is used (see Table 38). This bit is cleared after a reset, indicating that the PLL is not used and the clock on the MCLKI pin is used by the audio processing core. This allows the user to write to the part while the PLL is off. Power-up the PLL and set Bit 0 of User Control Register 1 to enable the PLL to generate all the clocks required for normal operation. The PLL requires some external components to operate correctly. These components, shown in Figure 19, form a loop filter that integrates the current pulses from a charge pump and produces a voltage to tune the VCO. A good quality capacitor, such as polyphenylene sulfide (PPS) film, is recommended. AVDD2 100nF 1nF 2k HEADPHONE AMPLIFIER The ADAV400 has an integrated stereo headphone amplifier that is capable of driving a 32 load. The headphone amplifier is internally connected to the output of Auxiliary DAC 1. The amplifiers are powered down by default and powered up by setting Bit 4 and Bit 3 in the power control register. Auxiliary DAC 1 also needs to be powered up when the headphone amplifier is required. The outputs of the headphone amplifiers use the same RC filters as the VOUT pins (see Figure 37). VOLTAGE REGULATOR The ADAV400 includes an on-chip voltage regulator that allows the chip to be used in systems where a 1.8 V supply is not available, but a 3.3 V supply is. The only external components needed are a PNP transistor (such as an FZT953), a single capacitor, and a single resistor. The recommended design for the voltage regulator is shown in Figure 20. The 10 F capacitor shown in this schematic is recommended for decoupling, but is not necessary for operation. Here, VDD is the main system voltage (3.3 V). A voltage of 1.8 V is generated at the transistor's collector that is connected to the DVDD pins. The reference voltage on VDRIVE is 2.6 V and is generated by the regulator. VDRIVE is connected to the base of the PNP transistor. Connect a 1 k resistor between VDRIVE and VDD. 10F + 100nF VDD PLL_LF 05621-018 PLL BLOCK Figure 19. PLL Loop Filter Components 1k 47F + 47F + 100nF 47F + 100nF A 3.3 V analog supply, connected to AVDD2, is required to operate the PLL. Where the supply for AVDD1 is also used for the PLL, additional filtering is recommended to prevent digital noise created by the PLL block being coupled to the analog circuitry powered by the AVDD1 supply. VDRIVE ODVDD DVDD ADAV400 Figure 20. Voltage Regulator Design ANALOG OUTPUTS The ADAV400 contains eight high performance DACs arranged as four stereo pairs. The DACs are the main outputs from the audio processor core. One pair of DACs are connected to integrated headphone amplifiers, although the outputs are also available on the AUXL1 and AUXR1 pins. Each stereo DAC has independent power control and is powered down by default. Power up the DACs by setting the appropriate bit in the power control register. Note that the output of the DAC section forms an inverting amplifier; thus, for a positive full-scale digital code, the DAC generates a negative full-scale signal. If required, this can be inverted in the audio flow. The headphone amplifiers are also inverting amplifiers thereby correcting the inversion for the headphone outputs. There are two specifications to take into consideration when choosing a regulator transistor. First, the transistor's current amplification factor (hFE or beta) should be at least 100. Second, the transistor's collector needs to be able to dissipate the heat generated when regulating from 3.3 V to 1.8 V. The maximum digital current draw of the ADAV400 is 135 mA. The equation for the minimum power dissipation is as follows: (3.3 V - 1.8 V) x 135 mA = 202.5 mW If the regulator is not used in the design, tie VDRIVE to ground. Rev.PrG | Page 14 of 36 05621-019 ADAU1421 DVDD ADAV400 SIGNAL PROCESSING The ADAV400 is designed to provide all signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is set by the software supplied by Analog Devices, which allows graphical entry and real-time control of all signal processing functions. Many of the signal processing functions are coded using full, 56-bit double-precision arithmetic. The input and output word lengths are 24 bits. Four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping. Additional gains are achieved by initially scaling down the input signal in the signal flow. The signal processing blocks can be arranged in a custom program that is loaded to the RAM of the ADAV400. The available signal processing blocks are explained in the Numeric Formats and Programming sections. top four bits of the signal to produce a 24-bit output with a range of +1.0 (- 1 LSB) to -1.0. 4-BIT SIGN EXTENSION SIGNAL PROCESSING (5.23 FORMAT) 1.23 5.23 5.23 DIGITAL CLIPPER 1.23 Figure 21. Numeric Precision and Clipping Structure PROGRAMMING On power-up, the default program of the ADAV400 passes the unprocessed input signals to the outputs, but the outputs are muted by default. There are 2,560 instruction cycles per audio sample. This DSP runs in a stream-oriented manner, meaning all 2,560 instructions are executed each sample period. The ADAV400 can also be set up to accept double- or quad-speed inputs by reducing the number of instructions per sample. This reduction is set in the audio core control register. The part is easily programmed using graphical tools provided by Analog Devices. No knowledge of writing DSP code is needed to program the ADAV400. Simply connect graphical blocks such as biquad filters, dynamics processors, mixers, and delays in a signal flow schematic. The schematic is then compiled, and the program and parameter files are loaded into the program RAM of the ADAV400 through the control port. Signal processing blocks available in the provided libraries include: * * * * * * * * * * * * Single and double precision bi-quad filters Mono- and multi-channel dynamics processors Mixers and splitters Tone and noise generators First-order filters Fixed and variable gain RMS look-up tables Loudness Delay Stereo enhancement (Phat StereoTM) Dynamic bass boost Interpolators and decimators NUMERIC FORMATS It is common in DSP systems to use a standardized method of specifying numeric formats. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. The ADAV400 uses the same numeric format for both the coefficient values (stored in the parameter RAM) and the signal data values. Numeric Format: 5.23 Range: -16.0 to (+16.0 - 1 LSB) Examples: 1000 0000 0000 0000 0000 0000 0000 = -16.0 1110 0000 0000 0000 0000 0000 0000 = -4.0 1111 1000 0000 0000 0000 0000 0000 = -1.0 1111 1110 0000 0000 0000 0000 0000 = -0.25 1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0) 0000 0000 0000 0000 0000 0000 0000 = 0.0 0000 0010 0000 0000 0000 0000 0000 = +0.25 0000 1000 0000 0000 0000 0000 0000 = +1.0 0010 0000 0000 0000 0000 0000 0000 = +4.0 0111 1111 1111 1111 1111 1111 1111 = (+16.0 - 1 LSB) The serial port accepts up to 24 bits on the input and is signextended to the full 28 bits of the core. This allows internal gains of up to 24 dB without encountering internal clipping. A digital clipper circuit is used between the output of the DSP core and the serial output ports (see Figure 21). This clips the Additional blocks are always in development. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms. Rev. PrG | Page 15 of 36 05621-020 DATA IN SERIAL PORT ADAV400 CONTROL PORT The ADAV400 has many different control options that can be set through an I2C interface. The ADAV400 uses a 2-wire I2C bus control port. Most signal processing parameters are controlled by writing new values to the parameter RAM using the control port. Other functions, such as mute and input/output mode control, are programmed by writing to the control registers. The control port is capable of full read/write operation for all memories and registers. All addresses can be accessed in either single-address or burst mode. A control word consists of the chip address, the register/RAM subaddress, and the data to be written. The number of bytes per word depends on the type of data that is written. The first byte of a control word (Byte 0) contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the memory or register location within the ADAV400. This subaddress must be two bytes because the memories within the ADAV400 are directly addressable and their sizes exceed the range of single-byte addressing. All subsequent bytes (Byte 3, Byte 4, and so on) contain data such as control port, program, or parameter data. The exact formats for specific types of writes are listed in Table 17 to Table 26. The ADAV400 has several mechanisms for updating signal processing parameters in real time without causing pops or clicks. In cases where large blocks of data need to be downloaded, halt the output of the DSP core using Bit 9 of the audio core control register, load the new data, and then restart the core. This is typically done during the booting sequence at startup, or when loading a new program into RAM. In cases where only a few parameters need to be changed, they can be loaded without halting the program. To avoid unwanted side effects while loading parameters on the fly, the SigmaDSP provides safeload registers. The safeload registers buffer a full set of parameters (such as the five coefficients of a biquad), and then transfer these parameters into the active program within one audio frame. The safeload mode uses internal logic to prevent contention between the DSP core and the control port. a read operation and Logic Level 0 corresponds to a write operation. The seventh bit of the address is set by tying the AD0 pin of the ADAV400 to Logic Level 0 or Logic Level 1. Table 5. I2C Addresses AD0 0 0 1 1 R/W 0 1 0 1 Slave Address 0x28 0x29 0x2A 0x2B Addressing Initially, all devices on the I2C bus are in an idle state wherein the devices monitor the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and read the next byte (7-bit address + R/W bit) MSB-first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic Level 0 on the LSB of the first byte means the master writes information to the peripheral. A Logic Level 1 on the LSB of the first byte means the master reads information from the peripheral. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. Figure 22 shows the timing of an I2C write. Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically if a stop condition is not encountered after a single word write. The registers and memories in the ADAV400 range in width from one to six bytes, so the autoincrement feature knows the mapping between subaddresses and the word length of the destination register (or memory location). A data transfer is always terminated by a stop condition. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAV400 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. In read mode, the ADAV400 outputs the highest subaddress register contents until the master device issues a no acknowledge, I2C PORT The ADAV400 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAV400 and the system I2C master controller. The ADAV400 is always a slave on the I2C bus, which means that it never initiates a data transfer. Each slave device is recognized by a unique address. The ADAV400 has four possible slave addresses, two for writing operations and two for reading. These are unique addresses for the device and are illustrated in Table 5. The LSB of the byte sets either a read or a write operation; Logic Level 1 corresponds to Rev.PrG | Page 16 of 36 ADAV400 indicating the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADAV400, and the part returns to the idle condition. operation. This is because the subaddress still must be written in order to set up the internal address. After the ADAV400 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W set to 1 (read). This causes the SDA of the ADAV400 to turn around and begin driving data back to the master. The master then responds every ninth clock with an acknowledge pulse to the ADAV400. Table 9 shows the timing of a burst mode read sequence. This table shows an example where the target read registers are two bytes. The ADAV400 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. Other address ranges may have a variety of word lengths ranging from one to six bytes; the ADAV400 always decodes the subaddress and sets the auto-increment circuit so that the address increments after the appropriate number of bytes. I2C Read and Write Operations Table 6 shows the timing of a single word write operation. Every ninth clock, the ADAV400 issues an acknowledge by pulling SDA low. Table 7 shows the timing of a burst mode write sequence. This table shows an example where the target destination registers are two bytes. The ADAV400 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length. The timing of a single word read operation is shown in Table 8. Note that the first R/W bit is still a 0, indicating a write Key for Table 6 to Table 9: S = start bit P = stop bit AM = acknowledge by master AS = acknowledge by slave Table 6. Single Word I2C Write S Chip Address, R/W = 0 AS Subaddress High AS Subaddress Low AS Data Byte 1 AS Data Byte 2 ... AS Data Byte N P Table 7. Burst Mode I2C Write Chip Address, S R/W = 0 Subaddress AS High Subaddress AS Low Data-Word 1 AS Byte 1 Data-Word 1 AS Byte 2 Data-Word 2 AS Byte 1 Data-Word 2 AS Byte 2 AS ... P Table 8. Single Word I2C Read Chip Address, S R/W = 0 AS Subaddress High AS Subaddress Low Chip Address AS S R/W = 1 AS Data Byte 1 AM Data Byte 2 ... Data AM Byte N P Table 9. Burst Mode I2C Read Chip Address, R/W = 0 Subaddress High Subaddress Low Chip Address R/W = 1 Data-Word 1 Byte 1 Data-Word 1 Byte 2 S AS AS AS S AS AM AM ... P Rev. PrG | Page 17 of 36 ADAV400 SCK SDA START BY MASTER 0 0 1 0 1 0 ADR SEL R/W ACK. BY ADAU1421 ACK. BY ADAU1421 FRAME 2 SUBADDRESS BYTE 1 FRAME 1 CHIP ADDRESS BYTE SCK (CONTINUED) SDA (CONTINUED) FRAME 2 SUBADDRESS BYTE 2 FRAME 3 DATA BYTE 1 Figure 22. I2C Write Format SCK SDA START BY MASTER 0 0 1 0 1 0 ADR SEL R/W ACK. BY ADAU1421 ACK. BY ADAU1421 FRAME 2 SUBADDRESS BYTE 1 FRAME 1 CHIP ADDRESS BYTE SCK (CONTINUED) SDA (CONTINUED) ACK. BY REPEATED ADAU1421 START BY MASTER 0 0 1 0 1 0 ADR SEL R/W ACK. BY ADAU1421 FRAME 3 SUBADDRESS BYTE 2 SCK (CONTINUED) SDA (CONTINUED) FRAME 4 CHIP ADDRESS BYTE FRAME 5 READ DATA BYTE 1 FRAME 6 READ DATA BYTE 1 Figure 23. I2C Read Format Rev.PrG | Page 18 of 36 05621-022 ACK. BY MASTER ACK. BY MASTER STOP BY MASTER 05621-021 ACK. BY ADAU1421 ACK. BY STOP BY ADAU1421 MASTER ADAV400 RAMS AND REGISTERS Table 10. Control Port Addresses I2C Subaddress 0 to 1023 (0x0000 to 0x03FF) 1024 to 4095 (0x0400 to 0x0FFF) 4096 to 4159 (0x1000 to 0x103F) 4160 to 4164 (0x1040 to 0x1044) 4165 to 4169 (0x1045 to 0x1049) 4170 to 4175 (0x104A to 0x104F) 4176 to 4177 (0x1050 to 0x1051) 4178 (0x1052) 4179 (0x1053) 4180 (0x1054) 4181 (0x1055) 4182 (0x1056) 4183 (0x1057) 4184 (0x1058) 4185 (0x1059) 4186 (0x105A) 4365 (0x110D) Register Name Parameter RAM Program RAM Target/Slew RAM Parameter RAM Data Safeload Register[0: 4] Parameter RAM Indirect Address Safeload Register[0:4] Data Capture Register[0:5] (Control Port Readback) Data Capture Registers (Digital Output) Audio Core Control Register RAM Modulo Control Register Serial Output Control Register Serial Input Control Register SRC Serial Port Control Register ADC Input Mux Control Register Power Control Register User Control 1 Register User Control 2 Register DAC Amplifier Register Read/Write Word Length Write: 4 Bytes, Read: 4 Bytes Write: 6 Bytes, Read: 6 Bytes Write: 5 Bytes, Read: N/A Write: 5 Bytes, Read: N/A Write: 2 Bytes, Read: N/A Write: 2 Bytes, Read: 3 Bytes Write: 2 Bytes, Read: N/A Write: 2 Bytes, Read: 2 Bytes Write: 1 Byte, Read: 1 Byte Write: 2 Bytes, Read: 2 Bytes Write: 1 Byte, Read: 1 Byte Write: 1 Byte, Read: 1 Byte Write: 2 Bytes, Read: 2 Bytes Write: 2 Bytes, Read: 2 Bytes Write: 2 Bytes, Read: 2 Bytes Write: 2 Bytes, Read: 2 Bytes Write: 2 Bytes, Read: 2 Bytes Table 11. RAM Read/Write Modes Memory Parameter RAM Program RAM Target/Slew RAM 1 Size 1024 x 28 2560 x 42 64 x 34 Subaddress Range 0 to 1023 (0x0000 to 0x03FF) 1024 to 3584 (0x0400 to 0x0E00) 4096 to 4159 (0x1000 to 0x1044) Read Yes Yes No Write Yes Yes Yes Burst Mode Available Yes Yes No Write Modes Direct Write1, Safeload Write Direct Write1 Safeload Write To avoid clicks or pops, shut down the DSP core first. CONTROL PORT ADDRESSING Table 10 shows the addressing of the RAM and register spaces of the ADAV400. The address space encompasses a set of registers and three RAMs; one each for holding signal processing parameters, holding the program instructions, and ramping parameter values. The program and parameter RAMs initialize on power-up. Table 11 lists the sizes and available writing modes of the parameter, program, and target/slew RAMs. Options for Parameter Updates The parameter RAM can be written and read using one of the two following methods: 1. Direct Read/Write. This method allows direct access to the program and parameter RAMs. This mode of operation is normally used during a complete new load of the RAMs using burst mode addressing. To avoid clicks or pops in the outputs, set the clear registers bit in the audio core control register to 0. It is also possible to use this mode during live program execution. However, because there is no handshaking between the core and the control port, the parameter RAM is unavailable to the DSP core during control writes, resulting in clicks and pops in the audio stream. Safeload Write. Up to five safeload registers can be loaded with parameter RAM address data. The data is transferred to the requested address when the RAM is not busy. Use this method for dynamic updates while live program material is playing through the ADAV400. PARAMETER RAM CONTENTS The parameter RAM is 28 bits wide and occupies Address 0 to Address 1023. The parameter RAM is initialized to all 0s on power-up. The data format of the parameter RAM is twos complement 5.23. This means that the coefficients can range from +16.0 (- 1 LSB) to -16.0, with 1.0 represented by the binary word 0000 1000 0000 0000 0000 0000 0000. 2. Rev. PrG | Page 19 of 36 ADAV400 For example, a complete update of one biquad section can occur in one audio frame while the RAM is not busy. This method is not available for writing to the program RAM or control registers. The following sections discuss these two options in more detail. 7. If the newly loaded program also uses the target/slew RAM, deassert Bit 12 of the audio control register to begin a volume ramp-up procedure. TARGET/SLEW RAM The target/slew RAM is a bank of 64 RAM locations, each of which can each be set to autoramp from one value to a desired final value in one of four modes. RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURES When writing large amounts of data to the program or parameter RAM in direct write mode, disable the processor core to prevent unpleasant noises from appearing at the audio output. The ADAV400 contains several mechanisms for disabling the core. If the loaded program does not use the target/slew RAM as the main system volume control (for example, the default power-up program): 1. Assert Bit 9 (low to assert--default setting) and Bit 6 (high to assert) of the audio control register. This zeroes the accumulators, the serial output registers, and the serial input registers. Fill the program RAM using burst mode writes. Fill the parameter RAM using burst mode writes. Assert Bit 7 of the audio control register to initiate a data memory clear sequence. Wait at least 100 s for this sequence to complete. This bit is automatically cleared after the operation is complete. Deassert Bit 9 and Bit 6 of the audio control register to allow the core to begin normal operation Summary When a program is loaded into the program RAM using one or more locations in the slew RAM to access internal coefficient data, the target/slew RAM is used by the DSP. Typically, these coefficients are used for volume controls or smooth crossfading effects, but can be used to update any value in the parameter RAM. Each of the 64 locations in the slew RAM are linked to corresponding locations in the target RAM. When a new value is written to the target RAM using the control port, the corresponding slew RAM location begins to ramp toward the target. The value is updated once per audio frame (LRCLK period). The target RAM is 34 bits wide. The lower 28 bits contain the target data in 5.23 format for the linear and exponential (constant dB and RC type) ramp types. For constant time ramping, the lower 28 bits contain 16 bits in 2.14 format and 12 bits to set the current step. The upper six bits are used to determine the type and speed of the ramp envelope in all modes. The format of the data write for linear and exponential formats is shown in Table 12. Table 13 shows the data write format for the constant time ramping. In normal operation, write data to the target/slew RAM using the safeload registers as described in the Safeload Registers section. A mute slew RAM bit is included in the audio control register to simultaneously set all the slew RAM target values to 0. This is useful for implementing a global multichannel mute. When this bit is deasserted, all slew RAM values return to their original premuted states. Table 12. Linear, Constant dB, and RC Type Ramp Data Write Byte 0 000000, curve_type[1:0] Byte 1 time_const[3:0], data[27:24] Bytes[2:4] data[23:0] 2. 3. 4. 5. If the loaded program does use the target/slew RAM as the main system volume control: 1. Assert Bit 12 of the audio control register. This begins a volume ramp down, with a time constant determined by the upper bits of the target RAM. Wait for this ramp-down to complete (the user can poll Bit 13 of the audio control register, or simply wait for a given amount of time). Assert Bit 9 (low to assert) and Bit 6 (high to assert) of the audio control register. This zeroes the accumulators, the serial output registers, and the serial input registers. Fill the program RAM using burst mode writes. Fill the parameter RAM using burst mode writes. Assert Bit 7 of the audio control register to initiate a data memory clear sequence. Wait at least 100 s for this sequence to complete. This bit is automatically cleared after the operation is complete. Deassert Bit 9 and Bit 6 of the audio control register. 2. 3. 4. 5. Table 13. Constant Time Ramp Data Write Byte 0 000000, curve_type[1:0] Byte 1 update_step[0], #_of_steps[2:0], data[15:12] Bytes[2:4] data[11:0], reserved[11:0] 6. Rev.PrG | Page 20 of 36 ADAV400 The four ramping curve types are: Linear The value slews to target using a fixed step size. Constant dB The value slews to target using the current value to calculate the step size. The resulting curve has a constant rise and decay when measured in dB. RC Type The value slews to target using the difference between target and current values to calculate the step size, producing a simple RC-type curve for rising and falling. Constant Time The value slews to the target in a fixed number of steps in a linear fashion. The control port mute has no affect on this type. Table 14. Target/Slew RAM Ramp Type Settings Settings 00 01 10 11 Ramp Type Linear Constant dB RC Type Constant Time Number of Steps (3 bits). The number of steps that it takes to slew to the target value is set by these three bits, with the number of steps equal to 23-bit setting + 6. 000 = 64 001 = 128 010 = 256 011 = 512 100 = 1024 101 = 2048 110 = 4096 111 = 8196 Data (16 bits). 2.14 format. Reserved (12 bits). When writing to the RAM, set all of these bits to 0. Target and Slew RAM Initialization On reset, the target/slew RAM initializes to preset values. The target RAM initializes to a linear ramp type with a time constant of 5 and the data set to 1.0. The slew RAM initializes to a value of 1.0. These defaults give a full-scale (1.0 to 0.0) ramp time of 21.3 ms. Linear Update Math Linear math is the addition or subtraction of a constant value, referred to as a step. The equation to describe this step size is The following sections detail how the control port writes to the target/slew RAM to control the time constant and ramp type parameters. Ramp Types[1:3]--Linear, Constant dB, RC Type (34-Bit Write) The target word for the first three ramp types is broken into three parts. The 34-bit command is written with six leading 0s to extend the data write to five bytes. The parts of the target RAM write are: Ramp Type (2 bits). Time Constant (4 bits). 0000 = fastest 1111 = slowest Data (28 bits): 5.23 format. step = 10 2x (tconst - 5 ) 20 213 The result of the equation is normalized to a 5.23 data format. This gives a time constant range from 6.75 ms to 213.4 ms. (-60 dB relative to 0 dB full-scale). An example of this kind of update is shown in Figure 24 and Figure 25. All slew RAM figure examples, except the half-scale constant time ramp plot, show an increasing or decreasing ramp between -80 dB and 0 dB (full-scale). All figures except the constant time plots (Figure 29 and Figure 30) use a time constant of 0x7 (0x0 being the fastest and 0xF being the slowest). 1.0 0.8 0.6 OUTPUT LEVEL (V) Ramp Type 4--Constant Time (34-Bit Write) The target word for the constant time ramp type is written in five parts, with the 34-bit command written with six leading 0s to extend the data write to five bytes. The parts of the constant time target RAM write are: Ramp Type (2 bits). Update Step (1 bit). Set to 1 when new target is loaded to trigger step value update. Value is automatically reset after the step value is updated. 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 05621-023 35 Figure 24. Slew RAM--Linear Update Increasing Ramp Rev. PrG | Page 21 of 36 ADAV400 1.0 0.8 0.6 OUTPUT LEVEL (V) 1.0 0.8 0.6 OUTPUT LEVEL (V) 0.4 0.2 0 -0.2 -0.4 -0.6 05621-024 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 05621-026 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 35 35 Figure 25. Slew RAM--Linear Update Decreasing Ramp Figure 27. Slew RAM--RC Type Update Increasing Ramp 1.0 0.8 0.6 Constant dB and RC Type (Exponential) Update Math Exponential math is accomplished by shifts and adds with a range from 6.1 ms to 1.27 s (-60 dB relative to 0 dB full-scale). When the ramp type is set to 01 (constant dB), each step size is set to the current value in the slew data. When the ramp type bits are set to 10 (RC type), the step sizes are equal to the difference between the values in the target RAM and slew RAM. Figure 26 and Figure 27 show examples of this type of target/slew RAM ramping. A decreasing ramp of both the constant dB and RC type ramps is a mirror image of the constant dB increasing ramp, and is shown in Figure 28. 1.0 0.8 0.6 OUTPUT LEVEL (V) 0.4 0.2 0 -0.2 -0.4 -0.6 05621-027 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 35 Figure 28. Slew RAM--Constant dB and RC Type Update Decreasing Ramp, Full Scale OUTPUT LEVEL (V) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 05621-025 Constant Time Update Math Constant time math is accomplished by adding a step value that is calculated after each new target is loaded. The equation for this step size is Step = (Target Data - Slew Data)/(Number of Steps) Figure 29 shows a plot of the target/slew RAM operating in constant time mode. For this example, 128 steps are used to reach the target value. This type of ramping takes a fixed amount of time for a given number of steps, regardless of the difference in the initial state and the target value. Figure 30 shows a plot of a constant time ramp from -80 dB to -6 dB (half scale) using 128 steps; thus, the ramp takes the same amount of time as the previous ramp from -80 dB to 0 dB. A constant time decreasing ramp plot is shown in Figure 30. 35 Figure 26. Slew RAM--Constant dB Update Increasing Ramp Rev.PrG | Page 22 of 36 ADAV400 1.0 0.8 0.6 OUTPUT LEVEL (V) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 05621-028 35 leading to transients that take a long time to decay. To eliminate this problem, the ADAV400 loads a set of 10 registers in the control port (five for 28-bit parameters, and another five for indirectly addressing the target/slew RAMs) with the desired parameter or target/slew RAM address and data. Five registers are used because a biquad filter uses five coefficients, and it is desirable to be able to do a complete biquad update in one transaction. The safeload registers can be used to update either the parameter RAM or target/slew RAM values. Once these registers are loaded, the appropriate initiate safe transfer bit (there are separate bits for parameter and target/slew loads) in the audio control register should be set to initiate the loading into RAM. Program lengths should be limited to 2,555 cycles (2,560 - 5) to ensure that the ADAV400 is able to perform the safeloads. It is guaranteed that the safeload occurs within one LRCLK period (21 s at fS = 48 kHz) of the initiate safe transfer bit being set. The safeload logic automatically sends only those safeload registers that have been written to since the last safeload operation. For example, if only two parameters are to be sent, only two of the five safeload registers must be written to. When the initiate safe transfer bit (in the audio control register) is asserted, only those two registers are sent; the other three registers are not sent to the RAM and can still hold old or invalid data. Table 15. Data Capture Control Registers Register Bits 13:2 1:0 Function 12-Bit Program Counter Address Register Select 00 = Mult_X_input 01 = Mult_Y_input 10 = MAC_output 11 = Accum_fback Figure 29. Slew RAM--Constant Time Update Increasing Ramp, Full Scale 1.0 0.8 0.6 OUTPUT LEVEL (V) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 05621-029 35 Figure 30. Slew RAM--Constant Time Update Increasing Ramp, Half Scale 1.0 0.8 0.6 OUTPUT LEVEL (V) DATA CAPTURE REGISTERS The ADAV400 data capture feature allows the data at any node in the signal processing flow to be sent to one of six control port-readable registers or to a serial output pin. Use this feature to monitor and display information about internal signal levels or compressor/limiter activity. The ADAV400 contains six independent control port-readable data capture registers, and two digital output capture registers. Use these registers when debugging the signal processing flow. For each of the data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 2,559 that corresponds to the program step number where the capture will occur. The register select field programs one of four registers in the DSP core that transfers to the data capture register when the program counter equals the capture count. The register select field selections are shown in Table 16. 05621-030 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 TIME (ms) 25 30 35 Figure 31. Slew RAM--Constant Time Update Decreasing Ramp, Full Scale SAFELOAD REGISTERS Many applications require real-time control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. To prevent instability from occurring, all of the parameters of a biquad filter must be updated at the same time. Otherwise, the filter can execute for one or two audio frames with a mix of old and new coefficients. This mix causes temporary instability Rev. PrG | Page 23 of 36 ADAV400 Table 16. Data Capture Output Register Select Settings 00 01 10 11 Register Multiplier X Input (Mult_X_input) Multiplier Y Input (Mult_Y_input) Multiplier-Accumulator Output (MAC_out) Accumulator Feedback (Accum_fback) multiple times during a single input audio sample period. Setting this bit to 1 allows the output LRCLK signal to control this data transfer rather than the internal end-of-sequence signal. Operation in this mode can require custom assembly language coding in the Analog Devices graphical tools. Clear Registers to All Zeros (Bit 9) Setting this bit to 0 sets the contents of the accumulators and serial output registers to 0. Like the other register bits, this one defaults to 0. This means the ADAV400 powers up in clear mode and does not pass signals until a 1 is written to this bit. This is intended to prevent noises from inadvertently occurring during the power-up sequence. The capture count and register select bits are set by writing to one of the eight data capture registers at register addresses. 4170: Control Port Data Capture Setup Register 0 4171: Control Port Data Capture Setup Register 1 4172: Control Port Data Capture Setup Register 2 4173: Control Port Data Capture Setup Register 3 4174: Control Port Data Capture Setup Register 4 4175: Control Port Data Capture Setup Register 5 4176: Digital Out Data Capture Setup Register 0 4177: Digital Out Data Capture Setup Register 1 The captured data is in 5.19 twos complement data format for all eight register select fields. The four LSBs are truncated from the internal 5.23 data-word. The data that must be written to set up the data capture is a concatenation of the 12-bit program count index with the 2-bit register select field. The capture count and register select values that correspond to the desired point to be monitored in the signal processing flow are found in a file output from the program compiler. The capture registers are accessed by reading from locations 4170 to 4175 (0x104A to 0x104F) for control port capture registers. The formats for reading and writing to the data capture registers are listed in Table 23 and Table 24. Force Multiplier to Zero (Bit 8) When this bit is set to 1, the input to the DSP multiplier is set to 0, which results in the multiplier output being 0. This control bit is included for maximum flexibility, and is normally not used. Initialize Data Memory with Zeros (Bit 7) Setting this bit to 1 initializes all data memory locations to 0. This bit is cleared to 0 after the operation is complete. Assert this bit after a complete program/parameter download has occurred to ensure click-free operation. Zero Serial Input Port (Bit 6) When this bit is set to 1, the serial input channels are forced to all zeros and effectively muted. Initiate Safe Transfer to Target RAM (Bit 5) Setting this bit to 1 initiates a safeload transfer to the target/slew RAM. This bit clears when the operation is completed. Of five safeload register pairs (address/data), only those registers that have been written since the last safeload event are transferred. Address 0 corresponds to the first target RAM location. AUDIO CORE CONTROL REGISTER The controls in this register set the operation of the DSP core of the ADAV400. Bit 6 to Bit 9 are used to initiate a shutdown of the core. The output is muted when this is performed; therefore, if slew RAM locations are used as volume controls in the program, assert Bit 12 of the audio core control register (Table 30) to avoid a click or pop when shutdown is asserted. Bit 13 indicates when this operation is complete. Initiate Safe Transfer to Parameter RAM (Bit 4) Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit clears when the operation is completed. Of five safeload registers pairs (address/data), only those registers that have been written since the last safeload event are transferred. Address 0 corresponds to the first parameter RAM location. Slew RAM Muted (Bit 13) This bit is set to 1 when the slew RAM mute operation has been completed. This bit is read-only and is automatically cleared by reading. Input Serial Port to Sequencer Sync (Bits[3:2]) Normally, the internal sequencer is synchronized to the incoming audio frame rate by comparing the internal program counter with the edge of the LRCLK input signal. In some cases the ADAV400 is used to decimate an incoming signal by some integer factor. In this case, it is desirable to synchronize the sequencer to a submultiple of the incoming LRCLK rate to make more than one audio input sample available to the program during a single audio output frame. For example, if these bits are set to 01 (LRCLK/2), a 96 kHz input can be used with a 48 kHz output, allowing two consecutive input samples to be processed during a single audio output frame. Operation Write Zero to Target RAM (Bit 12) Setting this bit to 1 is equivalent to writing zeros to all locations in the target RAM. The RAM then slews to zero, muting the volume. To enable normal operation, clear this bit to zero. Use Serial Out LRCLK for Output Latch (Bit 10) Normally, data is transferred from the DSP core to the serial output registers at the end of each program cycle. In some cases, such as when output sample rate is set to some multiple of input sampling rate, it is desirable to transfer the internal core data Rev.PrG | Page 24 of 36 ADAV400 in this mode may require custom assembly language coding in the Analog Devices graphical tools. with auto-incrementing address offset registers. The maximum setting of this register is the full size of the RAM, or 6,144 (6k) data-words. Note that addresses in this range automatically wrap around the modulo boundary as set by the register. This feature is not normally used with blocks supplied by Analog Devices. For normal operation, this register remains in its default state to set up the entire RAM to use the auto-increment feature. This feature is included for maximum programming flexibility and can be used for special software development. Program Length (Bits[1:0]) 96 kHz and 192 kHz Modes These bits set the length of the internal program. The default program length is 2,560 instructions for fS = 48 kHz, but the program length can be shortened by factors of 2 to accommodate sample rates higher than 48 kHz. For fS = 96 kHz, set the program length to 1,280 (01), and for fS = 192 kHz, set the length at 640 steps (10). CONTROL PORT READ/WRITE DATA FORMATS The read/write formats of the control port are designed to be byte-oriented. This allows for easy programming of common microcontroller chips. In order to fit into a byte-oriented format, 0s are appended to the data fields before the MSB to extend the data-word to the next multiple of eight bits. For example, 28-bit words written to the parameter RAM are appended with four leading 0s to reach 32 bits (4 bytes); 40-bit words written to the program RAM are not appended with any 0s because it is already a full 5 bytes. These zero-extended data fields are appended to a 3-byte field consisting of a 7-bit chip address, a read/write bit, and an 11-bit RAM/register address. The control port knows how many data bytes to expect based on the address that is received in the first three bytes. The total number of bytes for a single location write command can vary from four bytes (for a control register write), to eight bytes (for a program RAM write). Burst mode is used to fill contiguous register or RAM locations. A burst mode write is done by writing the address and data of the first RAM/register location to be written. Rather than ending the control port transaction, the next data word can be written immediately without first writing its specific address. The ADAV400 control ports auto-increment the address of each write, even across the boundaries of the different RAMs and registers. Low Power Modes All the blocks in the ADAV400 are individually controlled by power-up bits. Following a reset, all the bits are zero indicating that all the blocks are powered down. Blocks are powered up individually by setting the appropriate bit in the power control register (see Table 36). RAM CONFIGURATION REGISTER The ADAV400 uses a modulo RAM addressing scheme to allow filters and other blocks to be coded easily without requiring filter data to be explicitly moved during the filtering operation. This is accomplished by adding the contents of an address offset counter to the actual base address supplied in the core of the ADAV400. This address offset counter is automatically incremented at the audio frame rate. This method works well for most audio applications that involve filtering. In some cases, however, it is desirable to have direct access to the RAM, bypassing the auto-incrementing address offset counter. For this reason, the data memories in the ADAV400 can be divided into modulo and nonmodulo portions by programming the RAM modulo control register (see Table 31). The address range from 0 to 512 x (RAM configuration register contents) is treated as modulo memory Table 17. Parameter RAM Read/Write Format (Single Address) Byte 0 chip_adr [6:0], R/W Byte 1 000, param_adr [12:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes[4:6] param [23:0] Table 18. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 chip_adr [6:0], R/W Byte 1 000, param_adr [12:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes[4:6] param [23:0] Byte 7 Byte 8 Byte 9 Byte 10 param_adr + 1 Byte 11 Byte 12 Byte 13 Byte 14 param_adr + 2 <--param_adr--> Table 19. Program RAM Read/Write Format (Single Address) Byte 0 chip_adr [6:0], R/W Byte 1 000, prog_adr [12:8] Byte 2 prog_adr [7:0] Bytes[3:7] prog [39:0] Rev. PrG | Page 25 of 36 ADAV400 Table 20. Program RAM Block Read/Write Format (Burst Mode) Byte 0 chip_adr [6:0], R/W Byte 1 000, prog_adr [12:8] Byte 2 prog_adr [7:0] Bytes[3:7] prog [39:0] Byte 8 Byte 9 Byte 10 Byte 11 Byte 12 prog_adr +1 Byte 13 Byte 14 Byte 15 Byte 16 Byte 17 prog_adr +2 <--prog_adr--> Table 21. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1) Byte 0 chip_adr [6:0], R/W Byte1 000, reg_adr [12:8] Byte 2 reg_adr [7:0] Byte 3 data [15:8] Byte 4 data [7:0] Table 22. Control Register Read/Write Format (RAM Configuration, Serial Input) Byte 0 chip_adr [6:0], R/W Byte1 000, reg_adr [12:8] Byte 2 reg_adr [7:0] Byte 3 data [7:0] Table 23. Data Capture Register Write Format Byte 0 chip_adr [6:0], R/W Byte 1 000, data_capture_adr [12:8] Byte 2 data_capture_adr [7:0] Byte 3 000, progCount [10:6] Byte 4 progCount [5:0], regSel [1:0] Table 24. Data Capture (Control Port Readback) Register Read Format Byte 0 chip_adr [6:0], R/W Byte 1 000, data_capture_adr [12:8] Byte 2 data_capture_adr [7:0] Bytes[3:5] data [23:0] Table 25. Safeload Register Data Write Format Byte 0 chip_adr [6:0], R/W Byte 1 000, safeload_adr [12:8] Byte 2 safeload_adr [7:0] Byte 3 000000, data [33:32] Bytes[4:7] data [31:0] Table 26. Safeload Register Address Write Format Byte 0 chip_adr [6:0], R/W Byte 1 000, safeload_adr [12:8] Byte 2 safeload_adr [7:0] Byte 3 000000, param_adr [9:8] Byte 4 param_adr [7:0] Rev.PrG | Page 26 of 36 ADAV400 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAV400 can be set to accept or transmit data in 2-channel formats or in an 8- or 16-channel TDM stream. Data is processed in twos complement, MSB-first format. The left channel data field always precedes the right channel data field in the 2-channel streams. In the TDM modes, Slot 0 to Slot 3 (8-channel TDM) or Slot 0 to Slot 7 (16-channel TDM) fall in the first half of the audio frame, and Slot 4 to Slot 7 (or Slot 8 to Slot 15 in 16channel TDM) are in the second half of the frame. The serial modes are set in the serial output and serial input control registers. The input serial port is synchronized with the output serial port; in other words, BCLK1 and LRCLK1 are used for both. The output serial port can be programmed to be a master or slave port. The input control register allows control of clock polarity and data input modes. The valid data formats are I2S , left-justified, right-justified (24-/20-/18- or 16-bit), 8-channel and 16-channel TDM. In all modes, except for the right-justified modes, the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but they do truncate internally. Proper operation of the right-justified modes requires exactly 64 BCLKs per audio frame. The LRCLK in TDM mode can be input to the ADAV400 as either a 50/50 duty cycle clock or as a bit-wide pulse. In TDM mode, the ADAV400 is a master for 48 kHz and 96 kHz data, but not for 192 kHz data. LRCLK1 and BCLK1 are used as the left/right clock and bit clock, respectively, for the TDM stream. Apply input data for the TDM stream to SDIN0; TDM output data is available on SDO0. In 16-channel TDM mode, the ADCs and DACs cannot be used. Table 27 displays the modes in which the serial output port function. The output control registers give the user control of clock polarities, clock frequencies, clock types, and data format. In all modes, except for the right-justified modes (MSB delayed by 8, 12, or 16), the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but truncate internally. Proper operation of the right-justified modes requires the LSB to align with the edge of the LRCLK. The default settings of all serial port control registers correspond to 2-channel I2S mode. LRCLK1 and BCLK1 are clocks for the serial output port. All registers default to all 0s. All register settings apply to both master and slave modes, unless otherwise noted. Table 28 shows the proper configurations for standard audio data formats. Table 27. Serial Output Port Master/Slave Mode Capabilities fS 48 kHz 96 kHz 192 kHz 2-Channel Modes (I2S, Left-Justified, Right-Justified) Master and slave Master and slave Master and slave 8-Channel TDM Master and slave Master and slave Slave only 16-Channel TDM Slave only Slave only Slave only Table 28. Data Format Configurations Format I2S (Figure 32) Left-Justified (Figure 33) Right-Justified (Figure 34) TDM with Clock (Figure 35) TDM with Pulse (Figure 36) LRCLK Polarity Frame begins on falling edge Frame begins on rising edge Frame begins on rising edge Frame begins on falling edge Frame begins on rising edge LRCLK Type Clock Clock Clock Clock Pulse BCLK Polarity Data changes on falling edge Data changes on falling edge Data changes on falling edge Data changes on falling edge Data changes on falling edge MSB Position Delayed from LRCLK edge by one BCLK Aligned with LRCLK edge Delayed from LRCLK edge by 8, 12, or 16 BCLKs Delayed from start of word clock by one BCLK Delayed from start of word clock by one BCLK Rev. PrG | Page 27 of 36 ADAV400 Figure 35 shows just one of the formats in which the ADAV400 can operate in TDM mode. Refer to the Serial Data Input/Output Ports section for a more complete description of the modes of operation. LRCLK BCLK LEFT CHANNEL RIGHT CHANNEL 1 /FS Figure 32. I2S Mode--16 to 24 Bits per Channel LRCLK BCLK SDATA MSB LEFT CHANNEL LSB MSB 1 /FS RIGHT CHANNEL 05621-032 LSB Figure 33. Left-Justified Mode--16 to 24 Bits per Channel LRCLK BCLK SDATA MSB LEFT CHANNEL RIGHT CHANNEL 05621-031 SDATA MSB LSB MSB LSB LSB 1 /FS MSB LSB Figure 34. Right-Justified Mode--16 to 24 Bits per Channel LRCLK 256 BCLKs BCLK 32 BCLKs DATA SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 LRCLK 05621-034 BCLK MSB MSB-1 MSB-2 DATA Figure 35. 8-Channel TDM Mode LRCLK BCLK MSB TDM SDATA CH 0 MSB TDM 8TH CH 32 BCLKs Figure 36. TDM Mode with Pulse Word Clock Rev.PrG | Page 28 of 36 05621-035 SLOT 0 SDIN0L SLOT 1 SDIN0R SLOT 2 SDIN1L SLOT 3 SDIN1R SLOT 4 SDIN2L SLOT 5 SDIN2R SLOT 6 SDIN3L SLOT 7 SDIN3R 05621-033 ADAV400 CONTROL REGISTERS Table 29. Audio Register Map Register Address (Hex) 0x1052 0x1053 0x1054 0x1055 0x1056 0x1057 0x1058 0x1059 0x105A 0x110D 0x1113 Register Name Audio Core Control Register RAM Modulo Control Register Serial Output Control Register Serial Input Control Register SRC Serial Port Control Register ADC Input MUX Control Register Power Control Register User Control Register 1 User Control Register 2 DAC Amplifier Register Headphone Amplifier Register Register Width (Bits) 16 8 16 8 8 16 16 16 16 16 16 Table 30. Audio Core Control Register Register Address 0x1052 Default = 0x000 Register Bits Function 15 Reserved (Set to 0) 141 Enable SDO2 and SDO3 0 = enabled 1 = disabled 13 Indicates when Slew RAM is Muted (Read Only) 12 Equivalent to Writing 0s to the Target RAM 0 = normal operation 1 = RAM zeroed 11 Reserved (Set to 0) 10 LRCLK Used for Output Serial Data Transfer 0 = disabled 1 = enabled 9 Clears Internal Processor Registers (Active Low) 0 = registers cleared 1 = normal operation 8 Forces Multiplier Input to Zero 0 = normal operation 1 = force zero 7 Initializes Data RAM to Zero 0 = normal operation 1 = enabled Register Bits 6 Function Mute Serial Input Ports 0 = normal operation 1 = muted Initiate Safeload-to-Target/Slew RAM 0 = off 1 = on Initiate Safeload-to-Parameter RAM 0 = off 1 = on Determines the Input SPORT-to-Program Sequencer Ratio 00 = LRCLK 01 = LRCLK/2 10 = LRCLK/4 11= LRCLK/8 Program Length 00 = 2560 (48 kHz) 01 = 1280 (96 kHz digital IO only) 10 = 640 (192 kHz digital IO only) 11 = reserved 5 4 3:2 1:0 1 The polarity of this bit is inverted when read. Rev. PrG | Page 29 of 36 ADAV400 Table 31. RAM Modulo Control Register (8 Bits) Register Address 0x1053 Default = 0x28 Register Bits Function 7:6 Reserved (Set to 0) 5:0 Ram Modulo Size (1 LSB = 512 locations) Table 33. Serial Input Control Register (8 Bits) Register Address 0x1055 Default = 0x00 Register Bits Function 7:6 Reserved (Set to 0) 5 TDM Mode Function 0 = 8-channel TDM 1 = 16-channel TDM 4 LRCLK Polarity 0 = left low, right high 1 = left high, right low 3 BCLK Polarity 0 = data changes on falling edge 1 = data changes on rising edge 2:0 Serial Input Mode 000 = I2S 001 = left justified 010 = 8-channel TDM 011 = right justified, 24 bits 100 = right justified, 20 bits 101 = right justified, 18 bits 110 = right justified, 16 bits All others are reserved Table 32. Serial Output Control Register Register Address 0x1054 Default = 0x0000 Register Bits Function 15 Dither Enable 0 = disabled 1 = enabled 14 TDM Mode Function 0 = 8-channel TDM 1 = 16-channel TDM 13 LRCLK Polarity 0 = left low, right high 1 = left high, right low 12 BCLK Polarity 0 = data changes on falling edge 1 = data changes on rising edge 11 Master/Slave Mode Select 0 = slave 1 = master 10:9 BCLK Frequency (Master Mode) 00 = 3.072 MHz (48 kHz) 01 = 6.144 MHz (96 kHz digital IO only) 10 = 12.288 MHz (192 kHz digital IO only) 11 = reserved 8:7 LRCLK Frequency (Master Mode) 00 = 48 kHz 01 = 96 kHz 10 = 192 kHz 11 = reserved 6 Frame Sync Type 0 = LRCLK 1 = pulse 5 TDM Enable 0 = serial data out 1 = TDM out 4:2 MSB Position 000 = delay by 1 001 = delay by 0 010 = delay by 8 011 = delay by 12 100 = delay by 16 All others are reserved 1:0 Word Length 00 = 24 bits 01 = 20 bits 10 = 16 bits 11 = 16 bits Table 34. SRC Serial Port Control Register (8 Bits) Register Address 0x1056 Default = 0x00 Register Bits Function 7 Reserved (Set to 0) 6:5 SRC Serial Input Port Select 00 = SDIN3 01 = SDIN2 10 = SDIN1 11 = SDIN0 4 LRCLK Polarity 0 = left low, right high 1 = left high, right low 3 BCLK Polarity 0 = data changes on falling edge 1 = data changes on rising edge 2:0 Serial Input mode 000 = I2S 001 = left justified 010 = 8-channel TDM 011 = right justified, 24 bits 100 = right justified, 20 bits 101 = right justified, 18 bits 110 = right justified, 16 bits All others are reserved Rev.PrG | Page 30 of 36 ADAV400 SERIAL OUTPUT CONTROL REGISTERS Dither Enable (Bit 15) Setting this bit to 1 enables dither on the appropriate channels. this bit to 1 puts the part in 16-channel TDM input mode, input on SDIN0. LRCLK Polarity (Bit 4) When set to 0, the left channel data on the SDINx pins is clocked when LRCLK1 is low; and the right input data is clocked when LRCLK1 is high. When set to 1, this sequence is reversed. In TDM mode, when this bit is set to 0, data is clocked in starting with the next appropriate BCLK edge (set in Bit 3 of this register) following a falling edge on the LRCLK1 pin. When set to 1 and running in TDM mode, the input data is valid on the BCLK edge following a rising edge on the word clock (LRCLK1). The serial input port can also operate with a pulse input signal, rather than a clock. In this case, the first edge of the pulse is used by the ADAV400 to start the data frame. When this polarity bit is set to 0, use a low pulse; use a high pulse when the bit is set to 1. LRCLK Polarity (Bit 13) When set to 0, the left channel data is clocked when LRCLK is low, and the right data is clocked when LRCLK is high. When set to 1, this sequence is reversed. BCLK Polarity (Bit 12) This bit controls on which edge of the bit clock the output data is clocked. Data changes on the falling edge of BCLK1 when this bit is set to 0, and on the rising edge when this bit is set to 1. Master/Slave (Bit 11) This bit determines whether the output port is a clock master or slave. The default setting is slave; on power-up, Pin BCLK1 and Pin LRCLK1 are set as inputs until this bit is set to 1, at which time they become clock outputs. BCLK Polarity (Bit 3) This bit controls on which edge of the bit clock the input data changes, and on which edge it is clocked. Data changes on the falling edge of BCLK1 when this bit is set to 0, and on the rising edge when this bit is set at 1. BCLK Frequency (Bits[10:9]) When the output port is used as a clock master, these bits set the frequency of the output bit clock, which is divided down from the PLL. Frame Sync Frequency (Bits[8:7]) When the output port is used as a clock master, these bits set the frequency of the output word clock on the LRCLK1 pin, which is divided down from the PLL. Serial Input Mode (Bits[2:0]) These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4 of this control register override the settings in Bit 2 to Bit 0; therefore, all four bits must be changed together for proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high, then low, which is opposite from the default setting of Bit 4. When these bits are set to accept a TDM input, the ADAV400 data starts after the edge defined by Bit 4. Figure 35 shows an 8-channel TDM stream with a high-to-low triggered LRCLK and data changing on the falling edge of the BCLK. The ADAV400 expects the MSB of each data slot delayed by one BCLK from the beginning of the slot, just like in the stereo I2S format. In 8-channel TDM mode, the channels alternate with left and right channels starting with SDIN0 as shown in Figure 35. When in 16-channel TDM mode, the first half-frame holds Channel 0 to Channel 7, and the second half-frame has Channel 8 to Channel 15. Figure 36 shows an example of a TDM stream running with a pulse word clock used to interface to ADI codecs in their auxiliary mode. To work in this mode on either the input or output serial ports, the ADAV400 should be set to frame beginning on the rising edge of LRCLK, data changing on the falling edge of BCLK, and MSB position delayed from the start of the word clock by one BCLK. Table 28 explains the clock settings for each of these formats. Frame Sync Type (Bit 6) This bit sets the type of signal on the LRCLK1 pin. When set to 0, the signal is a word clock with a 50% duty cycle; when set to 1, the signal is a pulse with a duration of one bit clock at the beginning of the data frame. TDM Enable (Bit 5) Setting this bit to 1 changes the output port from multiple serial outputs to a single TDM output stream on the SDO0 pin. This bit must be set in both serial output control registers to enable 16-channel TDM on SDO0. MSB Position (Bits[4:2]) These three bits set the position of the MSB of the data with respect to the LRCLK edge. The data outputs of the ADAV400 are always MSB first. Output Word Length (Bits[1:0]) These bits set the word length of the output data-word. All bits following the LSB are set to 0. SERIAL INPUT CONTROL REGISTER 8-/16-Channel TDM Input (Bit 5) Setting this bit to 0 puts the ADAV400 into 8-channel TDM input mode, with the input stream coming in on SDIN0. Setting Rev. PrG | Page 31 of 36 ADAV400 Table 35. ADC Input MUX Control Register Register Address 0x1057 Default = 0x0001 Register Bits Function 15:4 Reserved (Set to 0) 3 AIN4 to ADC 2 AIN3 to ADC 1 AIN2 to ADC 0 AIN1 to ADC Table 38. User Control Register 1 Register Address 0x1059 Default = 0x0000 Register Bits Function 15:13 Reserved (Set to 0) 12:9 Reserved (Set to 0) These bits read back as 0b1111 8 SRC Mux Enable 0 = disabled 1 = enabled 7 (Read Only) Indicates SRC is Locked 0 = SRC not locked 1 = SRC locked 6 Enables MCLK Out Pin 0 = MCLKO pin disabled 1 = MCLKO pin enabled 5:3 MCLKO Select 000 = reserved 001 = ADC and DAC digital engine clock 010 = reserved 011 = reserved 1xx = ADC and DAC clock 2:1 PLL Clock Select 00 = 64 x fS (3.072 MHz) 01 = 128 x fS (6.144 MHz) 10 = 256 x fS (12.288 MHz) 11 = 512 x fS (24.576 MHz) 0 Enable PLL 0 = PLL bypassed 1 = PLL in use Table 36. Power Control Register Register Address 0x1058 Default = 0x0000 Register Bits Function 0 = Powered Down, 1 = Powered Up 15 PLL 14 Reference Buffer 13 ADC 12 VOUT4 DAC 11 VOUT3 DAC 10 VOUT2 DAC 9 VOUT1 DAC 8 AUX2 Right DAC 7 AUX2 Left DAC 6 AUX1/HP Right DAC 5 AUX1/HP Left DAC 4 Headphone Amplifier Right 3 Headphone Amplifier Left 2 SRC 1 Digital ADC and DAC Engine 0 Audio Processor Table 39. DAC Amplifier Register Table 37. User Control Register 2 Register Address 0x105A Default = 0x0000 Register Bits Function 15:8 Reserved (Set to 0) 7 Headphone Amplifier Mute 0 = Normal Operation 1 = Mute 6:5 Reserved (Set to 0) 4:0 Headphone Amplifier Attenuation 00000 = 0 dB 00001 = -1.5 dB 00010 = -3.0 dB 11110 = -45.0 dB 11111 = -46.5 dB Register Address 0x110D Default = 0x0000 Register Bits Function 15:5 Reserved (set to 0) 4 DAC Amplifier Chopping1 0 = enabled 1 = disabled 3:0 Reserved (set to 0) 1 Set this bit to 1 to obtain maximum performance from the DAC amplifier. Table 40. Headphone Amplifier Register Register Address 0x1113 Default = 0x0000 Register Bits Function 15:1 Reserved (set to 0) 0 Headphone Amplifier Chopping1 0 = enabled 1 = disabled 1 Set this bit to 1 to obtain maximum performance from the DAC amplifier. Rev.PrG | Page 32 of 36 ADAV400 TYPICAL APPLICATION DIAGRAM 3.3V 100nF 47F 100nF 47F 100nF 47F 100nF 600Z 47F 100nF 47F 10F + 100nF 3.3V FZT953 47F 47F 100nF 47F 100nF + + + + + + + + ODVDD 600Z VIN1L 47F + 20k 100nF AINL1 BCLK0 LRCLK0 VDRIVE AVDD2 AVDD3 AVDD1 AVDD4 AVDD5 DVDD 600Z VIN4R 47F + 20k 100nF SDIN0 AINR4 SDIN1 SDIN2 SDIN3 TO AUDIO CONTROLLER VOUTL 560 47F + VOUT1 BCLK1 LRCLK1 5.6nF 560 47F + VOUT4 VOUTR ADAU1421 ADAV400 SDO0 SDO1 5.6nF 20k IDAC AVDD2 DVDD RESET RESET CIRCUITRY CLOCK MCLKI 1nF 100nF 2k PLL_LF + VREF 100nF FILTA 100nF FILTD AGND AGND AGND AGND AGND 05621-036 SDA SCL AD0 I2C CONTROLLER 47F 47F + 100nF Figure 37. Typical Application Circuit Rev. PrG | Page 33 of 36 DGND DGND DGND DGND DGND DGND 47F + ADAV400 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 80 1 PIN 1 16.20 16.00 SQ 15.80 61 60 TOP VIEW (PINS DOWN) 14.20 14.00 SQ 13.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY 20 21 40 41 VIEW A VIEW A ROTATED 90 CCW 0.65 BSC LEAD PITCH 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 38. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters ORDERING GUIDE Model1 ADAV400KSTZ2 ADAV400KSTZ-REEL2 1 Temperature Range 0C to +70C 0C to +70C Package Description Low Profile Quad Flat Package [LQFP] Low Profile Quad Flat Package [LQFP] Package Option ST-80-2 ST-80-2 The ADAV400 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-mount soldering at up to 255C (5C). In addition, it is backward-compatible with conventional Sn/Pb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C. 2 Z = Pb-free part. Rev.PrG | Page 34 of 36 ADAV400 NOTES Rev. 0 | Page 35 of 36 ADAV400 NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05811-0-11/05(PrG) Rev.PrG | Page 36 of 36 |
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