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APPLICATION NOTE
STV0042 / STV0056
By Jean-Yves COUET
SUMMARY
1 2 3 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.5 4 4.1 4.2 4.3 4.4 5 6 7 7.1 7.2 7.3 7.4 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL BLOCK DIAGRAMS (Differences between STV0042 and STV0056) . . . . . APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIDEO PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FM DEMODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUDIO PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTHER FUNCTIONS, MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB LAYOUT RECOMMANDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIMPLIFIED VIDEO DE-EMPHASIS CHANNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J17 DE-EMPHASIS GENERATION WITH STV0042 . . . . . . . . . . . . . . . . . . . . . . . . . . . SIMPLIFIED AUDIO NOISE REDUCTION OR NO NOISE REDUCTION . . . . . . . . . . . AUDIO MONO APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TWIN TUNER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SATELLITE RECEIVER BUILT IN VCR OR TV SETS . . . . . . . . . . . . . . . . . . . . . . . . . TYPICAL APPLICATIONS DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STV0056 : 3 SCARTS PAL/EUROPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STV0042 : PAL/NTSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STV0042 : PAL M / BRAZIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STV0042 : AUDIO MONO APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POTENTIAL PROBLEMS AND SUGGESTED SOLUTIONS . . . . . . . . . . . . . . . . . . . . SOUND CRAKLING AND DISTORTED SIBILANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . AUDIO LEVEL WITH 50s DE-EMPHASIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOISY VIDEO SIGNAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22kHz TONE CROSSTALK ON VIDEEM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUDIO S/N, INFLUENCE OF THE VIDEO PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . STV0042 : AUDIO LEVEL MODULATION WHEN EVALUATING WITH SIGNAL GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIDEO OUTPUT, LIMITED SLEW-RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANNEXE : PLL DEMODULATOR THEORETICAL ANALYSIS . . . . . . . . . . . . . . . . . . .
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AN838/1095
STV0042/STV0056 APPLICATION NOTE
1 - INTRODUCTION The purpose of this application note is to provide the user with the most important informations relevant to the hardware and software environment of the STV0042 and the STV0056 circuits. In this introduction part, we would like to mention that the STV0042/STV0056 circuits features very specific FM demodulators, consequently we would advice to pay a specific attention to the relevant chapters. Conventions In this note, when the explanations are commun to both STV0042 and STV0056 circuits : the circuits are called STV42/56 and when pin numbers are given, they are relevant to the STV0056 (ex : Pin 15 means Pin 15 of STV0056 (corresponding to Pin 12 of STV0042)). When the explanations are relevant to only one circuit, the entire circuit reference is mentionned (ex : STV0042). When external components reference are given in this note, they are relevant to the STV0056 application circuit (page 31). When speaking about software : - R : stands for register - ex : R06 Register 06 - B : stands for bit - ex : R06 B1 Register 06 Bit1 Other conventions : - R05 B0-5 Register 05 from Bit 0 to Bit 5 - R06 B2 B4 Register 05 Bit 2 and Bit 4 - R05 B0-5 = 35 ; it means no attention is paid to Bit 6 and Bit 7. 35 is the hexadecimal value given by the 5 first bits.
2 - GENERAL BLOCK DIAGRAMS (differences between STV0042 and STV0056) The general block diagram of the STV0042 and STV0056 circuits are given in Figure 1 and 2 respectively. Figure 1 : STV0042 General Block Diagram
From Tuner
B-BAND 2 Video Processing 2
4x2 Video Matrix
2
From VCR/Decoder From Tuner
1 FM Demodulation 2 Channels Noise Reduction + Deemphasis To TV, VCR/Decoder Audio Matrix + Volume
2
22kHz to LNB
I2C Bus Interface
STV0042
Active in Stand-by
2/37
AN838-01.EPS
STV0042/STV0056 APPLICATION NOTE
2 - GENERAL BLOCK DIAGRAMS (differences between STV0042 and STV0056) (continued) Figure 2 : STV0056 General Block Diagram
From Tuner
B-BAND 2 Video Processing 4
6x3 Video Matrix
3
From TV, VCR/Decoder From Tuner
2 FM Demodulation 2 Channels Noise Reduction + Deemphasis To TV, VCR/Decoder Audio Matrix + Volume
3
22kHz to LNB
I2C Bus Interface
STV0056
Both circuits contain the following main functions : Video : - a baseband video processing block, - a video switching matrix, Audio : - 2 independant FM demodulators, - an audio processing part containing (audio deemphasis, noise reduction), - an audio switching matrix with a volume control output, Differences between STV0042 and STV0056 STV0042 Video Clamped Video Inputs 2 Clamped Video Outputs 2 Audio Audio De-emphasis 50/75s Audio Noise Reduction L+ R Auxillary Inputs 1 Auxillary Outputs 1 Others I2C Addresses 06 Digital I/O No 22kHz Tone Generator Pin 13
Active in Stand-by
Others : - an I2C bus decoder,
- a 22kHz tone generator for LNB control. When the circuit is in stand-by (R4 B3 = high), all the functions are turned-off except for the I2C bus interface and the audio and video matrix. With such a configuration, it is still possible to allow signals to go through the satellite receiver while having a lower power consumption.
STV0056 4 3 50/75s and J17 Panda 2 2 06 or 46 1 Pin 16 or/and Pin 29
Comments See Note 1 See Note 2
See Note 3
Notes : 1. One of STV0056 video output feature a DC level output (black level adjust) 2. With the STV0042 the input signal which is used to control the noise reduction circuit is (L + R). With the STV0056, there are 2 independants noise reduction circuits, one for left, one for right. 3. With the STV0056, the I2C bus address can be selected by connecting the HA pin either to VDD or to GND.
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AN838-02.EPS
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES 3.1 - Video Processing Figure 3 and Figure 4 respectively give the architecture of the video processing part of the STV0042 and STV0056 circuits. Figure 3 : STV0042 Video Processing Block Diagram
LPF NTSC PAL VIDEEM2/22kHz
13
VIDEEM1
15
UNCL DEEM
12
22kHz TONE /2 B-BAND IN 17 G 1 Baseband CLAMP IN
10
Deemphasized
CLAMP CLAMP
Normal VCR / Decoder Return
+6dB
S2 VID RTN
8
+6dB
6
5
S2 VID OUT To Decoder or VCR
S1 VID OUT To TV
Figure 4 : STV0056 Video Processing Block Diagram
LPF NTSC PAL VIDEEM2/22kHz
16
VIDEEM1
18
UNCL DEEM
15
I/O/22kHz 29 22kHz TONE
/2
Deemphasized
B-BAND IN 20
G
1 Baseband
CLAMP IN
13
CLAMP CLAMP CLAMP CLAMP
Normal Decoder Return VCR Return TV Return
+6dB +6dB +6dB
S3 VID RTN S2 VID RTN S1 VID RTN
5
11
4
BLACK LEVEL ADJUST
STV0056
S3 VID OUT To Decoder
7 S1 VID OUT
8
9
S2 VID OUT To VCR To TV
Basically those block diagrams contain two mains parts : the baseband video processing an a switching matrix.
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AN838-04.EPS
AN838-03.EPS
STV0042
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.1.1 - Breaking down the Baseband Video Processing Function 3.1.1.1 - Input Stage This wide band input stage has a programmable gain (R1 B0-5). The gain value is selected to get a 1VPP signal at the output (loaded with 75). Taking into account all the different gains of the video channel (externbal and internal buffers, low pass filters), it corresponds to a 0.4VPP signal at the input of the de-emphasis amplifier (synchro top to peak white (not taking into account the pre-emphasis spikes)).
G Input Stage = 0.4 VPP VTW
Comparing (1) and (3)
f2 R9 =1+ f1 R and f1 =
(4)
VT-W : the synchro top to peak white amplitude of the signal delivered by the tuner. 3.1.1.2 - Video Polarity Inverter To comply with both positive video (Ku bands) and negative video (C-band) ; a programmable inverter is implemented in the STV42/56 to recover good video phase. 3.1.1.3 - Video De-emphasis + External Low Pass Filter The video de-emphasis function is realized with a non-inverting amplifier (see Figure 5). Dimensionning the External Components The required video de-emphasis law is :
f f2 F=K f 1+ f1 1+ f : frequency (1)
in 625 lines systems : f2 = 1.56MHz, f1 = 312kHz in 525 lines systems : f2 = 0.875MHz, f 1 =187kHz The AC gain of the structure can be calculated as follow :
GAC = 1 + z2 R9 =1+ z1 R (R 9 C12 p + 1) (2)
1 (5) 2 R9 C12 Additionnaly the DC output voltage of the de-emphasis amplifier is choosen in the range of 3.5 to 4.0V. This range offers two advantages : - limits the current consumption when hybrid type of low pass filters are choosen, as suggested in our typical application diagrams (TDK SEL 5618 filter) VOUT DC IOUT DC = R15 + R16 - When the low pass filter is built with discrete components (L and C), there is generally the need for a group delay compensation circuit (see Figure 5) which implements a transistor Q. In such a case, to offer the widest swing, the voltage at the emitter VE should be : VDD 3V, VE (VOUT DC - 0.7V) VE 4 The DC output voltage of the de-emphasis amplifier is : R9 3.7V (6) VOUT DC = VIN DC 1 + R10 with VIN DC = 2.45V Using relations (4), (5), (6), it is possible to determine all the component values. - 625 lines systems : (VIDEEM1 Pin) R9 = 5.1k (choosen value) C12 = 100pF, R10 = 10k, R11 = 1.5k, C13 10F - 525 lines systems (see the PAL/NTSC typical application diagram, Pin VIDEEM2) R14 = 5.6k (choosen value) C14 = 100pF, R13 = 10k, R12 = 1.5k, C15 10F Remark : In order not to be to sensitive to potential crosstalk with the 22kHz tone signal which can be generated from Pin VIDEEM2/22kHz, it is possible to lower the impedance of the de-emphasis network ; for exemple by choosing R9 2.2k. In this case, it is required to add a resistor ( 2.7k) between the UNCL.DEEM Pin and ground. With R9 < 2.2k, the power consumption of the de-emphasis amplifier becomes important.
p : Laplace operator (p : j2f in the frequency field) R : R11//R10 |1/C2p| << R11 for video frequencies With some calculations, the relation (2) can be presented with the same shape as (1) :
R9 C12 p 1+ R9 ) (1+ R9 R ) = GAC (2) ( 1 + R ( R 9 C12 p + 1 )
(3)
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STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 5 : Video De-emphasis Amplifier
12V ( VDD) VC
Option
Q
VCE
Z1 R11 R10 C13
Z2 C12
VE
R9
R15 LPF To Clamping Stage R16
AN838-05.EPS
VIDEEM1
UNCL DEEM
B-BAND
3.1.2 - Breaking down the Video Matrix Section 3.1.2.1 - Clamp Stage All the video inputs of the video matrix feature the same clamp stage. The purposeof the clamp stage is to reject the energy dispersal ramp and to ensure a stable DC level at all video outputs (easier interface with decoder or text insertion circuits). The coupling capacitor value is only critical for the rejection of the energy dispersal ramp (C11 in the application diagram). The principle of the clamp stage is : DC alignment of the synchronization top bottom level. The coupling capacitor C11 is charged with a high current I2 when the input level is lower than 2.7V and is permanently discharged by a small I1 current (see Figure 6). Dimensionning the Coupling Capacitor C11 C11 is dimensionned for the largest ramp amplitude AR which can be measured at the output of the low pass filter :
AR max. = A G GDEEM 2
To reject the Slope : The I1 current must produce a negative ramp in C11 which compensate the positive ramp of the energy dispersal sawtooth :
C 11 I1 Min. T Max. (1)
Additionnaly the I2 current of the circuit is choosen to produces enough charge during the synchro pulse of the negative slopes of the energy dispersal ramp.
I2 Min. C 11 + I1 T TS (2)
Results : For a worst case of a 4MHz pp ramp added to a 16MHz/V channel
ARMax. = 1.25VPP Max. = 4.0mV
A : amplitude of the ramp at the tuner output G : gain of the input stage GDEEM : gain of the de-emphasis amplifier (at 25 or 30Hz) This worst case of the ramp produces a positive or negative voltage offset at each line :
= 6/37 ARmax. ARmax. (625 lines) or = (525 lines) 312.5 262.5
0.5A , C11 8.2nF 4mV (2) Required I2 Min. > 28A, Actual I2 Min. = 40A (specification of STV42/56) Remarks : - It is important not to use a too small C11 value. A low C11 value would induce a degradation of the TILT parameter (parasitic slope on the clamped video). Additionnaly, in case of built-in Videocrypt receiver, a parasitic slope would produce a voltage offset at the "cut and rotate" point. - For a good operation, the DC impedance of point A (see Figure 6) must be as low as possible. (1) C11
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 6 : Video Input Clamp Function
o Vide Filtered Unclamped Video A C11 I1 2.7V I CH = I 2 - I 1 during Ts during T - Ts I CH = - I 1
I2 Ts
AN838-06.EPS
T
3.1.2.2 - Switching Matrix This switching matrix is simply an array of CMOS switches which is driven by registers. All configurations are possible. Any output can be connected to any input. An input can be connected to several outputs. 3.1.2.3 - Output Stages Each video output has a 6dB output gain, and the internal final stage is a emitter follower structure pulled down with a 1.3mA current source. The output voltage amplitude is 2VPP, and the synchro bottom level is clamped at 1.3V typically. In the application, an external current amplifier (75 driver) is required. Remarks : - The S3VIDOUT of the STV0056 features a black level adjust (corresponding to a DC level adjust). This function may be used to more simply interface with built-in Videocrypt decoder. - When the high 2 low power mode is selected, the output impedance becomes high ( 23k typ.), and the DC output levels drops to low values (< 0.2V) consequently the external 75 driver is also turned (power saving). 3.2 - FM Demodulation 3.2.1 - Hardware Description This chapter is relevant to : - the input filter, - a study of the FM demodulatorwhich is integrated in the STV42/56 circuits (including the external components needed at Pins DET L/R, AMPLOCK L/R, CPUMP L/R, AGC L/R). 3.2.1.1 - Input Filter (C25, R18, R17, L4, C24, C23) The FM demodulator integrated in the STV42/56 circuit havea goodrejection of the video signal (due to the selective AGC stage see paragraph 3.2.1.2). However, to get a good audio signal to noise ratio, it is preferable to attenuate the video signal spec-
trum with an input filter. The filter proposed in the typical application (see Figure 7) contains a high pass cell (C25, R18, fC 1.5MHz) and a chroma trap (R17, L4, C24). C23 is required for capacitive coupling with the FM IN Pin (C23 value is not critical). The center frequency of the chroma trap is about 4.4MHz for PAL/SECAM application and 3.58MHz in case of NTSC application (Remark : In case of PAL/NTSC application, a double trap may be required.) It is recommanded to directly connect the input filter to the tuner baseband output,because at this stage the video signal is still emphazed (giving a natural 14dB attenuation of the lower part of the video spectrum where most of the energy is concentrated. 3.2.1.2 - FM Demodulators The block diagram of the FM demodulation part is given in Figure 8. This block diagram contains 2 independants FM demodulators able to process all types of mono and stereo sound, including : - mono signals with deviation from 30kHz up to 400kHz (remark the spec mentions : 19.5kHz to 592kHz, in order to cover all possible dispersions). - Stereo pair featuring a frequency spacing different from 180kHz (between left and right sub-carriers). Each FM demodulator section contains 2 parts : - an automatically gain controlled input stage - a PLL demodulator The only common point to both FM demodulators is the frequency synthesis circuit : SYNTHESIZER. The structure of the FM demodulators which is different from conventional solutions have been selected for the two following reasons : - no need for costly selective filters(LC or ceramic), - to have a variable bandwidth (to accomodate all type of deviations).
7/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 7 : FM Demodulation, Video Signal Rejection Filter
C25 TUNER R18 R17 C23 To FM IN L4 C24
AN838-07.EPS / AN838-07.TIF
Figure 8 : FM Demodulation Block Diagram
SW1 FM IN AGC LEVEL DETECTOR 1 AGC R LEVEL DETECTOR 2 AMPLK R
SD
Phase Detect
DET R AUDIO R FM dev. Select. A V REF CPUMP R
Bias
Amp. Detect 90 VCO 0 WATCHDOG V REF Reg8 b4 L AUDIO L SW3 AGC LEVEL DETECTOR 1 Phase Detect SW4 DET L R SW5 SYNTHESIZER SW2
RIGHT DEMODULATOR LEFT DEMODULATOR
Bias
FM dev. Select. A CPUMP L
AGC L LEVEL DETECTOR 2 AMPLK L
SD
V REF Amp. Detect 90 VCO 0 WATCHDOG
AN838-08.EPS
V REF
Reg8 b0 AGC STAGE PLL DEMODULATOR
STV0042/STV0056
8/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) a) Principle of the FM Demodulators To properly operate the FM demodulators require to go through different operating modes before to produce the demodulated signal. The required sequence is described in the software part (Section 3.2.2.1). Because there is no selective filter (LC or ceramic) which sets the operating frequency (ex : 10.7MHz), the demodulation of the STV42/56 circuit directly o p e ra t e s a t t h e s u bc a rrie r f re q u en cy (ex : fVCO = 7.02MHz when demodulating the 7.02MHz subcarrier). This first point explains why each VCO can be driven by the Synthesizer. - SW2 closed and SW5 to R to drive the right VCO - SW4 closed and SW5 to L to drive the left VCO During the Demodulation : When the FM demodulator is in demodulation, it operates like any PLL demodulator and its block diagram can be simplified (as Figure 9). Figure 9
Phase Detector VIN (from AGC stage) KD VCO Ko K Loop Filter F(p) Vo (to audio processor)
AN838-09.EPS
- In the satellite receiver applications it is asked to have a required audio level for a full deviation signal (ex : 1VRMS on the scart output at full deviation). Refering to relation (2), it means that the K KO products must remain constant for all deviations. Consequently to compensate the dispersion of the VCO slope KO, the STV42/56 FM deviation selection table offers many steps, so that there is always a selection which guarantees : K KO = constant small dispersion The method to select the optimum K factor is described in Section 3.2.2.3 - Additionnally, in relation (1), it can be noticed that a constant (K KO) product gives a more stable lock range. b) Breaking Down the PLL Demodulator Section (explanation for left channel and refered to Fig. 8) - Phase Detector : This part converts the phase difference between the wanted subcarrier and the VCO signal (with 90 phase log) into a current IPD. In the calculation KD is given in Volt per Radians, because a current to voltage conversion is done by the resistor R33 connectedbetween Pin DET and VREF. - The Loop Filter : It is made of external components connected between DET Pin and VREF. - The VCO : The voltage controlled oscillator typically has a 460kHz/volt slope. It is driven by the SYNTHESIZER during the frequency synthesis sequence and by the demodulated signal during the demodulation. The VCO part features a first output with 90 phase lag compared with the subcarrier, this output is used for phase detection ; the second output is in phase with the subcarrier and is used for synchronous amplitude detection (see AGC stage). - The Watchdog : It is used to measure the VCO frequency. This function is used to check if the VCO frequency has reached the wanted subcarrier frequency during the frequency synthesis. This operation is also usefull to monitor the VCO frequency during demodulation (preventing it from shifting away when operating under abnormal conditions). The watchdog is a 1/1000 divider (clocked by a 10kHz reference frequency) consequently its averages the VCO frequency over a 100ms period (equivalent to 10Hz) ; this long period makes the results independant from the audio modulating signal.
9/37
F(p) : the transfert function of the external loop filter which is connected at DET Pin. KD : the phase detector gain (in V/radians). KO : slope of the voltage controlled oscillator (VCO) in (radians/volts or Hz/volts). K : is a programmable coefficient related to the register 05 bits 0 to 5. In Annex 1 a more detailed study of this PLL structure is provided. Out of this detailed study the key results are : KO : 460kHz/V 2.89 10 radians/V (typ.) R33 KD DETH (for left channel) (0) R36 DETH is a parameter given in the specification. Lock range = L = KO K KD VO PP 1 DC gain = = (deviation PP K KO ) (1) (2)
6
Remarks about those relations : - The relations (1) shows that a programmable K coefficient corresponds to a programmable bandwidth (FM deviation selection, table in Page 26 of the specification dated June 1995).
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) - FM Deviation Selection : This part is a programmable attenuator driven by R5 B0-5. - SW3-SW4-SW5 : Those switches are used to drive the VCO either by the Synthesizer or by the wanted subcarrier. During the synthesis SW4 is closed, SW5 is set to L, and SW3 is connected to bias (in order not to have parasitic drives coming from the phase detector). Those switches are driven by the R06 B2 B4 (left), R06 B2 B5 (right). - Amplifier A and CPUMP Pin : During the demodulation, the DC voltage corresponding to the VCO center frequency is memorized in a large capacitor (about 10F) connected at CPUMP Pins. To prevent the VCO from slow frequency shifts which could be generated by current leakages, the PLL demodulator has a DC loop which is closed by a voltage to current amplifier A. The output current capability of this amplifier is low (max. 2A) in order not to disturb the AC operation of the amplifier. c) Why an AGC Input Stage When no selective filter (LC or ceramic) is used, the sum of all the subcarriers is input in the phase detector of the PLL demodulator. Consequently a linear type of phase detector is necessary (to avoid intermodulations); but this type of phase detector features a gain which is proportionnal to the amplitude (As) of the subcarrier to be demodulated. KD = As (3) Refering to the relation (1), the lock range of the PLL demodulator : L = KO K KD = KO K As Consequently in order to have a stable lock range, it is important to maintain a constant amplitude of the wanted subcarrier ; then an automatically gain controlled stage is required. d) Breaking Down the AGC Stage - The AGC amplifier is controlled by two level detectors, and offers a 40dB gain range. - The first control loop built with the AGC stage and the level detector 1, is always active (during the synthesis and the demodulation). This loop guarantees that the amplitude (As) of the wanted subcarrier does not take too small or too high values. In doing so, the first capture is easier when starting to demodulate. - The second loop made of : the amplitude detector, level detector 2 and the AGC stage, is active only during demodulation (SW3 connected to AGC amplifier). When operating, thanks to the higher current capability of level detector 2, the second loop controls the AGC amplifier. After the PLL capture, the amplitude detector receives all the subcarriers on one input and the VCO signal at the other input. Due to the PLL the VCO signal is synchronous with the wanted subcarrier ; consequently the average DC signal which can be measured at AMPLOCK Pin only depends on the amplitude of the wanted subcarrier (regardless the amplitude and the number of the other subcarriers). Finally with this second loop the amplitude of the wanted subcarrier is constant at the input of the phase detector. An external RD filter is used on the AMPLOCK Pin to reject all the AC components of the amplitude detector output signal. - SD comparator : This Subcarrier Detector comparator switches to high when the AMPLOCK voltage exceeds a fixed threshold. In doing so it detects wether a subcarrier is present at the wanted frequency. e) Synthesizer This function is shared between both FM demodulators.For this reason, when demodulating a stereo pair, two successive frequency synthesis sequences are required. The synthesizer used a conventional PLL solution, in which the VCO signal frequency is divided by a programmable N factor, and the frequency divided signal is compared in phase with a precise frequency reference (10kHz) derived from the crystal oscillator). The output of the phase detector is a current which charges or discharges the external CPUMP capacitor, so that the VCO frequency converges to the required frequency. The average charge current (when fVCO is quite different from the wanted frequency) is about 60A. Consequently the tuning speed is about fVCO 10.5MHz/second (C41 = 10F) t Important Remark : Due to its loop gain the frequency synthesizer has a 10kHz accuracy.
10/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) f) Dimensioning the External Components (DET, AMPLOCK, AGC, CPUMP Pins) Example : Left channel (see Figure 10). Figure 10 : Left Channel, FM Demodulator External Components The most severe case is : "narrow band stereo pair" when simultaneously are required a good quality sound and a precise control of the capture range (due to the low frequency spacing : 180kHz (80kHz dynamically)). Figure 11 : Stereo Pair, Frequency Spacing and Coverage
AGC
AMPLOCK
DET
CPUMP
C43 C38 R36 C49 R33 R32 V REF C37
C41
50k
50k
80k
50k
50k
FSB L
AN838-10.EPS
FSB R
- AMPLOCK, AGC Pins : Due to the AGC loop, the amplitude As of the wanted subcarrier at the phase detector input is inversely proportionnal to the external resistor connected to AMPPLOCK. 11k (As)PP DETH R36 In order to maintain the phase detector in a linear operation (even in case of a high number of subcarrier : 10 subcarriers), we recommand (As) not to exeed 0.25VPP. For R36 = 560k, AsPP 0.19 VPP. The C49 capacitor associated with R36 realizes a filter which rejects all the AC components. For a good operation, the roll-off frequency of this filter is lower than the audio spectrum for C49 = 100nF, fC 2.8MHz. The value of the AGC capacitor C43 is not very critical, 100nF has been selected for component standardization. However it is recommanded to have C43 < 1F for a good stability of the loop. - CPUMP Pin : Choosing the CPUMP capacitor value results from a compromisze. The smaller is CPUMP the shorter is the duration of the frequency synthesis, but a too small value of CPUMP induces a too fast response of the DC compensating loop (risk of distorsion in the low frequency audio signals). C41 = 10F is a good compromise. - DET Pins : following is a simplified method to calculate the components.
Theoretical request : L > 50kHz, C < 80kHz. Actually a more severe compromise is required. - L > 70kHz. A first margin is required to compensate the phase lag which appears in case of high frequency slew rates (case of audio sibilance). In practice, a further margin is given to compensate the dispersion of the phase detector gain, eventually : 90kHz L typ. 100kHz - C will be choosen as low as possible to also compensate potential level imbalance between left and right subcarriers (2 to 3dB max. could be measured on some broadcasted channels). The STV42/56 circuits have been optimized to get a 1VPP at the DET Pin (full deviation). Refering to realation (2) :
K KO = 100kHz PP = 100kHz/V 1VPP L 1V/rd K KO
choosing L = 100kHz in (1) :
KD =
using relation (0) :
R33 = KD R36 180k, DETH DETH = 3.1V, R 36 = 560k
To calculate the other components C37, R32 , would lead to complex mathematics. A first estimate can be done using the relations given in Annex 1. Some experiments and calculations have given R32 = 82k and C37 = 22pF, corresponding capture range is about 52kHz. An additionnal capacitor C38 is recommanded to give a further reduction to the capture range (C38 15 to 22pF).
11/37
AN838-11.EPS
180k
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.2.2 - Software Description To properly use the FM demodulators of the STV42/56, specific software routines need to be implemented. This section describes three software routines : - FM demodulation, - PLL monitoring, - PLL gain auto calibration. Remark : In this section some solutions are given, but the software engineer may improve them for his application. 3.2.2.1 - FM Demodulation Software Routine As far as the FM demodulation is concerned, there are two main cases : mono and stereo pair. In case of mono subcarriers, it is suggested to have both left and right demodulators demodulating the same wanted sub-carrier (in doing so, signals can be surely provided to the decoders). In case of stereo pair, naturally the two demodulators work on different subcarriers. Description (Flow Chart in Figure 12) With the STV0042/STV0056 circuits, for each channel, three steps are required to acheive a FM demodulation : - 1st step :To set the demodulation parameters : * A : FM deviation selection, * B : Subcarrier frequency selection. - 2nd step : To implement a waiting loop to check the actual VCO frequency. - 3rd step :To close the demodulation phase locked loop (PLL). Refering to the FM demodulation block diagram (see Figure 8), the frequency synthesis block is common to both channels (left and right) ; consequently two complete sequences have to be done one after the other when demodulating stereo pairs. For clarity, the explanations are based on the followin g e xample : s te re o p air 7 . 02MHz /L 7.20MHz/R, deviation 50kHz max. 1st Step (left) : SETTING THE DEMODULATION PARAMETERS A. The FM deviation is selected by loading R5 with the appropriate value (see Table 1). Table 1 : Register 5 (FM Deviation Selection)
43210 00000 00001 00010 Selected Nominal Carrier Modulation Bit 5 = 0 Do not use Do not use Do not use Bit 5 = 1 cal : do not use = 0.3373V offset on VCO cal : do not use = 0.3053V offset on VCO cal : do not use = 0.2763V offset on VCO calibration setting (1V offset on VCO) 296kHz modulation 267kHz modulation 242kHz 218kHz 198kHz 179kHz 161kHz 146kHz 133kHz 120kHz 109kHz 98.3kHz 89.7kHz 80.9kHz 73.1kHz 66.0kHz 60.0kHz 54.4kHz = default power up state 49.1kHz 44.3kHz 39.8kHz 35.9kHz 32.4kHz 29.1kHz 26.7kHz 24.3kHz 21.9kHz 19.7kHz
0 0 0 1 1 Cal. set. (2V) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 592kHz 534kHz 484kHz 436kHz 396kHz 358kHz 322kHz 292kHz 266kHz 240kHz 218kHz 196kHz 179kHz 161kHz 146kHz 122kHz 120kHz 109kHz 98kHz 89kHz 78kHz 71kHz 65kHz 58kHz 53kHz 48.6kHz 43.8kHz 39.6kHz
Corresponding bandwidth can be calculated as follows : Bw 2 (FM deviation + audio bandwidth) Bw 2 (value given in table + audio bandwidth) In the example : 50kHz R5 Bits 7 6 5 4 3 2 1 0 XX110110
12/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) B. The subcarrier frequency is selected by launching a frequencysynthesis (the VCO is driven to the wanted frequency). This operation requires two actions : - To connect the VCO to the frequency synthesis loop. Refering to the FM demodulator block diagram (see Figure 8) : * SW4 closed R6 B2 = H * SW3 to bias R6 B4 = L * SW2 to bias R6 B3 = L * SW1 opened R6 B5 = L - To load R7 and R6 B6 B7 with the value corresponding to the left channel frequency. This 10 bits value is calculated as follows : Subcarrier frequency = coded value x 10kHz (10kHz is the minimum step of the frequency synthesis function) Considering that the tunning range is comprised between 5 to 10MHz, the coded value is a number between 500 and 1000 (210 = 1024) then 10 bits are required. Example : 7.02MHz = 702 x 10kHz 702 1010 1111 10 AF + 10 R7 is loaded with AF and R6 B6 : L, R6 B7 : H. The Table 2 gives the setting for the most common subcarrier frequencies. 2nd Step (left) : VCO Frequency Checking (VCO) This second step is actually a waiting loop in which the actual running frequency of the VCO is measured. To exit of this loop is allowed when : Subcarrier Frequency - 20kHz Measured Frequency Subcarrier Frequency + 20kHz ( 10kHz is the maximum dispersion of the frequency synthesis function). In practice, R8 B2 B3 and R9 are read and compared to the value loaded in R6 B6 B7 and R7 2 bits. 3rd Step (left) The FM demodulationcan bestarted by connecting the VCO to the phase locked loop (PLL). In practice : - SW3 closed R6 B4 = H - SW4 opened R6 B2 = L After this sequence of 3 steps for left channel, a similar sequence is needed for the right channel.
Note : In the sequence for the right, there is no need to again select the FM deviation (once is enough for the pair). General Remark Before to enable the demodulated signal to the audio output, it is recommanded to keep the audio muting and to check whether a subcarrier is present at the wanted frequency. Such an information is available in R8 B0 and R8 B4 which can be read.
Table 2 : Frequency Synthesis Register Setting for the Most Common Subcarrier Frequencies
Subcarrier Frequency (MHz) 5.58 5.76 5.8 5.94 6.2 6.3 6.4 6.48 6.5 6.6 6.65 6.8 6.85 7.02 7.20 7.25 7.38 7.56 7.74 7.85 7.92 8.2 8.65 Register 7 (Hex) 8B 90 91 94 9B 9D A0 A2 A2 A5 A6 AA AB AF B4 B5 B8 BD C1 C4 C6 CD D8 Register 6 Bit 7 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1
13/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 12 : FM Demodulation Software routine Flow Chart
Start Mute Audio Output Relevant STV42/56 (W : Write, R : Read) W Reg 00
Select FM Deviation B 1st Step Lauch Frequency Synthesis (left)
W
Reg 05 B0-5
W W
Reg 07 Reg 06 B2 B4 + Reg 06 B6-7
Watchdog (left)
R
Reg 09 + Reg 08 B2-3
2nd Step
Note 3
fsb - 20kHz < fVCO < fsb + 20kHz Yes
No
3rd Step
Demodulation Start (PLL connected to AGC stage) Lauch Frequency Synthesis (Right) Wait for tAL 100ms
R
Reg 06 B2 B4
R
Reg 07 + Reg 03 B3 B5 + Reg 06 B6-7
Note 1
Left Subcarrier Presence
No
R
Reg 08 B0
Note 4 C
Yes
A Note 2
Watchdog (right)
R
Reg 0A + Reg 08 B6-7
Note 3
fsb - 20kHz < fVCO < fsb + 20kHz Yes
No
Demodulation Start (PLL connected to AGC stage) Wait for tAL 100ms
W
Reg 06 B3 B5
Note 1
Right Subcarrier Presence
No
R
Reg 08 B4
Note 4 E
Yes
D Note 2
AN838-12.EPS
Stop Muting End
W
Reg 00
Notes : 1. tAL must be longer than the setting time of the voltage at AMPLOCK Pins. tAL can be reduced by decreasing the AMPLOCK capacitor. 2. In points A and D different strategies may be adopted (up to the software engineer). Suggestion : to return to B point and to have a second trial. If this second trial is not successfull, to run till end ; in this case a randoom noise is output and the end user is warned about the subcarrier "abscence". 3. The frequency synthesis has a 10kHz accuracy. But in order to give some more margin 20kHz tolerance may be used (this tolerance remains lower than the capture range of the PLL). 4. In point C, two different strategies may be adapted : - either to keep muted the output till the MCU runs till E point, - or to output the left sound on both outputs untill the MCU runs to E point, and real stereo sound is output after E point.
14/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.2.2.2 - PPL Monitoring Software Routine During the demodulation, the VCO is locked on the wouted subcarrier frequency. If for any reason the subcarrier desappears (signal drop out, unreliable cable connection to the parabola ...) the VCO is no larger locked on a fixed frequency, it may drift away and may lock on unwanted subcarriers when the RF signal appears again. To prevent the application from tese problems, it is recommanded to implement PLL monitoring routine. Description To regularly and permanently check the VCO frequency (using) the watchdog). The sampling period may be in the range of 200ms to 500ms. When an error is detected, the demodulation is not imediatly stopped but an error counter is initialized. If at the next sampling of the watchdog, there is a new error, the error counter is incremented. The demodulation is stopped when the error counter reaches a fixed value (for instance 4 or 5). If one sampling of the watchdog gives a good esult before the error counter reaches the limit, the error counter is reset. Flow Chart This function has no real start sequence, because it permanently operates (see Figure 13). In Point A, it is suggestedto restart the FM demodulation sequence. Figure 13 : PLL Monitoring Routine : Flow Chart 3.2.2.3 - PLL Calibration Function a - Reason for the Calibration Inorderto havea goodand stablequalityof the sound, it is important to precisely control the PLL bandwidth (stable lock and capture ranges of the PLL). Refering to the general theory of the PLLs, the lock range can be calculated as following (also valid for the STV42/56 circuits) :
L = KO K KD (1)
where : KO : the VCO slope (in rd/V or kHz/V), KD : the phase detector gain ( in V per Rd), K : a constant (in the case of STV42/56, this parameter is programmable in order to accomodate different FM deviations : Reg 5 B0-5). In the case of the STV42/56, most of the dispersions come from the KO (VCO slope), in theory dispersions as high as 30 to 40% could be expected. In order to compensate this problems the STV42/56 circuits feature many PLL gain positions (K factor). In order to find the optimum K factor (Reg 5 B0-5) there are two methods : a.1 - To implement a test in the assembly line This test can be described as following : - A full deviation FM signal is input to the STV42/56 circuit. - The STV42/56 is set to demodulation. - The peak-to-peak signal is measured on the DET Pins or on the scart outputs (in this later case no de-emphasisand no noise reduction are preferable). - Then with either an automatic system or with the help of an operator, the optimum K parameter is selected to get a 1VPP signal on the DET Pins or 2VPP at the scart outputs. - The result of this test is memorized in the EEPROM of the receiver (remark : to save time the test can be done for only one deviation and its result can be used for all deviations accomodated by the receiver). a.2 - To use the auto-calibration function of the STV42/56 circuits This second method will actually be a software routine which is embeded in the microcontroller software. This second method has two advantages : - no need for test in the assembly line (time saving, equipment saving), - the receiver can auto-calibrate during its life, then compensating drifts related to time and temperature.
15/37
Wait for sampling period Reset Error Counter
Watchdog
Yes fS - 20kHz < fVCO < fS + 20kHz ? No Error Counter Error Counter + 1
Error Couter = Max.?
AN838-13.EPS
No Yes A
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) b - Principle of the Auto-calibration Function (see Figures 14 and 15) The purpose of the auto-calibration function is to automatically measure the slope of the VCO of the PLL. This can be done with the STV42/56 circuits when using the following software routine : 1st step : To implement a synthesis to bring the 4th step : After a well known delay, the new VCO t o a known freque ncy (Fo) frequency (Fe) reached by the VCO is (ex : 7.02MHz). me a su re d wit h t h e f re qu e nc y watchdog function. 2nd step : To u s e a f re q ue n c y wa t ch d og Remark : The delay to be given must sequence to check whether the VCO be higher than sampling period of the has reached the wanted Fo frequency. watchdog (100ms). And since the 3rd step : To generate a well known voltage internal timing of the watchdog is not increase V in the drive of the VCO known, we think that the optimumdelay (this function can be done with the is 200ms. autocalibrationsetting of the STV42/56 circuits (Reg 05 loaded with value 03 With all above steps, the VCO slope can be calcuor 23)). Fe Fo V = 1V for Reg 05 : 23 lated as follows : KO V V = 2V for Reg 05 : 03 Figure 14 : PLL Demodulator, Auto-calibration Function
RF Signal V REF (bias) KD SWA FM Dev. Select. V REF K +1
AN838-14.EPS AN838-15.EPS
DET Pin
A I Leakage
V VCO KO SWA is opened during the auto-calibration V = 1V or 2V
CPUMP Pin
Figure 15 : Auto-calibration Timing, Diagram of the Potential Drifts
Slope due to leakages
V 1
2 Ideally
VCO Drive Voltage
fo
f fE
fe
fe2 VCO Frequency
1st Step 2nd Step
16/37
3rd Step
(4th Step)1
(4th Step)2 Optional
1 200ms 2 : defined fE : required information
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) c - How to Use the Results of the Auto-calibration Routine Let us keep in mind that the final objective is to get a PLL gain or a lock range as close as possible to its optimum value. Coming back to relation (1) :
L = KOTyp. Ktable KD = KOact Kcorrected K KOTyp. Ktable KOact Kco rrected : is the VCO slope when there is no dispersion. : is the required coefficient (Reg 05 b0-5), when KO has no dispersion. : the actual measured value (with the auto-calibration). : the coefficient that will be set after the auto-calibration.
The selection range of this new table is :
th RMin. Fe - F O th RMax.
How to select the optimum setting in the FM deviation table (Reg 05 B0-5) In the FM deviation table of the STV42/56 circuits, each step produces a 11% increase :
KN+1/KN = 1.11
d - Additionnal Advices about the Auto-calibration Function d.1 - When to implement the auto-calibration function ? It is suggested to implement the auto-calibration function when the end-user turns-off the satellite receiver (remote control command or front panel command). This position of the auto-calibration function offers two advantages : - The receiver is auto-calibrated when the part is already warmed-up. In this way potential drift related to temperature are taken into account. - The auto-calibration is done when the end-user no longer wishes to use the receiver, consequently the duration of the auto-calibration routine (about 1s) is no longer an inconvenience. d.2 - To minimize the errors coming from voltage offsets There are two settings of Reg 05, 03 and 23 which can be used for the auto-calibration, but in preactice we suggest to use Reg 05 : 03 because it produces a higher voltage increase in the VCO drive. In such a case the offset voltages have relatively less influence. d.3 - Compensation of the drifts appearing on CPUMP (see Figure 15) To be efficient, the auto-calibration routine must be as precise as possible. For this reason we would suggest to compensate some errors which may happen during the autocalibration routine. More precisely, it has been noticed that small leakage currents produce a drift of the CPUMP voltage which also drives the VCO. Consequently,because of the required delay between the 3rd and 4th steps of the auto-calibration routine, a small error may be induced in the drive voltage of the VCO. Suggestion : To repeat twice the 4th step (frequency watchdog). The first time about 200ms after the 3rd step. The second time after a well known duration after the first time. Assuming that the drift is linear, it is possible to correct the first reading. Additionnaly to minimize the leakage currents which would induce a drift of the CPUMPvoltage, it is suggested not to connect the PLL circuit to the incoming RF signal, but to keep the phase detector input to bias (ex: if left channel is calibrated Reg 06 B2 = L and Reg 06 B4 = L).
17/37
Consequenctlythe maximum allowed dispersion of the slope KO before a correction is necessary, is the dispersion which respects the following relation :
(1+ ) = (1 - ) 1.11 = 5.26%
Repeting the same idea, it is possible to build a table of the required correction versus the dispersion of the VCO slope. Proposed table : In this table R is the ratio : KOact / KOTyp.
R Min. -----0.692 0.768 0.853 0.947 1.0526 1.168 1.297 1.44 R R Max. 0.692 0.768 0.853 0.947 1.0526 1.168 1.297 1.44 -----Required correction -4 -3 -2 -1 No correction +1 +2 +3 +4
+ 1 means : for a given deviation, + 1 is added to the typical value which is loaded in Reg 05 (example for 50kHz, typical value is 36h and the corrected value is 37h).
Remark : In general the correction will not exceed 2.
In practice In practice the microcontroller which are used in the satellite receivers seldom have advancd arithmetic processing functions (such as division). So, we propose to compare the actual result (Fe - Fo) to its expected typical value th . th = V KOTyp. V : 1V for Reg 05:23h and 2V for Reg 05:03h KOTyp. : 460kHz/V To select the corection to be implemented, a table similar to the above described one can be used.
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) e - Suggested Flow Chart Following is a suggestion which has not been tested in SGS-THOMSON laboratory yet. Figure 16 : Auto-Calibration Flow Chart
Start Synthesis VCO fO
3.3 - Audio Processing Figure 17 and Figure 18 give the architecture of the audio processing part of the STV42/56 circuits. The main functions of the audio processing part are : - the audio noise reduction system (ANRS), - the audio de-emphasis, - the volume control with the mono stereo switch, - a switching array, - input/outputbuffers. 3.3.1 - Audio Noise Reduction (ANRS)
N
fVCO = fO 20kHz
About the ANRS, there is a main difference between the STV0042 and the STV0056. In the STV0042, the input signal of the ANRS is the sum of left and right (L + R) (see Figure 19). Wh e re a s, t h e ST V 00 5 6 h as t wo ind ependant ANRS (one for left and one for right) (see Figure 20). For this reason, it is recommanded to use STV0056 when "Panda" qualification is targeted. Additionnally, as far as the ANRS input is concerned, the STV0056 offers two options (K4) ; either the decoder return or the FM demodulator output. The decoder return has been implemented provisionnaly, but so far, the second output is required : FM demodulator output. 3.3.1.1 - Principle The basic idea of the ANRS is to controlled the bandwidth of the output gm amplifier versus the amplitude of the demodulated audio signal coming from the FM demodulator. To do so, the ANRS implements three main functions : - An external band pass filter which rejects the undesired signal components which remains at the output of the FM demodulator. - The filtered signal is rectified, so that the DC voltage at Pin PKOUT is an image of the audio signal amplitude. More precisely : (VPKOUT - VREF) = k . A = control signal with K = proportionnality coefficient and A = amplitude of the audio signal - The output stage is an amplifier whose transconductance is a function of the control signal gm = f(control) = f ( K . A )
V on VCO (auto-calibration)
Reg 05 03 Reg 06 00
Wait for 1 (ideally 200ms) Read watchdog fe
Wait for 2
Read watchdog fe2 Calculate fE from fe and fe2 Calculate Correction Save results in EEPROM END
AN838-16.EPS
18/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 17 : STV0042 Audio Processing Block Diagram (Channel Left)
STV0042
a K2 a b K3 5 bc K5 -6dB 28 DET L 18 40 2 PK OUT PK IN S2 RTN L 3 SUM OUT 1 41 FC R FC L 29 U75 L S2 OUT L 6dB 9 VOL L TV DECODER OR VCR 7 AUDIO DEEMPHASIS b a K1 c MONO STEREO
ANRS AUDIO L
PLL FILTER
Figure 18 : STV0056 Audio Processing Block Diagram (Channel Left)
STV0056
a K2 b a b K3 4 abc K5 6dB -6dB 39 DET L 27 S3 OUT L 24 S3 RTN L 52 54 53 55 PK OUT L PK IN L LEVEL L FC L 32 J17 L 40 U75 L 12 S2 OUT L AUDIO DEEMPHASIS c
a b c
K1
AUDIO L abc K6 6dB K4 b
ANRS
MONO STEREO
a
-6dB 21 S2 RTN L 10 VOL L
PLL FILTER
DECODER
VCR
TV
19/37
AN838-18.EPS
Audio Decoder Out
Audio Decoder Return
AN838-17.EPS
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 19 : STV0042 ANRS Block Diagram
FM Demo Right FM Demo Left L To Audio De-emphasis R Rectifier -6dB 5k Control gm gm
STV0042
SUM OUT C63
PKIN
PKOUT
FCL
FCR C65 R59 C64 R58
AN838-19.EPS
R51 R57
C58
R60
R53
C66 BPF V REF
C60
BPF : Band Pass Filter
Figure 20 : STV0056 ANRS Block Diagram
FM Demo Left L
STV0056
To Audio De-emphasis
Rectifier
5k Control
gm
LEVEL L C115
PKIN L
PKOUT L
FCL
R113 R117
C112
R60
R53
C66 BPF V REF
C60
AN838-20.EPS
BPF : Band Pass Filter
20/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.3.1.2 - Dimensioning the External Components a) The Band Pass Filter : BPF The output signal of the FM demodulator contains different components : - The desired demodulated signal, - beat signal of the unwanted subcarriers with the VCO frequency, - beat signal of the attenuated video with the VCO frequency (attenuated video : the input filter C25, R18, R17, L4, C24 does not totally reject the video). The amplitude of the beat signals cannot be neglected when the desired audio signal has low amplitudes. Consequently, it is necessary to filter the signal before the rectifier. For a better efficiency a 12dB/octave filter (order 2) is prefered. The suggested solution (Figure 21) is a simple, low-cost, active filter (using a Sallen and Key structure). Main characteristics : ZIN few k, ZO 100, Bandwidth 15kHz, Attenuation at 80kHz 25dB, Peaking 1.3dB A small peaking has been prefered to provide a small correction of the frequency response of the complete ANRS. Figure 21 : Example of Simple Band Pass Filter b) Input and Output Circuitry of the Rectifier (R117, C115, C112, R113) C115 is necessary because the rectifier requires a capacitive coupling with the BPF. C115 value is not critical (C 220nF). R117 value combined with an internal 68k resistor, gives the gain of the rectifier : (VPKOUT - VREF) = K A 68k with K R117 C112 : Combined with an internal 5k resistor, the C112 capacitor produces a time constant which is optimized in order to have the lowest overshoot as possible on the rising edge of the 2Hz/4 / 1 burst pattern used in the PANDA qualification. Once C112 is fixed, R113 is choosen to produce a delay time constant which compensates the envelop appearing at the beginning of the low amplitude session of the 2Hz/4 / 1 burst pattern used in the PANDA qualification. Good compromise with R113 = 560k. Remark : The Rectifier is not a full wave one, it works with negative halfwaves.
LEVEL 12V
R114 C114 R115
R116 To R117
Q103 C113
21/37
AN838-21.EPS / AN838-21.TIF
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) c) Load of the Output Amplifiers (R60, C66, R53, C60) Looking at more in details, the output amplifier can be described as given in Figure 22. Figure 22 : ANRS Output Amplifier Structure
Control To Audio De-emphasis From FM Demodulator gm R60 VI x1 VO ZL C66 C60 R53
AN838-22.EPS
qualification (PPL : standing for peak program level which is equivalent to full deviation 50kHz) In summary : R53 C60 75s
R53 and R117 optimized to get flat frequency response with (PPL-18dB) and (PPL-28dB).
with such a structure :
gm ZL VO = VI 1 + gm ZL
R60 C66 Filter : Without this filter, when the audio signal is very low (VPKOUT VREF) or when there is no signal, the 1/gm value reaches very high values (several M) ; under those conditions the FC Pins have a very impedance and become a noise pick-up. With the R60 C66 filter, the maximum impedance which can be reached by the FC Pins is clipped to the value of R60 ; the S/N ratio is greatly improved. C66 is not actual (C66 10nF). 3.3.1.3 - Results with PANDA Encoder Refering to the STV0056 specification. a) Distorsion is lower than 1% at PPL b) Crosstalk is typically lower than 60dB in stereo at 1kHz c) Signal to noise ratio unweighted (output level : 0.77VRMS) S/N = 67dB typ. S/N 74dB typ. (with 400HzHPF) d) Frequency Response at (PPL - 18dB) and (PPL - 28dB) (see Figure 24) e) Compander Gain Tracking
Input Level PPL PPL - 10dB PPL - 20dB PPL - 30dB PPL - 40dB PPL - 50dB PPL - 60dB 400Hz 18dB 11.4dB 0 -11.1dB -20dB -29.4dB -37dB 10kHz 16dB 8.4dB 0 -8.8dB -17.8dB -27.4dB -36dB Limits 23/17dB 23/17dB Reference -13/-7dB -23/-17dB -34/-26dB -47/-33dB
(1)
In order to simplify the calculations, it can be noticed that the R60 C66 filter only operates at very low frequencies, and assuming that R60 >> R53, the impedance ZL can be reduced to (R53 + C60). With such assumptions
R 53 C 60 p + 1 VO = 1 VI C60 p + 1 R53 + gm p : Laplace operator (p = j2f in the frequency field) gm = f(control)
Conclusion : The output stage of the ANRS behaves as a filter having a fixed zero and a variable pole (depending on the audio level) (see Figure 23). Figure 23 : ANRS Output Amplifier, General Frequency Response
Vo / V i
(zero) 1 2 R53 . C60
Figure 24 :
A : PPL - 18dB . A : PPL - 28dB
f
2 C60 ( R53 +
(pole)
1 ) gm
The ANRS is used in combination with the 75s de-emphasis ; consequently the (zero) frequency is choosen to compensate the de-emphasis R53 C60 75s The value of R53 is optimized in order to get the flatest frequency response as possible at levels (PPL - 18dB) and (PPL - 28dB) of the PANDA
22/37
AN838-23.EPS
1
AN838-24.TIF
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.3.2 - Audio De-emphasis The audio de-emphasis functions are simply realized with transconductance amplifiers loaded by external loads whose impedance follow the required de-emphasis laws (see Figure 25). With such structures : VOUT = VIN gm ZL (1) ZL : Output Impedance (external circuit) 3.3.2.1 - Dimensioning the External Components a) J7 De-emphasis (STV0056 only) Using relation (1) :
R 107 C108 p + 1 VO17 = R106 + R 107 C108 p + 1 VI p : Laplace operator (p = j2f in the frequency field)
R106 34.7k R106 = 36k
(2)
As far as AC characteristics are concerned : (3) 4135Hz 2 R107 C108 (zero of the J17 curve)
1
(4)
1
2 ( R106 + R107 ) Cp (pole of the J17 curve)
477Hz
Combining (2) (3) (4) : R107 = 4.69k R107 = 4.7k C108 = 8.19nF C108 = 8.2nF Remark about J17 1) Due to the zero of the J17 law, the high frequency signals contained in the input signal are not completely attenuated. This explains why the beat frequency produced inside the PLL section remains present at the scart output when J17 is selected. If the user prefers to give a further attenuate to the high frequencysignals, optionnallyCOP can be used (COPT is choosen to produce a additional pole at about 20kHz). In theory COPT 1.9nF (1.5nF can be also selected for standardization of values). 2) Under certain conditions it is possible to implement both J17 and 50 /75s wit h STV0042 (please refer to "Application options" Chapter 4.2).
The DC gain of the J17 de-emphasis is dimensionned in order to comply with the scart recommandations : VOUT scart = 1VRMS 3dB at full deviation. Taking into account the 6dB gain of the scart drivers.
VO17 = VOUT scart
2
= 0.5 VRMS 1.41 VPP
VO17 DC = gm R106 VI with gm =
1
10.8k
(integrated characteristics)
VI = 0.44 VPP (at low frequencies of a J17 preemphazed signal)
Figure 25 : Audio De-emphasis Solution
From Switch K3 J17 gm Rb Vi V ia SW1 V REF J17L C108 Copt R106 V 017 R107 V REF C39 SW0 V REF U75L Ra 50/75s gm Rint To Switch K2
R34
Rb 0.66 Ra + Rb
23/37
AN838-25.EPS
V 075 or V 050
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) b) 75s De-emphasis When the 75s de-emphasis is selected, SW1 is closed and SW0 is opened. The de-emphasis amplifier is only loaded by the external C39 R34 filter, and with SWI the input level is attenuated in order to have similar output levels for both 75 and 50s de-emphasis. DC gain : VO75 = Via gm R39 with VO75 = 1.41 VPP R34 25.4k 27k gm = 1/10.8k Via = 0.66 VI VI = 0.905 VPP AC characteristics : R34 C34 75s C39 = 2.7nF c) 50s De-emphasis When 50s de-emphasis is selected, SW1 is opened and SW0 closed. The load of the de-emphasis amplifier corresponds to the external filter in parallel with an internal resistor RIN. This configuration would give a lower DC gain, but in compensation the input signal is not attenuated (SW1 : opened). Remark : In theory Rint value should be equal to 2 x R34. This not the case. This imperfection of the circuit will be corrected in a version which will be launched lately (STV0056A). d) General Remark about the Audio De-emphasis When the audio de-emphasis Pins are not used, it is required to directly connect them to VREF. 3.3.3 - Volume Control, Mono Stereo Switch Most of the informations relevant to the volume stage are given in the specification. The mono/stereo switch allows to output on the volume controlled stage either the stereo signal or twice left or twice right. Remark : The mono/stereo switch is only available on volume outputs. In case of multilingual channels it is preferable to set the two FM demodulators on the same subcarrier, so that there is no problem for the other outputs : S2 and S3. 3.3.4 - Switching Array The STV42/56 circuits offer many switching configurations, please refer to the specification for details. 3.3.5 - Input/Output Buffers a) The input buffers (S2RTN, S3RTN Pins) have two important characteristics : - the input impedance is 25k typically, - a 6dB attenuation: allowing to accept signals as high as 2VRMS. b) The output buffers (S2OUT, S3OUTPins) have the following characteristics : - 6dB gain : in order to have a 1VRMS output signal at full deviation, - can be set to high impedance, this feature is interesting for twin tuner applications, - output impedance ZOUT is about 60 (in active mode). Remark : Under certain conditions, this rather low impedance (60 Typ.), allows to realize the (L + R) function (required to drive the RF modulators) by simpling using two resistors without inducing high level of crosstalk (see Figure 26). The crosstalk level can be calculated as Ctk = with V3 = 0 V1 assuming ZOUT << R, and Req = R//ZIN
V2
V2
V1
R + ZOUT Req + R
ZOUT
Req
Example : a RF modulation with ZIN = 10k and requiring 1.24VPP at full deviation R = 27k (Ctk)dB = -66dB
Figure 26 : Simple (L + R) Function for RF Modulator Drive
To Scart Z OUT V1 Z OUT V3 R L R R To RF Modulator (Z IN )
AN838-26.EPS
V2
To Scart
24/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.4 - Others Functions, Miscellaneous 3.4.1 - Power Supplies For operation, the STV42/56 circuits simultaneously require both a 5V (VDD) and a 12V (VCC). Due to an internal reset function, the STV42/56 circuits stop working when either the 5V or the 12V line is faulty (or both). Under this condition all the registers are reset and the I2C decoder stops operating. Remark : The reset signal is available at Pin I/O of STV0056 when R5 B7 = H and R5 B6 = L. Reset signal is active high. Important Remark : For power consumption and reliability, it is not recommanded to only supply either the 5V or the 12V. Under those conditions, high currents may circulate in the ESD protection circuit (electrostatical discharge protection diodes). 3.4.2 - Active/Stand-by Modes The STV42/56 circuits features a stand-by mode in which the power consumption is greatly decreased (one thrird). However in this stand-by mode the following functions remain active : - I2C bus decoder, - audio switching matrix, - video clamp and switching matrix. With such a configuration it is still possible to route signals during the stand-by mode of the receiver (example : to connect the VCR scart audio and video signals to the TV scart). To enter or to exit the stand-by mode is simply done by driving R04 B3. Remark : To minimize the power consumption in stand-by, it is recommanded to set as many audio and video output stages in high impedance modes (minimizes the STV42/56 consumption and turns off the external 75 video buffers). 3.4.3 - Crystal / Clock Two functions of the STV42/56 circuits require a precise reference frequency : the 22kHz tone generator and the frequency synthesis function of the FM demodulator (required accurary < 0.4%). Two possible frequencies can be selected 4MHz or 8MHz (R02 B3). The clock pin XTL of the STV42/56 have been designed to either work with a external crystal or to be an clock input.For instance, this second solution can be used if the microcontroller work with a 4MHz or 8MHz crystal (see Figure 27). Figure 27 : External or Internal Clock Generation
MCU STV42/56 STV42/56
OSCIN OSCOUT XTL 22pF 4 or 8MHz 1 INTERNAL 2 EXTERNAL R C few k R 30k C not critical
AN838-27.EPS
XTL
Remark : If for cost reasons, clock signals with an accurary ranging from 0.3 to 0.6% are prefered, please contact with SGS-THOMSON. 3.4.4 - 22kHz Tone Generator The STV42/56 circuits can generate the 22kHz tone signal required to control the LNB systems. The actual frequency is 22.22kHz ; the frequency accuracy is very high because the tone signal is derived from the clock signal. Depending on the register settings, there are several possibilities to get the 22kHz tone : STV0042 Pin 13 R03 B3 : H and R01 B7 : L STV0056 Pin 16 R03 B3 : H and R01 B7 : L STV0056 Pin 29 R05 B6 : H Remark : When STV0042 Pin 13 or STV0056 Pin 16 is used to generate the 22kHz tone signal, some care must be taken to avoid crosstalk on the VIDEEM1 Pin : - to limit the parasitic capacitance of the PCB between VIDEEM2/22kHz Pin and VIDEEM1 Pin (optionnally some ground shielding track can be layout between those 2 pins). - Optionnally, the slew rate on VIDEEM2/22kHz Pin can be decreased by connecting a capacitor to ground ( 100pF). - The equivalent impedance at VIDEEM1 Pin can be decreased (see last remark of pa ragraph 3.1.1.3). 3.4.5 - I/O Interface The Pin 29 of STV0056 circuit can be set as a general purpose digital I/O (Input/Output).To do so, R05 B6 B7 R06 B0 B1 are needed. For example in combination with a resistor divider, this I/O may be used to monitor the Pin 8 of a scart connector.
25/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) 3.5 - PCB Layout Recommandations The pinout of the STV42/56 circuit has been defined to, in the widest extent as possible, simplify the PCB layout. Dual in line plastic packages (SDIP42 or SDIP56) have been prefered to offer a low cost solution. Additionnaly with these packages very compact and efficient layout can be design by soldering surface mounted devices (SMD) under the circuit. 3.5.1 - Power Supplies and Ground Paths With reference to the STV42/56 pinnout and to the Figure 30 of the specification (page 21/33 of the specification dated June 95). The STV42/56 circuits feature : - 3 independants power supply lines (5V, 12V Video, 12V Audio), - 4 independants ground pins (GND 5V, Video Ground, Audio Ground Left, Audio Ground Right). In such as a configuration, to avoid interferences between the different supply lines, it is important : (see example in Figure 29). - To make a star connection of the four ground tracks. - To have short connections to the decoupling capacitor of each supply line (at least to the ceramic capacitor which realizes a good decoupling of the high frequency components of the supply current). 3.5.2 - IREF /VREF Pins With an external 240k 1% resistor (or very close value), the IREF Pin is used to produce a 10A reference current which is used to bias most of the internal functions of the circuit. The ground point to which this external resistor is connected must not be polluted ; ideally it is the audio ground right pin or in between audio ground pin and the ground star point. A VREF line (2.4V) is generated by the STV42/56 circuits. This reference line is used to bias the audio stages (audio de-emphasis, noise reduction). Typically a 470F external capacitor C40 is used for decoupling, preferally this capacitor is connected close to the VREF Pin. Optionnally, to improve the left to right crosstalk at low audio frequencies, low pass filters can be used for both left and right current paths ; those two filters are connected to the VREF decoupling capacitor C40 (see Figure 28). Figure 28 : Optional VREF decoupling with Separated Left and Right Paths
From J17L U75L DETL 470 100F V REF 470 C40 100F
AN838-28.EPS
From J17R U75R DETR
100F
3.5.3 - Insulation between the Video Inputs and Outputs A lot of care must be given in making two separate ground paths one for the video input, the other for video outputs. Reason : Due to the low impedance (75) of the video sources (TV return, VCR return, decoder Return) and of the video outputs (TV out, VCR out, decoder out), even small commun PCB pattern produces important crosstalk. Example : a 0.1 commun impedance on the groud path between the input and the outputs would generate (-57dB) of crosstalk. 3.5.4 - Insulation between Video Outputs Again due to the low impedance it is important to minimize the commun impedance between the different outputs. To do so, it is preferable to make a star connection with the output video buffers and with the video ground of each output connector (GND1, GND2, GND3) (see Figure 29). Additionnaly it is recommanded to have a short connection between the ground star point and the video (12V) decoupling capacitor, C33.
26/37
STV0042/STV0056 APPLICATION NOTE
3 - APPLICATION NOTES (continued) Figure 29 : PCB Layout, Ground Pattern (good and uncorrect layout)
DEL RTN VCR RTN TV RTN
GND1
GND2
GND3
Video Input GND
12V Option 12V GND
Video Buffers
GOOD LAYOUT
STV0042/STV0056
GND1
GND2
GND3
Video Output GND
GND
AN838-29.EPS
UNCORRECT LAYOUT
STV0042/STV0056
3.5.5 - Insulation between Video Inputs As usually required with video signals, it is recommanded to minimize the parasitic capacitances between the video inputs. For memory, one pF (picofarad) parasitic produces about 61dB crosstalk at 5MHz. When possible, to minimize this capacitance, a ground shield can be layout between the video tracks. 3.5.6 - 22Hz Tone Influence on VIDEEM1 When the VIDEEM2/22kHz Pin is used as a 22kHz tone generator some care has to be taken in the PCB layout. The 22kHz tone track must be layout as far as possible from the VIDEEM1 Pin and from R10, R11, C13, R9, C12.
It is also recommanded to layout a ground shield. 3.5.7 - Video Crosstalk on the Right Channel Due to the circuit pinnout, the right channel noise reduction circuit is quite close to the video section. This remark is particularly important for FCR Pin which drives a high impedance ( 51k at 15kHz when the audio signal is low amplitude). If no care is taken in the PCB layout, the video crosstalk may jeopardize the audio S/N which may become critical when applying for PANDA qualification. Consequently, it is recommanded to minimize the capacitive couplingbetween FC right and the video tracks.
27/37
STV0042/STV0056 APPLICATION NOTE
4 - APPLICATION OPTIONS This part refers to some specific application cases (not typical cases). 4.1 - Simplified Video De-emphasis Channel 4.2 - J17 De-emphasis Generation with STV0042 In some specific applications, such as add-on Some specific applications, or some specific marboard in TV set, the J17 de-emphasis may be kets do not require to ouput a baseband signal. required. There are two solutions (see Figure 31). Under this condition it is possible use the application diagram given in Figure 30. Solution 1 The conventional emitter follower stage Q used at This solution canbe implemented when the S2OUT the tuner output is changed into a voltage amplifier and S2RTN are not required (no interface with (gain 3), and the video de-emphasis is done with decoder or when the interface function is implethe filter (Ra, Rb, C). mented on the TV main board. In this solution, the PLL demodulator output signal is sent to S2OUT To recover the correct phase the inverter stage is Pin (switch K5 to C, see STV0042 specification). set by software R01 B6. The de-emphasisamplifier And a J17 filter (R1, R2, C) is connected between is turned into a follower stage. S2OUT and S2RTN. Remark : Remark : Ra is choosen around 1k in order not to be With this solution, at full deviation the level is 1VPP sensitive to the dispersion of the input stage impedat S2RTNPin. The level difference with 75s needs ance. to be compensated by the volume stage (+3dB). Advantages : Compared with the typical application, this circuits offer two advantages : - to save one electrolytre capacitor (C13), - to drive the input stage with attenuated high frequencies, this helps to minimize the potential intermodulation between the FM subcarriers with the video or the intermodulation of the parasitic side bands producedby the tuner with the wanted channel. Figure 30 : Simplified Video De-emphasis Channel
12V
Solution 2 When solution 1 cannot be implemented, a second solution which switches de-emphais filters at U75 pin can be used. The switch can be simply realized with PNP bipolar transistor, this solution does not provide distorsion if the base of those transistors is properly pulled down to the ground (R1 and R2 10k). The control is done by two switches (transistors, or MCU I/O) which are in opposite state (K1 closed K2 opened, and vice-versa).
Ra
1k
1k LPF
TUNER
Q
1 Rb
Rc
AN838-30.EPS
C To FM Demodulation Section
28/37
STV0042/STV0056 APPLICATION NOTE
4 - APPLICATION OPTIONS (continued) Figure 31 : J17 De-emphasis with STV0042
STV0042
U75
STV0042
75s bc 27k 2.7nF 36k
J17 4.7k 8.2nF Q2 VREF
AN838-31.EPS
To Volume Control S2RTN
K5 S2OUT
R1 120k
R2 15k C 2.7nF
Q1
V REF
R1
K1
R2
K2
1
2
4.3 - Simplified Audio Noise Reduction or No Noise Reduction When it is not required to perfectly match with the PANDA noise reduction, the external filter used between LEVEl and PKIN Pins of STV0056 or SUMOUT and PKIN of STV0042 can be simplified (see Figure 32). When no noise reduction is required, the following changes needs to be implemented in the application : - to take all components connected to Pin LEVEL, or SUMOUT, PKIN, PKOUT, FC, - to keep floating LEVEL or SUMOUT Pins, - to connect to VREF : PKOUT, PKIN Pins, - to connect FC Pin either to VREF or GND. 4.4 - Audio Mono Applications This kind of application may be required for collective receiving systems where audio mono channels are processed. For those applications, more likely the STV0042 is choosen, and the following changes are recommanded : - to remove all the components relevant to one channel (for example left)
- Following pins must be grounded : AGC, AMPLOCK - Following pins must be connected to VREF : DET, U75, CPUMP, FC - The capacitor C40 may be reduced to 10 or 22F. - The resistor R57 must be reduced to half value (about 13 to 15k) in case of STV0042. A typical audio mono application diagram is given in Chapter 7. Figure 32 : Noise Reduction, Simplified BPF
SUMOUT or LEVEL L,R
PKIN or PKIN L,R
5.6k
22k
220nF
1nF
AN838-32.EPS
29/37
STV0042/STV0056 APPLICATION NOTE
5 - TWIN TUNER APPLICATIONS It is very easy to build twin tuner applications with STV42/56 circuits without extra audio and video switching hardware. Twin applications are simply realized by paralleling the audio/videoinputs and outputs (see Figure 33). - The audioinputs impedance is 25k, so a parallel configuration gives 12.5k (still compatible with the Scart standard). - The video inputs impedance is a few k, so by far enough for parallel configuration. - The audio and video outputs feature a high impedance mode (accessed by software) which allows to directly connect the outputs one to the other. By software one output is set to high impedance mode while the other is active. Remark : Per default, to avoid conflicts at power-up all audio and video outputs are set to high impedance mode. To avoid I 2C bus address conflicts, the STV0056 feature a hardware address pin HA which is used to define two addresses. Twin tuner applications can be realized either with two STV0056circuits or with STV0056 + STV0042. 6 - SATELLITE RECEIVER BUILT IN VCR OR TV SETS For cost reasons, in these applications the STV0042 may be prefered. The add-on applications are basically the same as stand alone receivers, however here are some suggestions : J17 with STV0042 Please refer to the chapter "Application Options" (section 4.2). Clock Generator In these applications, in order not to route a disturbing 4MHz or 8MHz clock signal from the main chassis ; the clock signal is generally generated locally on the add-on board. There are two options : - to use 4 or 8MHz crystal with the STV0042 circuit, - or to use the 4MHz clock signal which is often generated inside the tuner (this point has to negociated with tuner makers). Power Supplies As mentioned in chapter "Other Functions/Miscellaneous" (section 3.4.1) , it is important to simultaneously maintain or turn-off both the 5V and 12V. It is important to bear this point in mind when designing the power system of the VCR or TV set. Remark : Thanks to the low power consumption mode of the STV42/56, the power consumption remains reasonnable even when the add-on board is supplied during the stand-by mode of the VCR or TV set. 22kHz Tone T h e sig n a l ca n VIDEEM/22kHz Pin. be o u t pu t at th e
Figure 33 : Twin Tuner Applications. No Extra Switching Hardware Required.
Video
8
TUNER 1
34
I C Bus
2
S T V 0 0 5 6
9 7
TV SCART 6-10 12-14 27-28 Audio 2 Video
VCR SCART Audio 2 Video
8
TUNER 2
5V
34
27-28
30/37
AN838-33.EPS
S T V 0 0 5 6
9 7
DECODER SCART 6-10 12-14 Audio 2
Figure 34
SEL56185MHz LPF made by TDK / Japan :
VCR SCART TV SCART
DECODER SCART
1
2 1 3 5 7 9 11 13 15 17 19 21
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R102 75
2 4 6 8 10 12 14 16 18 20
C101 220nF R6 75
1 2 3 5 7 9 11 13 15 17 19 21 4 6 8 10 12 14 16 18 20
C4 220nF
J1
21
J3
J2
C7 2.2F
R5 68 R J6
C8 2.2F C6 2.2F
L VCCV Q2 BC547 Q101 BC547 V J4 Q1 BC547 VCCV VCCV J5
C103 2.2F
C104 2.2F
C5 2.2F
R103 68
C105 2.2F
C102 2.2F
TDK FILTER SEL5618 C11 8.2nF
R4 470 R101 470
C3 2.2F
R3 470
C2 2.2F
R2 68
1 2 R16 1k R11 1.5k + C13 10F 16V JP12 C12 100pF R10 10k R9 5.1k
3
R15 1k
C100 220nF C26 10F 16V
VCCV
R100 75
J7
TUNER INPUT
C25 100pF R17 470
C23 8.2nF
R48 75
R18 1k
L4 47H
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C24 27pF
C56 100nF
C64 1.5nF R58 51k
C65 100nF R59 1M
7.1 - STV0056 : 3 Scarts PAL/Europe Application (Figure 34)
J8 I/O 1 CLOCK 1 INPUT J9
STV0056
32 35
JP4 V DD C29 22pF 4MHz or 8MHz Crystal R36 560k C42 100nF R50 237k 1% C43 100nF VCCA C41 10F 16V C50 10F 16V R53 51k C60 1.5nF R60 1M C66 100nF C115 220nF R37 560k C58 100nF C112 100nF R114 3.3k R51 560k R113 560k C114 8.2nF R117 27k C63 220nF C62 8.2nF R54 3.3k
29 36 37 38 + 39 40 41 42 43 44 45 46 47 48 49 + 50
30
31
33
34
51
52
53
54
55
56
R57 27k
5V SDA SCL GND
J10 1 2 3 4
C66 47pF
C65 47pF
7 - TYPICAL APPLICATIONS DIAGRAMS This chapter is simply a compilation of different typical application diagrams
J11 5V 1 GND 1 J12 C45 100nF
L1 22H
VDD
+ C31 220F 16V
C30 100nF
VCCV
J13 L2 22H 12V 1 GND 1 J14
+ C33 220F 16V
C32 100nF
VCCA C108 8.2nF C37 22pF R106 36k R32 82k C38 22pF R33 180k R34 27k + C39 2.7nF R39 27k C46 2.7nF R40 180k C47 22pF R107 4.7k C48 22pF R41 82k C40 470F 16V
R115 1.5k C113 1.5nF Q103 BC557
R116 10k
R55 1.5k C61 1.5nF VCCA
+ C35 220F 16V
C34 100nF
C107 8.2nF
R56 10k Q4 BC557
R104 4.7k
R105 36k
STV0042/STV0056 APPLICATION NOTE
31/37
AN838-34.EPS
32/37
VCR/DECODER SCART TV SCART
1 2 3 5 7 9 11 13 15 17 19 21 4 6 8 10 12 14 16 18 20
Figure 35
Optionally :
A second video deemphasis network R13, R12, C15, R14, C14 is shown for 525 lines systems. J2
1 3 5 7 9 11 13 15 17 19 21
JP1 .. JP 11 : Jumper required for PCB compatibility with STV0056
2 4 6 8 10 12 14 16 18 20
R6 75
J1
C4 220nF
SEL5618 :
5MHz LPF made by TDK / Japan
C7 2.2F
J6
C8 2.2F C6 2.2F C5 2.2F
L R5 68 VCCV Q2 BC547 Q1 BC547 V J4 VCCV J5
R
TDK FILTER SEL5618 C11 8.2nF
1 R16 1k R13 10k R12 1.8k R10 10k R11 1.5k + C13 10F 16V JP11 C12 100pF C15 10F C14 150pF 16V + R9 5.1k
R4 470 R3 470
2 R14 5.6k C3 2.2F C2 2.2F
R2 68
3
STV0042/STV0056 APPLICATION NOTE
R15 1k
J7
C25 100pF R17 470 100nF
VCCV
C23 8.2nF C26 10F 16V
JP1
C56
JP9 JP10 JP8
7 - TYPICAL APPLICATIONS DIAGRAMS (continued)
TUNER INPUT
R48 75
R18 1k
L4 47H
L9 47H
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C65 100nF
C24 27pF
C70 39pF
C64 1.5nF
R57 27k R59 1M R58 51k C63 220nF R54 3.3k
J8 I/O 1 CLOCK 1 INPUT J9
STV0042
23
+ V DD VCCA C29 22pF VDD 4MHz or 8MHz Crystal R36 560k C42 100nF C45 100nF R37 560k C41 10F 16V C43 100nF
JP2
22
24
25 26 27 28 29 30 31 33 34 35
32
36
37
38
+
39
C50 10F 16V
40
41
42
JP5 JP7 R50 237k 1% R60 1M C58 100nF R51 560k C66 100nF R53 51k C60 1.5nF
7.2 - STV0042 : PAL/NTSCApplication (2 video de-emphasis) (Figure 35)
C62 8.2nF
J10 5V 1 SDA 2 SCL 3 GND 4
C66 47pF
C65 JP6 47pF
R56 10k Q4 BC557
R55 1.5k C61 1.5nF VCCA
J11 5V 1 GND 1 J12
L1 22H
+ C31 220F 16V
C30 100nF
VCCV C37 22pF R32 82k C38 22pF R33 180k C39 2.7nF R34 27k R39 27k C46 2.7nF R40 180k C47 22pF C48 22pF R41 82k + C40 470F 16V
J13 L2 22H 12V 1 GND 1 J14
+ C33 220F 16V
C32 100nF
VCCA
+ C35 220F 16V
C34 100nF
AN838-35.EPS
Figure 36
AUXILLARY OUTPUTS R L J5 L V OUTPUTS TO TV
JP1 .. JP 11 : Jumper required for PCB compatibility with STV0056
LPF 1 2 R16 1k
R13 10k
R V CCV Q2 BC547 Q1 BC547 V R5 68 R2 68 J4 V CCV
C11 8.2nF 3
R14 5.6k
C6 2.2F
J6
C5 2.2F
R15 1k 10F 16V
R4 470
R12 1.8k
C15 + 150pF
C14
JP1 C56 100nF
VCCV
J7
C25 100pF R17 470 C26 10F 16V JP11
C23 8.2nF
C2 2.2F
C3 2.2F
R3 470
TUNER INPUT
R48 75
R18 1k
L9 47H
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7.3 - STV0042 : PAL M / Brazil Application (Figure 36)
C70 39pF
7 - TYPICAL APPLICATIONS DIAGRAMS (continued)
J8 I/O 1 CLOCK 1 INPUT J9
STV0042
23
VDD C29 22pF VDD 4MHz or 8MHz Crystal R36 560k C42 100nF C45 100nF R37 560k C41 10F 16V C43 100nF VCCA
JP2
22
24
25 26 27 + 28 29 30 31 33 34 35
32
36
37
38 +
39
C50 10F 16V
40
41
42
5V SDA SCL GND
J10 1 2 3 4
C66 47pF
C65 JP6 47pF
R50 237k 1%
J11 5V 1 GND 1 J12 C37 22pF R32 82k C38 22pF R33 180k C39 2.7nF R34 27k +
L1 22H
+ C31 220F 16V
C30 100nF C48 22pF R39 27k C46 2.7nF R40 180k C47 22pF R41 82k C40 470F 16V
VCCV
J13 L2 22H 12V 1 GND 1 J14
+ C33 220F 16V
C32 100nF
VCCA
+ C35 220F 16V
C34 100nF
STV0042/STV0056 APPLICATION NOTE
33/37
AN838-36.EPS
34/37
RTN EXTERNAL DECODER OUT VCCV VCCV OUT RTN
Figure 37
Optionally :
A second video deemphasis network R13, R12, C15, R14, C14 is shown for 525 lines systems.
JP1 .. JP 11 : Jumper required for PCB compatibility with STV0056
SEL5618 : Q2 BC547 Q1 BC547 V J4
MAIN OUTPUTS
5MHz LPF made by TDK / Japan
TDK FILTER SEL5618
C11 8.2nF
R10 10k
R5 68
1 R16 1k
R11 1.5k
R J6
2
R9 5.1k
R4 470 R3 470
R2 68
3
C12 100pF
R15 1k
+ C13 10F 16V
C3 2.2F C7 2.2F
VCCV
JP9 JP10
STV0042/STV0056 APPLICATION NOTE
J7
TUNER INPUT
C25 100pF R17 470 C26 10F 16V C6 2.2F C4 220nF JP11 R6 75
C23 8.2nF
R48 75
R18 1k
L4 47H
JP8
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7 - TYPICAL APPLICATIONS DIAGRAMS (continued)
C24 27pF
C65 100nF R59 1M
C64 1.5nF
J8 I/O 1 CLOCK 1 INPUT J9
STV0042
24
VDD C29 22pF 4MHz or 8MHz Crystal C45 100nF R37 560k C43 100nF VCCA
R57 10k
JP2
22
23
25 26 27 28 29 30 31 33 34 35 36
32
37
C50 10F 16V
38
+
39
40
41
42
JP5
R58 51k
C63 220nF
R54 5.6k C61 1.5nF R50 237k 1% R51 560k C58 100nF
J10 5V 1 SDA 2 SCL 3 GND 4
C66 47pF
C65 JP6 47pF
J11 5V 1 GND 1 J12
L1 22H
VDD
+ C31 220F 16V
C30 100nF C48 22pF R39 27k + C46 2.7nF R40 180k C47 10pF R41 82k
VCCV
J13 L2 22H 12V 1 GND 1 J14
+ C33 220F 16V
C32 100nF
7.4 - STV0042 : Audio Mono Application, with Simplified Audio Noise Reduction (Figure 37)
VCCA
+ C35 220F 16V
C34 100nF
C40 22F 16V
AN838-37.EPS
STV0042/STV0056 APPLICATION NOTE
8 - POTENTIAL PROBLEM AND SUGGESTED SOLUTIONS This chapter deals with potential problems or undesired effects in the application and suggests solutions. Remark : SGS-THOMSON will improve points 8.2, 8.4, 8.7 which directly depend on the STV42/56 circuit. 8.1 - Sound Cracking and Distorted Sibilance Ideally the internal resistor value should be twice the value of the external resistor. Currently the When the characteristics of the PLL demodulator situation is : are not optimized, two effects may happen : Rint = 30k, R34 = 27k (for left) (July 95). - Distorted sibilance ("S" sounds are emphazed) : this corresponds to a too narrow lock range. This point will be corrected by SGS-THOMSON. - Small crackles (click) : this corresponds to a too wide capture range. 8.3 - Noisy Video Signal If such effects appear, it is important to check that the PLL gain is properly calibrated. To do so, a test If the selected tuner does not features a high signal is supplied to FM IN, and a 1VPP 8% ideally rejection of the frequencies higher than 10MHz ; (or 10% can be accepted) must be found on the under certain conditions, it can be noticed an interDET Pin. modulation background noise in the video signal. One of the reasons of this effect is the wide bandTest Signal : FM subcarrier : 50kHz full deviation, width of the baseband input stage of the STV42/56 400Hz modulating frequency circuit which peaks or keeps some gain at frequenVery likely, a too large signal on DET Pin correcies as high as 25MHz. sponds to distorded sibilance, and a too low signal corresponds to sound cracking. SGS-THOMSON is evaluating this problem. After this test, the PLL calibration procedure must In the meantime, two solutions are suggested : be optimized (see section 3.2.2.3). 1) To implement an efficient low pass filter (rollSome crakles may remain on some paticular off at 10MHz) between the tuner and the base channels which slightly overmodulate. Normally band input. A (R,L,C) filter can be used (see this case is corrected inside the STV42/56 cirFigure 39-1) cuits by a clipping circuit which limits the DET Pin 2) To modify the typical video de-emphasized swing. To totally take out the remaining crakles, channel as follows : (see Figure 39-2) an external clipping circuit may be experimented (see Figure 38). - Video de-emphasis is directly performed at the tuner output (Ra, Rb, Rc). Figure 38 : Optional External Circuit to limit DET - An the baseband signal is recovered by Signal Swing changing the de-emphasis amplifier into a pre-emphasis amplifier. DET - To get a 1VPP output signal, and to recover the same phase as the baseband signal, a 2 transistors amplifier is implemented before the video LPF. This second solution provide a natural 14dB attenuation for all frequencies higher than the VREF zero of the video pre-emphasis law, and Option makes the input stage working with lower amplitude signals. 8.2 - Audio Level with 50s De-emphasis Remark : Refering to the Section 3.3.2, the audio level and When the second solution is implemented, the the actual roll-off frequency of the 50s depends baseband signal is selected by the de-emphazed on an external filter and an internal resistor Rint. video position of the switch matrix table.
3 x 1N4148 82k 22pF 180k 22pF
AN838-38.EPS
35/37
STV0042/STV0056 APPLICATION NOTE
8 - POTENTIAL PROBLEM AND SUGGESTED SOLUTIONS (continued) Figure 39 : Back-up Solution, when some intermodulation noise is noticed
12V 1.5k 300
1
2
LPF
To clamp
1k
1k
100pF 1k L8 TUNER R49 C55 To VIDIN TUNER 1k VID IN VIDEEM1
3.9k
UNCL DEEM
B-BAND 470pF 220
ex : L8 = 2.7H C55 = 100F R49 = 680
8.4 - 22kHz Tone Crosstalk on VIDEEM1 This potential problem and the suggested solution are mentioned in Sections 3.1.1.3, 3.4.4 and 3.5.6. 8.5 - Audio S/N, Influence of the Video Pattern The S/N measurement conditions do not always describe which video pattern has to be used simultaneously with the audio. When a color bar is displayed, the unweighted S/N is better than 63dB. However when using patterns such as multiburst the S/N becomes lower (about 58dB). If it is required to get better than 63dB under this condition, then it is recommanded to used a more complex filter between the tuner and FM IN. Figure 40 gives an example of a more sophisticated filter. 8.6 - STV0042 : Audio Level Modulation when Evaluating with a Signal Generator Refering to the block diagram of STV0042 noise reduction (see Figure 19 of Section 3.3.1). The signal at SUMOUT is the sum of the left and right
signals. When using signal generators it may happen that left and right signals are exactly in opposite phase or slowly beat. In such a case the SUMOUT signal becomes null and consequently the signal at PKOUT becomes low and the output amplifier have a low frequency response. The final result is an amplitude modulation of the audio output signal. This is a very specific case which may happen only when using signal generator and which likely never occurs in reality. 8.7 - Video Output, Limited Slew-rate The video output stages of STV42/56 are internally pulled down with 1.3mA current sources. This pulling down source may not be enough when the external load becomes highly capacitive (Cload 20pF). SGS-THOMSON will correct this effect. In the meantime, when this problem is faced, pulldown resistors ( 2.2k) can be connected between the ground and the video outputs.
Figure 40 : More SophisticatedVideo Rejection Filter
15pF 470 TUNER 5.6H 5.6H 680pF 82H 60pF 1k 1nF 22H 1nF To FMIN
AN838-40.EPS
36/37
AN838-39.EPS
STV0042/STV0056 APPLICATION NOTE
9 - ANNEXE : PLL DEMODULATOR THEORETICAL ANALYSIS 9.1 - Modelization of the STV42/56 FM Demodulator A part from the AGC section, the FM demodulator of the STV42/56 can be modelized as a conventional PLL structure (see Figure 41). Figure 41
KD
I
9.2 - Frequency Response of the PLL Demodulator In standard applications the STV42/56 is used with the following external loop filter (left channel). Figure 42
DET R33 R32 C37
AN838-41.EPS AN838-42.EPS
F(p)
Vo
VREF
VCO Ko K
The closed loop gain of the PLL is : VO 1 (p) = K KO I 1+ 1 p K KO KD (1)
With this type of filter the PLL closed loop gain becomes a second order low pass filter which can be compared to the following : VO 1 (p) = p I 1+2 + O O : damping factor O : resonnating frequency (for = 0) Comparing relations (1) and (2), the damping factor and the resonnating frequency can be calculated as follows :
N=
(2)
I = 2 ( f(t) - fO ) in radians VO : peak-to-peak output voltage K : modulation depth coefficient (R05 B0-5) Ko : VCO slope (in radians per volt) KD : Phase detector gain (volt per radian)
Remark : The phase detector gain can be determined as follows :
KD = DETH R33 sin (left channel) R36

1
K KO KD ( R33 + R32 ) C37
: the angle difference between incoming signal and the VCO The relation (1) shows that the DC gain of the PLL is : GDC = 1 K KO
=
K KO KD ( R 33 + R32 ) C37
+ R82

K KO KD R33 + R32
9.3 - Lock Range and Capture Range Lock Range : L = KO K KD Capture Range : C
Typically the STV42/56 has been designed with : KO = 2.89 106 radians/volt

L ( R33 + R32 ) C37
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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