View MN662785TBUC_323464.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LSI 6 for C 5T pa C MNs 6278omBUct Disc/CD-RO M Player
MN662785TBUC
1. TYPE
Signal processing integrated circuit for CDs (Compact Discs)
2. OVERVIEW
MN662785TBUC is a signal processing IC for CDs. It incorporates optical servo (focus, tracking, and traverse servos) processing function, digital signal processing function (EFM demodulation and error correction), digital servo processing function for spindle motor, anti-shock memory control function for 16M, 4M, or 1M DRAM in compression or decompression mode available to disc rotation synchronous playback (jitter-free), a digital filter, and D/A converter. All the processing functions after the head amplifier (RF amplifier) are incorporated into a single chip.
3. FUNCTIONS AND FEATURES
(Optical servo) Focus (Fo), tracking (Tr), and traverse (TRV) servos Automatic adjustment functions (Fo/Tr gain, Fo/Tr offset, Fo/Tr balance) On-chip PWM for drive output Provided with a countermeasure for dropout Provided with anti-shock function Provided with track cross detection function (Digital signal processing) Containing DSL and PLL Provided with a frame synchronous detection/protection/interpolation Subcode data processing Q-data CRC check On-chip Q-data register On-chip CD-TEXT-data register CIRC error correction C1 decoder double error correction C2 decoder triple error correction On-chip de-interleaving 16K RAM Audio data interpolation processing 4-sampling linear interpolation and previous value hold Soft muting Digital attenuation (256 levels) (- , -48 dB to 0 dB, 256 levels) Soft attenuation (256 levels) (- , -48 dB to 0 dB, 256 levels) Digital audio interface (EIAJ format), IEC format Compatible with digital audio interface when anti-shock memory control is turned on. Compatible with bilingual operation when anti-shock memory control is turned on. (Spindle motor servo) CLV digital servo Provided with servo gain selection function Provided with shaft loss compensation setting function Provided with forced acceleration/deceleration output level setting function
Public ation date: J une 2002
SDD00026AEM
1
MN662785TBUC
(Audio circuit) 8x-oversampling digital filter On-chip low-voltage op amp Bass boost filter, high-band notch filter, and surround function
(Anti-shock memory controller) ADPCM 4-bit compression or expansion mode/decompression full 16-bit mode External DRAM selectable 16M DRAM (4M 4 bits) 1 4M DRAM (1M 4 bits) 2 4M DRAM (1M 4 bits) 1 1M DRAM (256K 4 bits) 2 1M DRAM (256K 4 bits) 1 (Others) Disc rotation synchronous playback (jitter-free) mode
SDD00026AEM
2
MN662785TBUC
4. PIN ASSIGNMENT
80-pin qua d fla t pa c ka ge ( LQF P 080-P -1414A)
TX EXT2/IBCLK/EFM EXT1/ILRCK/VDET/PCK EXT0/ISRDATA/SRMON2 IPFLAG/CLVS FLAG/SRMON1 TMOD2 TMOD1 FSEL AVDD1 OUTR AVSS1 OUTL AVSS2 AVDD2 VCOF PLLF DRF DSLF ADPVCC 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
MCLK MDATA MLD BLKCK/DQSY1 SQCK/BCLK1/TXTCLK1 SUBQ/LRCK1/TXTDAT1 DMUTE/SRDATA1 STAT NRST SPPOL PMCK SMCK SUBC/TXTDAT2/SRDATA2 SBCK/TXTCLK2/LRCK2 NCLDCK/DQSY2/BCLK2 NTEST X1 X2 DVDD1 DVSS1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
IREF ARF LD O N BDO NRFDET OFT RFENV TE FE CSEL TBAL FBAL FOM FOP TRM TRP TRVM TRVP SPOUT DVDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DVDD3V D0 D1 NW E NRAS D2 D3 NCAS0 NCAS1 A8 A7 A6 A5 A4 A9 A0 A1 A2 A3 DVSS2
SDD00026AEM
3
MN662785TBUC
5. BLOCK DIAGRAM
SUBQ/LRCK1/TXTDAT1
MDATA MCLK/TXTCLK2 MLD
CSEL X1 X2 FSEL PMCK IPFLAG/CLVS SMCK
AVDD2
DVDD2 DVSS2 DVDD1 DVSS1 NRST SERVO TIMING GENERATOR NTEST TMOD1 TMOD2 EXT0/ISRDATA/SRMON2 EXT1/ILRCK/VDET/PCK EXT2/IBCLK/EFM TIMING GENERATOR DSL PLL VCO SUBCODE/CD-TEXT BUFFER
AVSS2
STAT
SQCK/BCLK1/TXTCLK2
ARF DRF IREF DSLF PLLF VCOF
MICROCOMPUTER INTERFACE
EFM SYNC
DEMODULATION INTERPOLATION DEMODULATION
SUBCODE
SUBC/SSYNC/ TXTDAT2/SRDATA2 SBCK/64FS/ TXTCLK2/LRCK2 NCLDCK/DQSY2/ BCLK2
BLKCK/DQSY1
CLV INPUT PORT BDO NRFDET OFT SERVO DIGITAL SERVO CIRC ERROR CORRECTION DEINTERLEAVE 16K SRAM
FLAG/SRMON1
INTERPOLATION
8x-OVERSAMPLING DIGITAL FILTER A/D CONVERTER FE TE RFENV ADPVCC SOFT MUTING OUTPUT PORT ANTI-SHOCK MEMORY PWM+ CHARGE PUMP PWM CONTROLLER 1-bit DAC DIGITAL DEEMPHASIS DIGITAL ATTENUATION SOFT ATTENUATION DIGITAL AUDIO INTERFACE
TX
PWM (L)
PWM (R) L.P.F
L.P.F
DMUTE/SRDATA1
OUTR
OUTL
FBAL TBAL LDON FOM FOP TRM TRP TRVM TRVP SPOUT SPPOL DVDD3V A9 to A0 D3 to D0 NCAS0 NCAS1 NRAS NWE
SDD00026AEM
AVDD1 AVSS1
4
MN662785TBUC
6. PIN DESCRIPTIONS
No. 1 2 3 4 5 6 7 8 9 Symbol DVDD3V D0 D1 NW E NR AS D2 D3 NC AS 0 NC AS 1 I/O I I/O I/O O O I/O I/O O O Function P owe r supply for DR AM inte rfa c e ( P ins 2 to 19) DR AM da ta I/O 0 DR AM da ta I/O 1 DR AM write e na ble signa l output DR AM R AS c ontrol signa l output DR AM da ta I/O 2 DR AM da ta I/O 3 DR AM C AS c ontrol signa l output 0 DR AM C AS c ontrol signa l output 1 ( W he n two 1M or 4M DR AMs a re in use ) DR AM a ddre ss signa l output 10 ( W he n 16M DR AM is in use ) DR AM a ddre ss signa l output 8 DR AM a ddre ss signa l output 7 DR AM a ddre ss signa l output 6 DR AM a ddre ss signa l output 5 DR AM a ddre ss signa l output 4 DR AM a ddre ss signa l output 9 DR AM a ddre ss signa l output 0 DR AM a ddre ss signa l output 1 DR AM a ddre ss signa l output 2 DR AM a ddre ss signa l output 3 Ground for digita l c irc uits P owe r supply for digita l c irc uits S pindle motor drive signa l output
10 11 12 13 14 15 16 17 18 19 20 21 22
A8 A7 A6 A5 A4 A9 A0 A1 A2 A3 DVSS2 DVDD2 S P OUT
O O O O O O O O O O I I O
SDD00026AEM
5
MN662785TBUC
No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Symbol TR VP TR VM TR P TR M F OP F OM F B AL TB AL C S EL FE TE RFENV OFT NRFDET BDO LDON ARF IREF ADPVCC DSLF DRF PLLF VCOF AVDD2 AVSS2
I/O O O O O O O O O I I I I I I I O I I I O I O O I I Tra ve rse drive signa l output Tra ve rse drive signa l output Tra c king drive signa l output Tra c king drive signa l output F oc us drive signa l output F oc us drive signa l output
Function ( + side output) ( - side output) ( + side output) ( - side output) ( + side output) ( - side output)
F oc us ba la nc e a djustme nt signa l output Tra c king ba la nc e a djustme nt signa l output Te st pin F oc us e rror signa l input Tra c king e rror signa l input R F e nve lope signa l input Off-tra c k signa l input R F de te c tion signa l input Dropout signa l input La se r ON signa l output R F signa l input R e fe re nc e c urre nt input A/D c onve rte r re fe re nc e volta ge input DS L loop filte r DS L bia s P LL loop filte r Jitte r-fre e VC O loop filte r P owe r supply for a na log c irc uits ( F or DS L, P LL, VC OF , DR F , a nd A/D c onve rte r) Ground for a na log c irc uits ( F or DS L, P LL, VC OF , DR F , a nd A/D c onve rte r)
6
Norma l: H
H Off tra c k L De te c t H Dropout H ON
SDD00026AEM
MN662785TBUC
No. 48 49 50 51 52 53 54 55 56
Symbol OUTL AVSS1 OUTR AVDD1 F S EL TMOD1 TMOD2 F LAG/S R MON1 IP F LAG/C LVS
I/O O I O I I I I O O L-c h a udio output Ground for a na log c irc uits R -c h a udio output
Function ( R e fe r to Note in pa ge 3) ( F or a udio output sta ge ) ( R e fe r to Note in pa ge 3)
P owe r supply for a na log c irc uits ( F or a udio output sta ge ) Te st pin Norma l: H ( Noise filte r is se le c te d by using a c omma nd.) Norma l: L Norma l: L
P in mode se le c tion input 1 P in mode se le c tion input 2
F la g signa l output / S e ria l monitor signa l output 1 ( Eva lua tion de dic a te d monitor) C omma nd se le c tion Inte rpola tion fla g signa l output H: Inte rpola tion S pindle se rvo pha se sync signa l output H: C LV L: R ough se rvo Expa nsion port 0 I/O S e ria l a udio da ta input ( Exte rna l I/O mode ) 64fs S e ria l monitor signa l output 2 ( Eva lua tion de dic a te d monitor) Expa nsion port 1 I/O L or R disc rimina tion signa l input ( Exte rna l I/O mode ) H: L-c h a udio da ta L: R -c h a udio da ta Vibra tion de te c tion fla g signa l output P LL e xtra c tion c loc k output fPCK = 4.321 MHz ( Norma lspe e d pla yba c k) Expa nsion port 2 I/O B it c loc k input ( Exte rna l I/O mode ) 64fS EF M monitor signa l
57
EXT0/ IS R DATA/ S R MON2 EXT1/ ILR C K/ VDET/P C K
I/O
C omma nd se le c tion
58
I/O
C omma nd se le c tion
59
EXT2/ IB C LK/EF M TX MCLK MDATA MLD B LKC K/ DQS Y1 S QC K/ B C LK1/ TXTC LK1 S UB Q/ LR C K1/ TXTDAT1
I/O O I I I O I/O
C omma nd se le c tion
60 61 62 63 64 65
Digita l a udio inte rfa c e signa l output Mic roc ompute r c omma nd c loc k signa l input Mic roc ompute r c omma nd da ta signa l input Mic roc ompute r c omma nd loa d signa l input B loc k c loc k signa l output C D-TEXT sync signa l output L Loa d
fBLKCK= 75 Hz ( Norma l-spe e d pla yba c k) fDQSY= 300 Hz ( Norma l-spe e d pla yba c k)
External clock input for subcode Q register Bit clock output CD-TEXT data read clock input 1 S ubc ode Q-da ta output L or R disc rimina tion signa l output H: L-c h a udio da ta L: R -c h a udio da ta C D-TEXT da ta output 1
66
O
SDD00026AEM
7
MN662785TBUC
No. 67
Symbol DMUTE/ S R DATA1
I/O I/O
Function Muting input H Mute ( Muting of OUTL, OUTR , a nd TX outputs) S e ria l a udio da ta output S ta tus signa l output ( C R C , R ES Y, C LVS , NTTS TOP , S QOK, F LAG6, S ENS E, NF LOC K, NTLOC K, B S S EL, ZDET, S UB Q da ta output, C D-TEXT da ta output, Anti-shoc k me mory c ontrolle r re a ding da ta , Disc rota tion spe e d da ta ) R e se t input L R e se t
68
S TAT
O
69 70 71 72 73
NR S T S P P OL PMCK SMCK SUBC/ SSYNC/ TXTDAT2/ SRDATA2 SBCK/ TXTCLK2/ LRCK2
I O O O O
S pindle motor powe r c ontrol signa l output ( P C ) 88.2-kHz clock signal output 4.2336-MHz clock signal output 8.4672-MHz clock signal output Subcode output CD-TEXT data output Serial audio data output Subcode output clock input CD-TEXT data read clock input 3 L or R discrimination signal output (External output mode) H: L-ch audio data L: R-ch audio data Frame sync signal output fCLDCK=7.35 kHz (Normal-speed playback) CD-TEXT output fDQSY =300 Hz (Normal-speed playback) Bit clock output Te st pin Crystal oscillator input pin Crystal oscillator output pin P owe r supply for digita l c irc uits Ground for digita l c irc uits Norma l: H f 33.8688 MHz f 33.8688 MHz
74
I
75
NCLDCK/ DQSY2/ BCLK2
O
76 77 78 79 80
NTEST X1 X2 DVDD1 DVSS1
I I O I I
SDD00026AEM
8
MN662785TBUC
7. FUNCTION DESCRIPTION (Table of contents)
7-0 Contents of functions amended from MN662780 P10
7-1 Microcomputer interface List of commands vs. control items List of microcomputer commands Initial setting Data setting for servos Data setting for signal processing section Data setting for anti-shock memory controller Automatic adjustment
P 12 P 13 P 14 P 18 P 19 P 46 P 55 P 60
7-2 I/O timing Subcode interface Serial data output Serial data input
P 62 P 61 P 62 P 63
SDD00026AEM
9
MN662785TBUC
7-0 Contents of functions amended from MN662780
(1) Digital servo section Focus and tracking servos' sampling frequency : 88.2 kHz Timings of initial settings Spindle forced acceleration/deceleration output level setting KICK pulse level setting (KICK2) for servo pull-in operation abolished Zero-cross reference brake mode abolished Fixed noise rejection mode during braking operation of tracking Software reset function added Change of servo parameter exponent part format (FEXP, TEXP) (2) Digital filter (DF) and D/A converter (DAC) sections DF and DAC sections operating clock selectable between normal-speed and 2x-speed modes DF section 8x-oversampling operation Low-voltage op amp Change of low-band boost filter characteristics (Low band: 3 dB 4.5 dB) (3) Signal processing section 33.8688-MHz system clock Function to select a microcomputer interface input noise filter with a command Clock selection function for microcomputer (4 MHz, 8 MHz) Function to select current rate of PLL frequency comparison and phase comparison Function to select output width when detecting 12T or 5T Subcode Q data adding function in control of digital audio interface output when the anti-shock memory function is in use Compatible with bilingual operation when anti-shock memory function is in use Compatible with 2x-speed digital audio interface output Muting of data output from anti-shock memory controller Audio data 0 detection flag function (ZDET signal)
SDD00026AEM
10
MN662785TBUC
(4) Anti-shock memory controller (5) The whole system Digital servo's D/A converter output abolished by PWM charge pump current output of FBAL, TBAL, and DSLF2 No VREF pin No DSLF2 pin Serial input/output interfaces added No PWMCK and TRVSTP pins No peak detection circuit No variable pitch function CD-TEXT mode interface added IPFLAG pin (pin 56) added EFM signal output added PCK signal output added VDET signal output added Added function to stop A/D converter operation with reference current shut-off command Oscillation stop mode added A/D converter reference voltage input pin (ADPVCC: pin 41) added No CD-TEXT modes 1 and 3
SDD00026AEM
11
MN662785TBUC
7-1. Microcomputer interface
Each mode can be set by inputting the 16-bit data (D15 to D0) and 8-bit command (B7 to B0) starting from the MSB in 3 inputs of MDATA, MCLK, and MLD at the timing as shown in Figure 7-1-1.
MSB MDATA D15 D14 D13
LSB D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0
MCLK
MLD
Note
Data is determined at the "L" level of MLD. MDATA, MCLK, and MLD are invalid while NRST is "L." All commands are initialized by setting NRST to "L." While MLD is set to "L," MCLK will be canceled if it rises. Set 0 to any bit which is input through the MDATA input with no functional specification assigned to the bit. Timing
MDATA
B2
B1
B0
MCLK
MLD
300 ns 300 ns 300 ns 300 ns min. min. min. min. Figure 7-1-1
300 ns min.
500 ns 300 ns min. min. 5 s max.
SDD00026AEM
12
MN662785TBUC
7-1 (1) List of commands vs. control items
Table 7-1-1 Command (HEX) (B7 to B0) 1x 4x 7x 8x 9x Ex Fx
Control Target
Block
Spindle servo Various signal processing STAT output Anti-shock memory write command Anti-shock memory read command
Signal processing section Anti-shock memory controller
Focus, tracking, and traverse servos Optical servo Initial setting, automatic adjustment, and access section
SDD00026AEM
13
MN662785TBUC
7-1 (2) List of microcomputer commands
Set 0 to any bit which is indicated by X in the following list of commands with no functional specification assigned to the bit. (1) Commands for signal processing section No data length setting is required wherever
Control target Spindle Control 1 Data length Command (B7 to B0) Symbol TTOFF TTO N STOP ACC BRAKE PLAY
appears in the following table.
Function ( Turntable OFF Turntable ON Free-running Acceleration Deceleration Normal play
Table 7-1-2 (1)
Reference page
Setting at reset)
Various signal processing control
16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits
Audio control Digital audio interface control Attenuation control Spindle control PWM output control (Optical servo system) Playback speed control Dropout control PLL control I/O control 1 DSL unbalance compensation control I/O control 2
46 47 48 48 49 50 50 51 52 52 53
SDD00026AEM
14
MN662785TBUC
Table 7-1-2 (2)
Control target STAT pin output Data length Command (B7 to B0) Symbol Function ( Setting at reset)
Reference page
3 bits
STAT output CRC STAT output RESY STAT output CLVS STAT output NTTSTOP STAT output SQOK STAT output switching STAT output BSSEL STAT output FCLV STAT output SSTAT STAT output SUBQ (SQCK sync) STAT output SUBQ (MCLK sync) STAT output ZDET (Zero data detection) STAT output SPEED (Disc rotation speed)
54 54 54 54 54 54 54 54 54 54 54 54 54
(2) Commands for anti-shock memory controller No data length setting is required wherever
Control target Write command Data length 8 bits 4 bits 4 bits 8 bits 8 bits Command (B7 to B0)
appears in the following table.
Function ( Setting at reset)
Table 7-1-2 (3)
Reference page
Symbol
Memory system command Expansion I/O port I/O setting Expansion I/O port output data setting Option setting Option setting TX Q-data input Status 1 reading (Read data length: 8 bits) Status 2 reading (Read data length: 8 bits) Remaining enabled data check (Read data length: 16 bits) Expansion I/O port input data setting (Read data length: 8 bits)
55 55 56 56 56 57 58 58 59 59
Read command
SDD00026AEM
15
MN662785TBUC
(3) Commands for optical servo section No data length setting is required wherever
Control target Optical servo
appears in the following table. Table 7-1-2 (4)
Data length
Command (B7 to B0) Symbol STB DDT TO F PLY
Function ( Standby Reserved Disc detection Fo ON, Tr OFF Fo ON, Tr ON Reserved Reserved
Setting at reset)
SENSE signal OFT FESL FESL OFT
Reference page
Traverse servo
TV S TV F TV R TV P
Traverse stop Reserved Traverse forward feed Traverse reverse feed Traverse play Stopping access operation Kick Track count move Data write Data read Await initialization cancel command Reserved Focus balance adjustment Stopping automatic adjustment Offset adjustment (focus, tracking) Reserved Tracking balance adjustment Focus rough gain adjustment Tracking rough gain adjustment Focus fine gain adjustment Tracking fine gain adjustment
Unchanged Unchanged Unchanged Unchanged NACEND NACEND NACEND N W TEN D DATA
Access 16 bits 16 bits Data setting Initial setting Automatic adjustment 16 bits 8 bits
ACA KICK TCNT DTMS DTSM SYS
44 44 19 20 18
ABC1 ADA AOC ABC2 AGC1 AGC2 FAGC TA G C
NAJEND NAJEND NAJEND NAJEND NAJEND NAJEND NAJEND NAJEND
60 60 60 60 60 60 60 60
SDD00026AEM
16
MN662785TBUC
SENSE signal SENSE signal can be monitored through STAT pin. The meaning of SENSE signal varies with the input command. The meanings are described below. Off-track input signal is output as it is. It is set to "H" when the absolute value of the focus error signal amplitude exceeds 30 LSBs by executing the disc detection command. It is set to "L" when the access terminates and the pull-in operation of the tracking servo starts. It is set to "L" when automatic adjustment terminates. It is set to "L" when data write terminates normally. The contents of the RAM of the specified address is output beginning with MSB by inputting MCLK a minimum of 25 s after MLD is set to "L" with the data read command, DTSM, sent out for data reading. Refer to Figure 7-1-4.
OFT FESL
NACEND
NAJEND NWTEND DATA
MDATA
Disc detection
Fo ON, Tr ON
Fo fine AGC
KICK
MLD FESL OFT NAJEND NACEND
SENSE (STAT pin) End of automatic adjustment Figure 7-1-2 Switching of SENSE output End of KICK
SDD00026AEM
17
MN662785TBUC
7-1 (3) Initial setting
After clearing NRST, the SENSE signal is set to "H" and the system is in the standby status for the SYS command. After 75-ms continuous standby status for the SYS command, the STANDBY mode starts. If the SYS command is sent during the period of 75-ms continuous standby status for the SYS command, however, the SENSE signal is set to "L" and the STANDBY mode starts immediately. In the STANDBY mode, the system is ready for receiving the DTMS and DTSM commands.
Table 7-1-3 Data (D7 to D0)
D7 D6 D 5 D4 D3 D2 D1D0
Address (HEX) Command (HEX) (A7 to A0) (B7 to B0)
XX F5
Function
SYS command
75 ms max. NRST
SENSE (STATpin)
MDATA
SYS
Other than SYS
MLD Figure 7-1-3 Timing chart in initial setting
SDD00026AEM
18
MN662785TBUC
7-1 (4) Data setting for servos
[1] Data write (DTMS) Various features can be achieved by writing various characteristics of the optical servo system from an external microcomputer to this IC. DTMS command is used to write the data such as servo parameters. (Application) (A) Setting of automatic adjustment value (B) Setting of the optical servo loop characteristics including the characteristics for anti-vibration (C) Setting of gain crossover for the optical servo loop (D) Mode selection for anti-vibration (E) Various system settings (F) Various settings for optical servo system (G) Access command setting
(MDATA format) D D6 A D A D A D A D A D A D A A : Data : Address (Label specified) : Command (DTMS)
Note) Use the DTMS command in the STANDBY or PLAY mode. If you write data successively, wait at least 25 s before each data writing so that the microcomputer finishes DSP processing and becomes ready for writing next data.
SDD00026AEM
19
MN662785TBUC
[2] Data read (DTSM) This IC can read out the parameters such as automatic adjustment results of the optical servo with the DTSM command. (MDATA format) A7 A6 A5 A4 A3 A2 A1 A0 Address (Label specified) Command (DTSM) (Data output format) Input an address and command, and after a lapse of at least 25 s since setting MLD to "H" from "L," input MCLK, thus enabling to read data from STAT pin. (SENSE output)
MDATA
DTSM
MLD
MCLK
SENSE (STAT pin)
Indefinite
Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0
Min. 25 s Figure 7-1-4 Timing chart for reading data Note) Perform either in the STANDBY or PLAY mode.
SDD00026AEM
20
MN662785TBUC
(List of DTMS/DTSM addresses) Table 7-1-4 (1)
Address (HEX) (A7 to A0)
Label FG0 FEXP0 FBAL FOFS TG 0 TEXP0 TBAL TOFS FC FR TC TR FC2 FR2 TC2 TR2 GSET VSET SET0 SET1 SET2 FES TES CRAM2 SD KS TV G CRAM3 CRAM4 SET3 DED0
Application Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus gain automatic adjustment value in normal-speed mode (for setting use) Focus balance automatic adjustment value Focus offset automatic adjustment value
Tracking gain automatic adjustment value in normal-speed mode (for setting use) Tracking gain automatic adjustment value in normal-speed mode (for setting use)
Reference page
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 16 17 18 19 1A 1B 1C 1D 1E 1F
Tracking balance automatic adjustment value Tracking offset automatic adjustment value Focus phase compensation constant Focus low-band compensation constant Tracking phase compensation constant Tracking low-band compensation constant Focus phase compensation constant at vibration Focus low-band compensation constant at vibration Tracking phase compensation constant at vibration Tracking low-band compensation constant at vibration Gain crossover setting Mode selection for anti-vibration System settings System settings System settings Focus gain disturbance amplitude Tracking gain disturbance amplitude Focus search amplitude Search direction Kick speed / Kick brake timing Traverse gain constant in tracking brake operation Fail-safe value for tracking servo Tracking balance disturbance adjustment value System settings Traverse drive dead-zone
23 23 23 23 23 23 23 23 25 25 25 25 25 25 25 25 27 28 30 31 32 23 23 38 38 39 40 39 39 33 41
SDD00026AEM
21
MN662785TBUC
Table 7-1-4 (2)
Address (HEX) (A7 to A0)
Label ECM SVOFS FG2 FEXP2 SPG0 TG 2 TEXP2 TRVG0 GLF1 GLF2 GLF3 GLF4 GLT1 GLT2 GLT3 GLT4 SETKC SETTB KCCNT FMAX FMIN KICK TRV VSLT SETV1 SETV2
Application Spindle forced acceleration/deceleration output level setting Spindle shaft loss compensation output level setting Focus gain constant mantissa part at vibration (for setting use) Focus gain constant exponent part at vibration (for setting use) Spindle gain setting Tracking gain constant mantissa part at vibration (for setting use) Tracking gain constant exponent part at vibration (for setting use) Traverse gain setting Focus gain constant upper limit mantissa part Focus gain constant upper limit exponent part Focus gain constant lower limit mantissa part Focus gain constant lower limit exponent part Tracking gain constant upper limit mantissa part Tracking gain constant upper limit exponent part Tracking gain constant lower limit mantissa part Tracking gain constant lower limit exponent part Track count noise elimination width System settings Inverted pulse width with tracking brake and servo control turned on Initial accelerating time with tracking brake turned on FE signal maximum value (8-bit 2's complement) FE signal minimum value (8-bit 2's complement) KICK output level Traverse output level Vibration detecting level mantissa part Soft VDET parameter setting 1 Soft VDET parameter setting 2 Focus and tracking gains setting for normal gain Focus and tracking gains setting for forced gain-up Software reset
Reference page
2B 2C 2D 2E 2F 35 36 37 39 3A 3B 3C 3D 3E 3F 40 49 4A 4B 6C 6D 78 79 7B 7C 7D 80 81 AA
45 45 29 29 45 29 29 43 43 43 43 43 43 43 43 43 41 36 42 42
42 42 35 34 34 37 37 37
Do not write illegal data in any of the above addresses, otherwise the existing data in the address is overwritten and the operation of this IC is not guaranteed.
SDD00026AEM
22
MN662785TBUC
(A) Setting of automatic adjustment value FG0 FEXP0 FBAL FOFS FES TES (Focus gain mantissa part) (Focus gain exponent part) (Focus balance adjustment value) (Focus offset adjustment value) (Disturbance amplitude in focus gain adjustment) (Disturbance amplitude in tracking gain adjustment) , , , , TG0 TEXP0 TBAL TOFS (Tracking gain mantissa part) (Tracking gain exponent part) (Tracking balance adjustment value) (Tracking offset adjustment value)
Table 7-1-4 (3) Data (D7 to D0)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0) 00 01 F2
Function
Focus gain constant (FG0) (8-bit mantissa) (1 to 255) Focus gain constant (FEXP0) (8-bit exponent) (0 to 7) (Note) (Focus gain constant = mantissa / 28-FEXP0) Focus balance constant (FBAL) (8-bit 2' s complement) ( 128 to +127) Focus offset constant (FOFS) (8-bit 2' s complement) ( 128 to +127) Tracking gain constant (TG0) (8-bit mantissa) (1 to 255) Tracking gain constant (TEXP0) (8-bit exponent) (0 to 7) (Note) (Tracking gain constant = mantissa / 28-TEXP0) Tracking balance constant (TBAL) (8-bit 2' s complement) ( 128 to +127) Tracking offset constant (TOFS) (8-bit 2' s complement) ( 128 to +127) Disturbance amplitude in focus gain adjustment (FES) (1 to 127) Disturbance amplitude in tracking gain adjustment (TES) (1 to 127)
Setting at reset 202 2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
02 03 04 05
0 0 150 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
06 07 16
0 0 85
D7 D6 D5 D4 D3 D2 D1 D0
17
85
(Note) The operation may fluctuate when FEXP0 or TEXP0 setting is 5 or more.
FEXP0/TEXP0 corresponding setting table
MN662783 MN662785
128 1
64 2
32 3
16 4
SDD00026AEM
23
MN662785TBUC
(B) Setting of the optical servo characteristics including the characteristics for anti-vibration Gain constant Focus gain mantissa part FG Tracking gain mantissa part Focus gain exponent part FEXP Tracking gain exponent part
TG TEXP
Phase compensation and low-band compensation constant Focus phase compensation constant FC Tracking phase compensation constant TC Focus low-band compensation constant FR Tracking low-band compensation constant TR The above four constants can be set by writing 8-bit data (0 to 127) directly with the microcomputer command. Configuration
K
Z -1 R G
+ +
Z -N C
+
fs of the focus system: 88.2 kHz fs of the tracking system: 88.2 kHz fs of the filter for low-band compensation: 44.1 kHz
G (Z)
G
1 1 Z
1
R
(1
C
Z)
N
G=
TG 28-TEXP TR 2
15
or
FG 28-FEXP FR 2
15
C=
TC 128
or
FC 128
R=
or
K=1
N in Z
N
can be replaced with : 2 or 1 (by setting bit 1 of SET0) in case of the focus system. 1 in case of the tracking system.
SDD00026AEM
24
MN662785TBUC
Setting of loop filter constants Table 7-1-4 (4) Data (D7 to D0)
D7 D6 D7 D6 D7 D6 D7 D6 D5 D4 D5 D4 D5 D4 D5 D4 D3 D3 D3 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0
Address Command (HEX) (HEX) (B7 to B0) (A7 to A0)
08 09 0A 0B F2
Function
Focus phase compensation constant : FC (8 bits) (1 to 127) Focus low-band compensation constant : FR (8 bits) (1 to 127) Tracking phase compensation constant: TC (8 bits) (1 to 127) Tracking low-band compensation constant : TR (8 bits) (1 to 127) Focus phase compensation constant at vibration : FC2 (8 bits) (1 to 127) Focus low-band compensation constant at vibration : FR2 (8 bits) (1 to 127) Tracking phase compensation constant at vibration : TC2 (8 bits) (1 to 127) Tracking low-band compensation constant at vibration : TR2 (8 bits) (1 to 127)
Setting at reset 117 64 122 64
D7 D6 D7 D6 D7 D6 D7 D6
D5 D4 D5 D4 D5 D4 D5 D4
D3 D3 D3 D3
D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0
0C 0D 0E 0F
117 64 122 64
SDD00026AEM
25
MN662785TBUC
Setting of the traverse filter Configuration
-1 Low-band Component of TE
+ +
+ +
Dead-Zone Amp
Traverse filter sampling frequency
11.02 kHz
K=1 - 2-14 R= 2 -10
There are three types of dead-zone amps; type A, type B, and type C. They can be selected by setting SET2. The dead-zone width can be specified by setting DED0.
SDD00026AEM
26
MN662785TBUC
(C) Setting of gain crossover for optical servo loop Before performing focus and tracking automatic adjustments, gain crossover after automatic adjustment can be determined by writing data to the label name GSET (address: 10h) according to the table below. In the automatic gain adjustment, disturbance is input to the servo loop, and gain is increased or decreased according to the GSET setting after adjusting the gain so that the feedback gain at the disturbance frequency becomes 0 dB (gain crossover is equal to the disturbance frequency).
(Setting for focus system) Data (D7 to D0)
D3 D2 01 01 01 01 00 00 00 00 11 11 11 11 10 10 10 10 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 7-1-4 (5)
Address (HEX) Command (HEX) (A7 to A0) 10 F2
Function (
: Setting at reset)
Focus gain at the disturbance frequency of 750 Hz Approx. value 3.92 dB Approx. value 3.36 dB Approx. value 2.80 dB Approx. value 2.24 dB Approx. value 1.68 dB Approx. value 1.12 dB Approx. value 0.56 dB Approx. value 0 dB Approx. value 1.05 dB Approx. value 2.11 dB Approx. value 3.16 dB Approx. value 4.21 dB Approx. value 5.27 dB Approx. value 6.32 dB Approx. value 7.37 dB Approx. value 8.43 dB
(Setting for tracking system) Data (D7 to D0)
D7 D6 D5 D4 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 Address (HEX) (A7 to A0) Command (HEX) 10 F2
Table 7-1-4 (6) Function ( : Setting at reset)
Tracking gain at the disturbance frequency of 1 kHz Approx. value 3.92 dB Approx. value 3.36 dB Approx. value 2.80 dB Approx. value 2.24 dB Approx. value 1.68 dB Approx. value 1.12 dB Approx. value 0.56 dB Approx. value 0 dB Approx. value 1.05 dB Approx. value 2.11 dB Approx. value 3.16 dB Approx. value 4.21 dB Approx. value 5.27 dB Approx. value 6.32 dB Approx. value 7.37 dB Approx. value 8.43 dB
SDD00026AEM
27
MN662785TBUC
(D) Setting for anti-vibration (VSET) The gain-up amount and gain-up time can be set when VDET is set to "H." (VDET can be monitored through the EXT1 pin. Refer to 7-1 (5) (I) for details.)
Table 7-1-4 (7) Data (D7 to D0)
D2 0 0 0 0 1 1 1 1 D5 0 0 0 0 1 1 1 1 D7 D6 00 01 10 11 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Address (HEX) Command (HEX) (B7 to B0) (A7 to A0) 11 F2
Function (
: Setting at reset)
Setting of the focus gain-up amount at vibration Scale factor 1.0 (0 dB) Scale factor 1.125 ( 1.0 dB) Scale factor 1.25 ( 1.9 dB) Scale factor 1.375 ( 2.8 dB) Scale factor 1.5 ( 3.5 dB) Scale factor 1.625 ( 4.2 dB) Scale factor 1.75 ( 4.9 dB) Scale factor 2.0 ( 6.0 dB) Setting of the tracking gain-up amount at vibration Scale factor 1.0 (0 dB) Scale factor 1.125 ( 1.0 dB) Scale factor 1.25 ( 1.9 dB) Scale factor 1.375 ( 2.8 dB) Scale factor 1.5 ( 3.5 dB) Scale factor 1.625 ( 4.2 dB) Scale factor 1.75 ( 4.9 dB) Scale factor 2.0 ( 6.0 dB) Setting of the gain-up time at vibration Time 23.2 ms Time 46.4 ms Time 92.9 ms Time 185.8 ms
Note)
The gain-up amount set by VSET is valid only when FC2 or FR2 for the focus system or TC2 or TR2 for the tracking system is written after VSET setting. (No operation is performed to set servo parameters in the anti-vibration mode only by VSET setting.)
SDD00026AEM
28
MN662785TBUC
The gain values can be overwritten when VDET is set to "H." Data (D7 to D0)
D7 D6 D5 D4 D3 D2 D1D0 D7 D6 D5 D4 D3 D2 D1D0 Address ( H EX ) (A7 to A0) 2D 2E Command ( H EX ) (B7 to B0) F2
Table 7-1-4 (8) Function
Setting at reset 202 2
D7 D6 D5 D4 D3 D2 D1D0 D7 D6 D5 D4 D3 D2 D1D0
35 36
Focus gain constant at vibration (FG2) (8-bit mantissa) (1 to 255) Focus gain constant at vibration (FEXP2) (8-bit exponent) (1 to 7) (Focus gain constant = mantissa / 28-FEXP2) Tracking gain constant at vibration (TG2) (8-bit mantissa) (1 to 255) Tracking gain constant at vibration (TEXP2) (8-bit exponent) (1 to 7) (Tracking gain constant = mantissa / 28-TEXP2)
150 1
Note) Be aware that the gain set with VSET applies at the time of fine gain adjustment or writing data to the FC2, FR2, TC2, or TR2.
SDD00026AEM
29
MN662785TBUC
(E) System settings (E)-1 ET0 setting Data (D7 to D0)
D1 01 11 D3 D2 00 01 10 11 1 1 1 1 Address (HEX) Command (HEX) (A7 to A0) (B7 to B0) 12 F2
Table 7-1-4 (9) Function ( : Setting at reset)
Setting the number of Fo loop filter delay stages 2nd-order (Z-2) 1st-order (Z-1) Setting of forced brake operation time OFF ON (5.8 ms) ON (11.6 ms) ON (23.2 ms) Setting of convergence gain during tracking balance adjustment 1/8192 1/4096 1/2048 1/1024
D5 D4 00 01 10 11
1 1 1 1
D6 0 1
1 1
Tracking balance adjustment output Conventional method Inverted polarity
D7 0 1
1 1
TVD output smoothing OFF ON
TVD output Example of the TVD intermittent drive is as follows.
Smoothing OFF
TVD
Smoothing ON
TVD
1.45 ms 1.45 ms 1.45 ms 1.45 ms
SDD00026AEM
30
MN662785TBUC
(E)-2
SET1 setting Table 7-1-4 (10) Data (D7 to D0) Address Command (HEX) (HEX) (B7 to B0) (A7 to A0)
D0 13 F2
Function (
: Setting at reset)
TVD output at the time of kick pulse output in the traverse stop state TVD output No TVD output Pull-in method when turning focus on from off Conventional method High-speed pull-in High-speed kickback ON/OFF ON OFF Focus offset adjustment method With vibration Without vibration Focus offset adjustment method direction (Same as MN66271) direction Note)
D1
D2
D4
D5
D6
D3
Wait time after TCNT 50 ms 100 ms 0 ms 10 ms DAC output limiter (FABC, TABC)
D7
OFF ON
Note) It is recommended to turn off the high-speed kickback function while the anti-shock memory control function is in use.
SDD00026AEM
31
MN662785TBUC
(E)-3 SET2 setting Table 7-1-4 (11) Data (D7 to D0)
D1 D0
Address (HEX) (A7 to A0)
14
Command (HEX) (B7 to B0)
F2
Function (
: Setting at reset)
Traverse dead-zone amp Normal (Type A) side only (Type B) side only (Type C) Tracking offset adjustment wait time None 30 ms Convergence judgement condition for tracking balance adjustment 2 LSBs at TBAL output stage 1 LSB at TE input stage Focus balance adjustment convergence gain 18 14 1 32 1 16 Disc detection, focus rough gain adjustment frequency 5.4 Hz 2.6 Hz Traverse intermittent drive Output enabled Output disabled
D2
D3
D5D4
D6
D7
D ED 0
DED0 2
D ED 0
2
Figure 1 Traverse dead-zone amp Type A
Figure 2 Traverse dead-zone amp Type B
Figure 3 Traverse dead-zone amp Type C
Note) Refer to 7-1 (4) (F)-6 for the DED0 setting.
SDD00026AEM
32
MN662785TBUC
(E)-4
SET3 setting Table 7-1-4 (12) Data (D7 to D0)
D1
Address Command (HEX) (HEX) (B7 to B0) (A7 to A0)
1E F2
Function (
: Setting at reset)
Focus balance adjustment convergence condition 15 LSBs 7 LSBs Cancellation of focus balance adjustment Reset to the initial value at the start of adjustment The adjusting value is on hold Tracking rough gain adjustment time 134 ms 319 ms Focus search mode Conventional mode Amplitude: 1/4 Focus balance adjustment output Positive polarity (Conventional mode) Negative polarity Focus search frequency 1.3 Hz 2.6 Hz
D2
D3
D4
D6
D7
SDD00026AEM
33
MN662785TBUC
(E)-5
Setting of soft VDET (Setting of vibration detection bandpass filter constant) Data (D7 to D0)
Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0)
Table 7-1-4 (13) Function Setting at reset
7C
D3 D2 D1 D0
F2
Setting of HPF constant A SETV1 D3 to D0 (0 to 7)
3
D7 D6 D5 D4
Vibration detection level exponent part n setting SETV1 D7 to D4 (0 to 7)
1
D3 D2 D1 D0
7D
Setting of LPF 2nd stage constant C SETV2 D3 to D0 (0 to 7)
5
D7 D6 D5 D4
Setting of LPF 1st stage constant B SETV2 D7 to D4 (0 to 7)
5
See next page for the setting of vibration detection level.
1/2 TRE Vibration detection signal (VDET)
-1 -1 -1 -1
Detection level
1-2 / 256 HPF
A
1-2 / 256
1-2 / 256
LPF 1st stage LPF 2nd stage
Sampling frequency for filter arithmetic operation: 11.02 kHz
SDD00026AEM
34
MN662785TBUC
(Setting of vibration detection level) Data (D7 to D0)
1 D6 D5 D4 D3 D2 D1 D0 Address Command (HEX) ( H EX ) (B7 to B0) (A7 to A0) 7B F2
Table 7-1-4 (14) Function
Setting of VDET detecting TE threshold level (Mantissa part) VSLT (128 to 255)
Setting at reset 230
Vibration detection level TE 0 Vibration detection level :
VSLT n=SETV1 2n D7 to D4
VDET
SDD00026AEM
35
MN662785TBUC
(E)-6 SETTB setting Table 7-1-4 (15) Data (D7 to D0)
D1 Address ( H EX ) (A7 to A0) 4A Command (HEX) (B7 to B0) F2
Function (
: Setting at reset)
D3
Low-band compensation during tracking brake operation Ye s No DO countermeasure during KICK operation No Ye s Hunting countermeasure for focus balance adjustment No Ye s
D6
SDD00026AEM
36
MN662785TBUC
(E)-7 Forced gain-up setting The IC can be in forced gain-up mode by accessing the data in 81h address. This mode is reset by accessing the data in 80h address.
Table 7-1-4 (16) Data (D7 to D0) Address (HEX) (A7 to A0)
81
Command (HEX) (B7 to B0)
F2
Function
Focus / tracking forced gain-up setting (Data is disabled.) Focus / tracking normal gain (Data is disabled.)
80
Note)
The status of the VDET can be monitored through the EXT1 pin. For details, refer to 7-1 (5) (I). Sending a fine gain adjustment command resets the gain to the normal value.
(E)-8
Software reset Accessing the data in AAh address initializes servo processing. (DSP processing starts from the top address.) Table 7-1-4 (17) Data (D7 to D0) Address (HEX) (A7 to A0)
AA
Command (HEX) (B7 to B0)
F2
Function
Software reset (Data is disabled.)
Note) Only the digital servo section is reset in the software reset operation.
SDD00026AEM
37
MN662785TBUC
(F) Settings for optical servo system Focus search setting Data (D7 to D0)
0 D6 D5 D4 D3 D2 D1 D0
(F)-1
Table 7-1-4 (18) Address (HEX) Command (HEX) (B7 to B0) (A7 to A0)
18 F2
Function
Focus search amplitude (CRAM2) setting 8-bit data (p-p) (40 to 127) Focus search/disc detection direction (SD) setting *FOD decrement FOD increment
Setting at reset 96
D0 0 1 D2 0 1
19
0
Max./Min. FE value teaching during focus search *ON OFF
Note) In focus search/disc detection direction setting, a value of SD will change automatically according to execution of a focus search/disc detection. Consequently, the values written by initial setting and DTMS may have changed when they are read out with DTSM. If you want to perform a focus search/disc detection from the same direction every time, it is necessary to set with DTMS every time before the focus search/disc detection. (Set D0 of SD only.) Check the value of SD with DTSM in the writing operation of SD, and confirm that only the value of set bit of D0 has changed. Note) There will be no focus pull-in operation during the first excitation period (between the first peak and second peak of triangular FOD output) of the IC in focus search operation right after the system starts. The teaching of the maximum and minimum values (FMAX and FMIN) of the FE signal will be, however, conducted. The focus will be pulled in when the S-shape signal is detected after the first excitation period. Once the focus is pulled in, the servo DSP automatically sets SD D2 to 1. Then the focus will be pulled in when the S-curve signal is detected after the first peak of excitation. After offset and focus balance adjustments, SD D2 will be automatically set to 0 and the teaching of FMAX and FMIN will be conducted again.
SDD00026AEM
38
MN662785TBUC
(F)-2
Setting of tracking servo fail-safe value (CRAM3) Address Command (HEX) Data (HEX) (B7 to B0) (D7 to D0) (A7 to A0)
1C F2
Table 7-1-4 (19) Function
Fail-safe value clip level 8-bit data (0 to 127) Low-band component of drive output in the tracking brake mode is clipped at the specified value. Setting at reset 36
0
D6 D5 D4 D3 D2 D1 D0
(F)-3
Setting of disturbance amplitude (CRAM4) in tracking balance adjustment mode Address Command (HEX) Data (HEX) Function (B7 to B0) (D7 to D0) (A7 to A0)
1D F2 Disturbance amplitude (one side) 8-bit data (0 to 127)
Table 7-1-4 (20)
Setting at reset 36
0
D6 D5 D4 D3 D2 D1 D0
Amplitude of the disturbance waves injected in the tracking balance adjustment mode is set. Actual disturbance amplitude is 1/8 CRAM4.
SDD00026AEM
39
MN662785TBUC
(F)-4 KICK setting Data (D7 to D0)
D3 D2 D1 D0
Table 7-1-4 (21) Address Command (HEX) (HEX) (B7 to B0) (A7 to A0)
1A F2
Function
KICK speed (KS) setting 4-bit data (6 to 15) KICK brake timing (OFDE) setting 4-bit data (0 to 15)
Setting at reset 6
D7 D6 D5 D4
0
TE cycle in the speed control mode is determined by the KICK speed setting. KS (D3 to D0) TS TS : 11.3 ms
TE
KICK brake output timing delay time is set in the KICK brake timing setting. (1 count TS delay) Setting value 0: No delay
When OFT is turned to "L" before reaching a position of 1/4 track OFT
When OFT is turned to "L" after passing the position of 1/4 track OFT
1/4 track
TE Delay KICK Brake
TE Delay KICK Brake
SDD00026AEM
40
MN662785TBUC
(F)-5 Traverse drive constant in tracking brake (TVG) Data (D7 to D0)
D 3 D2 D 1 D 0
Table 7-1-4 (22) Function
Traverse drive constant TVG (1 to 15) Only in the tracking brake, traverse will be driven with the traverse error multiplied by the specified constant. Setting at reset 15
Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
1B F2
(F)-6 Traverse drive dead zone setting (DED0) Data (D7 to D0)
0 D6 D5 D4 D3 D2 D1 D0
Table 7-1-4 (23) Function Traverse drive dead zone setting (one side)
DED0 (0 to 127) Setting at reset 112
Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
1F F2
(F)-7
TE noise rejection width setting at track count (SETKC) Data (D7 to D0) Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
49 F2
Table 7-1-4 (24) Function
Setting at reset 3
0 D6 D5 D4 D3 D2 D1 D0
TE noise rejection width setting at track count
SETKC (0 to 127)
TE Ignored SETKC SETKC When the TE slope is inverted and reaches the level of the SETKC, it is regarded that the TE slope has actually changed.
SDD00026AEM
41
MN662785TBUC
(F)-8
KICK pulse width setting (KCCNT) Data (D7 to D0) Address (HEX) (A7 to A0)
4B
Table 7-1-4 (25) Command (HEX) (B7 to B0)
F2
Function
Inverted pulse width during servo pull-in operation in KICK operation. (Set value TS TS/2) s KICK pulse initial accelerating time (0 to 15) (Set value TS) s
Setting at reset 1
D7 D6 D5 D4
D3 D2 D1 D0
9
TS : 11.3 s
TE Inverted pulse width KICK (TRD) Brake
TE
KICK (TRD) Initial accelerating time
(F)-9
KICK pulse level setting (KICK) Data (D7 to D0) Address (HEX) (A7 to A0)
78
Table 7-1-4 (26) Command (HEX) (B7 to B0)
F2
Function
KICK pulse level setting KICK (0 to 127)
Setting at reset 22
0 D6 D5 D4 D3 D2 D1 D0
(F)-10
Traverse output gain setting (TRV) Data (D7 to D0) Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
79 F2
Table 7-1-4 (27) Function
Traverse output gain setting TRV (0 to 127) Setting at reset 65
0 D6 D5 D4 D3 D2 D1 D0
SDD00026AEM
42
MN662785TBUC
(F)-11
Traverse fine adjustment gain setting (TRVG0) Data (D7 to D0) Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
37 F2 Traverse gain TRVG0/16
Table 7-1-4 (28) Function
(0 to 127) Setting at reset 18
D7 D6 D5 D4 D3 D2 D1 D0
Set the above value after setting the TRV value.
(F)-12 Setting of automatic adjustment range The limits of adjustment values can be set arbitrarily in the range of 1/28 to 255/2 (or 48 dB to 42 dB). In order to ensure automatic gain convergence within a limited, narrow adjustment range to prevent excessive gain change, which had difficulty in convergence control, however, make sure that the maximum automatic adjustment range is 9 dB on the basis of the gain set value. Tracking gain Automatic adjustment range Data (D7 to D0)
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0
GLT3/GLT4 to GLT1/GLT2 Address Command (HEX) (HEX) (A7 to A0) (B7 to B0)
3D 3E F2
Table 7-1-4 (29) Function
Setting at reset
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0
3F 40
Tracking gain upper limit GLT1 (mantissa) (128 to 255) GLT2 (exponent) (0 to 7) Upper limit: GLT1/28-GLT2 Tracking gain lower limit GLT3 (mantissa) (128 to 255) GLT4 (exponent) (0 to 7) Lower limit: GLT3/28-GLT4
212 2
106 0
Focus gain Automatic adjustment range Data (D7 to D0)
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D3 D2 D1 D0
GLF3/GLF4 to GLF1/GLF2 Command Address (HEX) (HEX) (A7 to A0) (B7 to B0)
39 3A F2
Table 7-1-4 (30) Function
Setting at reset
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D 3 D2 D1 D0
3B 3C
Focus gain upper limit GLF1 (mantissa) (128 to 255) GLF2 (exponent) (0 to 7) Upper limit: GLF1/28-GLF2 Focus gain lower limit GLF3 (mantissa) (128 to 255) GLF4 (exponent) (0 to 7) Lower limit: GLF3/28-GLF4
143 4
144 1
SDD00026AEM
43
MN662785TBUC
(G) Access command setting Table 7-1-4 (31) Data (D15 to D0)
D15 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Kick-count setting (other than 0) F3
Command (HEX) (B7 to B0)
F1
Function
KICK-count setting/KICK operation start Inner track KICK operation Outer track KICK operation Track-count setting / Track counting start Inner track counting Outer track counting
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1
Track-count setting
Note) The track-count means the number of tracks until the brake operation start point is reached. TE sampling frequency in track counting is 176.4 kHz. Care must be taken so that the maximum TE frequency in track counting does not exceed one fourth of the sampling frequency.
SDD00026AEM
44
MN662785TBUC
(H) Spindle related settings (H)-1 Setting of spindle forced acceleration/deceleration (ECM) output level Data (D7 to D0) Address (HEX) Command (HEX) (A7 to A0) (B7 to B0)
2B F2
Table 7-1-4 (32) Function Setting at reset
127
D7 D6 D5 D4 D3 D2 D1 D0
ECM acceleration (ACC) level setting ECM (0 to 127)
* At the time of deceleration (BREAK), 2's complement of the above setting will be output. * If the ECM value is set to 127, 128 (ALLH or ALLL) will be output.
(H)-2
Setting of spindle shaft loss compensation value Data (D7 to D0) Address (HEX) Command (HEX) (A7 to A0) (B7 to B0)
2C F2
Table 7-1-4 (33) Function
Shaft loss compensation value setting SVOFS (-128 to 0)
Setting at reset
0
D7 D6 D5 D4 D3 D2 D1 D0
* The shaft loss compensation value will be enabled only when the spindle is in free running condition (STOP). No compensation will be enabled with this value set to 0.
(H)-3 Spindle fine adjustment gain setting (SPG0) Data (D7 to D0) Address (HEX) Command (HEX) (A7 to A0) (B7 to B0)
2F F2
Table 7-1-4 (34) Function
Spindle gain 0 to 127 SPG0 16
Setting at reset
22
D7 D6 D5 D4 D3 D2 D1 D0
Set the above value after setting the spindle gain with the 45h command.
SDD00026AEM
45
MN662785TBUC 7-1 (5) Data setting for signal processing section
(A) Audio control Table 7-1-5 (1) Data (D15 to D0) Command (HEX) (B7 to B0) 41 Symbol Function ( Setting at reset)
BIMAIN, Bilingual setting Normal stereo BISUB L-ch monaural R-ch monaural L- and R-ch reverse I NV Audio output polarity selection Normal Inverted Emphasis control (Note 1) De-emphasis connected directly Forced ON Forced OFF
MEMP
DEPSEL
Serial data output selection Before general attenuation and de-emphasis processing After general attenuation and de-emphasis processing Internal serial data muting SMUTE Disabled Enabled Note) Serial data input to the anti-shock memory controller will be muted. LRINV Selection of polarity of LRCK for DF input Normal L-ch H Inverted XBS XBS mode selection Disabled Enabled ASC mode selection Disabled Enabled LIVE mode selection Disabled Enabled
ASC
LI VE
AUDIO1, Serial data format selection AUDIO mode 1 AUDIO2 AUDIO mode 2 XMUTE Serial data output muting Disabled Enabled MMUTE Audio output muting Disabled Enabled
Note 1) Care must be taken during the anti-shock memory control operation since the control timing must be shifted based on the remaining memory though it is not needed during the normal operation.
SDD00026AEM
46
MN662785TBUC
(B) Digital audio interface control Table 7-1-5 (2) Data (D15 to D0) Command (HEX) (B7 to B0) 42 Symbol
UBITC
Function (
Setting at reset)
Bit U control LDON control (Inverted LDON) Output enabled Output fixed at high level Generation status bit setting 0 setting 1 setting
COPYI
TXVSEL Bit V control 1 High level while the signal is attenuated Signal attenuation ignored Note 1) Soft muting is included. Note 2) Both levels will be high with the gain set to dB. TMUTE Output data muting Disabled Enabled Note 1) Only audio data is fixed at 0. Note 2) The bit V level is high.
IPDISEN Bit V control 2 High level when the level of IPFLAG is high IPFLAG ignored TXDSEL Output speed selection Normal speed 2x speed Note 1) Available only if the anti-shock memory controller is turned off in 2x-speed playback mode. Note 2) Audio signal will be output at 2xspeed as well. VFREE Bit V control 3 The level will be high while the signal is attenuated (including the gain setting to dB) in DMUTE condition. Signal attenuation (including the gain setting to dB) with DMUTE condition ignored. Output control Enabled Fixed at low level Category code setting CD mode General mode Clock precision setting Standard mode Variable pitch mode High precision mode Not defined
XSEL
CATC
CFS1, CFS2
SDD00026AEM
47
MN662785TBUC
(C) Attenuation control
Table 7-1-5 (3)
Data (D15 to D0)
D7 D6 D5 D4 D3 D2 D1 D0
Command (HEX) (B7 to B0) 44
Symbol
Function (
Setting at reset)
MCNT(7:0) Attenuation level setting Note) The attenuation level is set to n/256. Initially set to 40 (HEX). A TT, MUTEM Normal (0 dB) Soft muting Digital attenuation Soft attenuation
(D) Spindle control 2 Data (D15 to D0) Command (HEX) (B7 to B0) 45 Symbol
FO1SEL, FO2SEL
Table 7-1-5 (4)
Function (
f0 frequency setting 24 Hz 6 Hz 12 Hz 3 Hz Loop gain setting 1 2 4 1/2
Setting at reset)
SG0, SG1
PCINV
PC output polarity selection Normal (ON at low level) Inverted
CLVSEL Selection of CLV mode transition condition (from rough to CLV) RESY: High level and rpm condition ( 4.6%) RESY: High level Note) Transition from CLV to rough mode is enabled under the condition of BSSEL failure. JFMODE Analog jitter-free mode Disabled Enabled ACCFIX Spindle fixed in a single direction (for acceleration only) Disabled Enabled Signal processing clock stop Disabled Enabled
KILL
CKSTOP Oscillation stop Disabled Enabled Note) The IC is reset and stops.
SDD00026AEM
48
MN662785TBUC
(E) PWM output control (Optical servo system)
Table 7-1-5 (5)
Data (D15 to D0)
Command (HEX) (B7 to B0) 46
Symbol
FBAL1E, FBAL2E
Function (
Setting at reset)
FBAL charge pump current source control Stop 1 1/2 3/2 TBAL charge pump current source control Stop 1 1/2 3/2
TBAL1E, TBAL2E
MCFSEL Noise filter for microcomputer interface Enabled Disabled
SDD00026AEM
49
MN662785TBUC
(F) Playback speed control
Table 7-1-5 (6)
Data (D15 to D0)
Command (HEX) Symbol (B7 to B0) 49
DSEL
Function (
Setting at reset)
2x-speed playback selection Normal speed 2x speed 4x-speed playback selection Normal speed 4x speed (Note 4)
QSEL
OVERDRV Overdrive mode (Note 4) Disabled Enabled Note 1) Constantly 1.5x speed based on the speed set with DSEL and QSEL. Note 2) Available in jitter-free mode only. SVPC(2:0) Spindle speed change rate setting 1 15/16 14/16 13/16 12/16 11/16 10/16 9/16 Note 3) Available in jitter-free mode only. VCOE VCO control for jitter-free OFF Oscillation ON Charge pump current source stop (for jitter-free) Disabled Enabled
CPOFF
Note 4) If the anti-shock memory controller is turned on, maximum 2.25x-speed playback in decompression mode and maximum 3x-speed playback in compression mode are guaranteed with the jitter-free function turned on.
(G) DO control
Table 7-1-5 (7)
Data (D15 to D0)
Command (HEX) (B7 to B0) 4A
Symbol
DSLDO
Function (
DSL's DO processing Enabled Disabled
Setting at reset)
CLVDO
Spindle's DO processing Enabled Disabled PLL's DO processing Enabled Disabled DO with faults processing Enabled Disabled
PLLDO
W GEN
SDD00026AEM
50
MN662785TBUC
(H) PLL control
Table 7-1-5 (8)
Data (D15 to D0)
Command (HEX) (B7 to B0) 4B
Symbol
PLLG1, PLLG2
Function (
Setting at reset)
PLLF current setting x1 (Conventional setting) x5/4 x1/2 x3/4 VCO frequency selection x1/2 x1 IREF current shut off Normal Shut off PLLF current shut off by tracking failure Disabled Enabled Frequency pull-in method selection 2T detection 5T detection
PCKG
IROFF
PLHLD
DET5T
D9 D8 D7 D6
FL02,FL04, Pull-in time setting with 2T or 5T detected FL08,FL16 Calculation formula 9 32 nD8 6 D7 nD6 (pck) Note) Initially set to 32 pck FH32 Pull-in time setting with 12T detected 64 pck 32 pck Forced double current setting for phase PLLG comparison Disabled Enabled PLLG3, PLLG4 Frequency comparison current rate selection x1 x5/4 x1/2 x3/4
SDD00026AEM
51
MN662785TBUC
(I) I/O control 1
Table 7-1-5 (9)
Data (D15 to D0)
Command (HEX) (B7 to B0) 4C
Symbol
TX T2
Function (
Setting at reset)
CD-TEXT data output pin selection (SUBC, SBCK, NCLDCK) (TXTD, TXTCLK, DQSY) Serial output pin selection (SUBC, SBCK, NCLDCK) (SRDATA, LRCK, BCLK)
SROUT2
EXT12SEL EXT1 and EXT2 output pins selection (EXT1, EXT2) (VDET, EFM) PCKOUT EXT1 output pin selection 2 V D ET PCK Note) Enabled only when the level of EXT12SEL is high.
(J) DSL unbalance compensation control
Table 7-1-5 (10)
Data (D15 to D0)
Command (HEX) (B7 to B0) 4D
Symbol
DSLBSEL
Function (
Setting at reset)
EFM or SRF selection EFM SRF Charge pump current source control Shut off x1 x 1/2 x 3/2 Compensation value counter operation control Previous value kept on hold Compensation value taken in
DSLB1E, DSLB2E
DSLBEN
SDD00026AEM
52
MN662785TBUC
(K) I/O control 2
Table 7-1-5 (11)
Data (D15 to D0)
Command (HEX) (B7 to B0) 4E
Symbol
IOSTOP
Function (
Setting at reset)
Output pin fixed at low level Disabled Enabled Note 1) Enabled pins: SRDATA, LRCK, BCLK, IPFLAG, SUBC, NCLDCK Note 2) Serial input mode is activated if IOSTOP is disabled. EXT0,EXT1,EXT2 RDATA,LRCK,BCLK
MCMSEL SMCK frequency selection 8.4672 MHz 4.2336 MHz DF input selection DFSEL Input bypassing the anti-shock memory controller Input from the anti-shock memory controller Off-track noise filter OFTSEL Disabled Enabled EXT0SEL EXT0 pin selection Normal Serial monitor (for evaluation) DRF pin control Disabled Enabled RSEL selection Bright levelAFLow Bright level High BLKCK and SUBQ pins selection (BLKCK, SUBQ) (ZBLKCK, SUBQ) (DQSY, TXTD) Note) ZBLKCK:Interpolation BLKCK, TXTD:CD-TEXT data Serial output mode selection Normal Serial output mode Note) DMUTE,SUBQ,SQCK RDATA,LRCK,BCLK IPFLAG pin selection Normal CLVS FLAG pin selection Normal Serial monitor (for evaluation) FLAG0 output fixed Disabled Enabled Note) FLAG0 is always output from FLAG pin.
DSLDR
RSEL
MCOM4E BLKCKSEL
MPEGIF
IPSEL
FLAGSEL
FLAGFIX
SDD00026AEM
53
MN662785TBUC
(L) STAT pin control
Table 7-1-5 (12)
Data (D15 to D0)
Command (HEX) (B7 to B0)
70 71 72 73 74 76 77 79 7A 7B 75
Symbol
Function (
Setting at reset)
XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X
XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X XXX X
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
D2D1
STAT pin output selection : CRC : RESY : CLVS : NTTSTOP : SQOK : BSSEL : FCLV : SUBQ (SQCK sync) / TXTDAT : SUBQ (MCLK sync) / TXTDAT : ZDET (Zero data detection) STAT pin output setting STAT pin output 0. FLAG6 0. SENSE 0. NFLOCK 0. NTLOCK STAT pin output mode selection by MCLK (excluding the setting of SENSE(01)) 1. FLAG6 2. SENSE 3. NFLOCK 4. NTLOCK 5. SQOK 6. CRC 7. CLVS 8. NTTSTOP Clearing FLAG6 output from STAT pin Disabled Enabled (Reset of FLAG6) Disc rotation speed data output from STAT pin (8-bit data)
XXX X XXX X XXX X XXX X
XXX X XXX X XXX X XXX X
XXXX XXXX XXXX XXXX
X0 0 X X0 1 X X1 0 X X1 1 X
D0
XXX X XXX X XXXX XXX0 XXX X XXX X XXXX XXX1
XXX X XXX X XXXX XXXX
7E
D2D1D0 0 1 1 1 0 1 0 1
MDATA
MCLK MLD
STAT output
0
1
2
3
4
5
6
7
8
Timing chart of STAT pin output mode selection by MCLK
SDD00026AEM
54
MN662785TBUC
7-1 (6) Data setting for anti-shock memory controller
[1] Data write (A) Memory system command Table 7-1-6 (1) Data (D7 to D0) Command (HEX) (B7 to B0) 80 Symbol
MSON
Function (
Setting at reset)
Memory system stop Memory system run Q-data disabled Q-data enabled Comparison connection aborted Direct connection 2-pair comparison connection 3-pair comparison connection Normal operation Read address reset Decoding aborted Decoding executed Normal operation Write address reset Encoding aborted Encoding executed
WAQV
MSDCN
MSRACL
MSRDEN
MSWACL
MSWREN
(B) Expansion I/O port (I/O setting) Table 7-1-6 (2) Data (D7 to D0) Command (HEX) (B7 to B0) 81 Symbol
EXT0ST
Function (
Setting at reset)
Input Output Input Output Input Output
Expansion I/O Port EXT0 I/O setting
EXT1ST
Expansion I/O Port EXT1 I/O setting
EXT2ST
Expansion I/O Port EXT2 I/O setting
SDD00026AEM
55
MN662785TBUC
(C) Expansion I/O port (Output data setting) Table 7-1-6 (3) Data (D7 to D0) Command (HEX) (B7 to B0) 82 Symbol
EXT0WT
Function (
Setting at reset)
L output H output L output H output L output H output
Expansion I/O port EXT0 output setting
EXT1WT
Expansion I/O port EXT1 output setting
EXT2WT
Expansion I/O port EXT2 output setting
(D) Option setting Table 7-1-6 (4) Data (D7 to D0) Command (HEX) (B7 to B0) 85 Symbol
CMOD
Function (
Decompression mode 4-bit compression mode
Setting at reset)
16M DRAM not used 16M DRAM used (NCAS1 used as A10) RSEL1 One DRAM used Two DRAMs used (NCAS of unused RAM is fixed at high level) 1M DRAM used 4M DRAM used No window discrimination Window discrimination 98 Window discrimination 98 Window discrimination 98
RSEL0
86
WSEL
4 CLDCK window 8 CLDCK window 28 CLDCK window
C2SEL
Interpolated comparison Comparison without interpolation 16-bit comparison Upper 12-bit comparison Parameter reset at start of encoding during direct connection No Yes
CMPSEL
Note) The D4 bit of the 86h command is by default set to 0. Set this bit to 1 while the memory system is running, otherwise playback data will involve noise.
SDD00026AEM
56
MN662785TBUC
(E) Q code input for optical digital output signal (TX) MDATA MCLK MLD If the anti-shock memory controller is turned on, Q code data can be set for user data on the optical digital output signal. Table 7-1-6 (5) Command (HEX) (B7 to B0) 87 Data Q0 to Q79 (80 bits) Symbol
MCQ Q0 Q1 Q2 Q77 Q78 Q79
Function
Q code input for TX
Internal block sync signal CLDCK
16 clocks 16 clocks a b A 16 clocks c
Input timing Output timing
The Q code that is input into a-zone is output as bit U data during period A.
Details of bit U (Q channel) --
0 0 Q0 Sub code Sync word
Q1
- -Input data
Q79 Q80 Q81
- --
Q95
CRC data (16 bits)
0 0 Sub code Sync word
- --
CRC data is generated from the arithmetic operation of input data and added. Note1) The internal block sync signal is a synchronized with a subcode sync word. Data input BLKCK Output data
A A B C C a b c
If no Q code is input, the previous value will be kept on hold and bit U will be output. At that time, CRC data is added with disabling data. Note2) Interruption is not allowed while the Q code is input, otherwise the wrong bit U will be output. The Q code cannot be input into a single block more than once, otherwise the wrong bit U will be output.
SDD00026AEM
57
MN662785TBUC
[2] Data read
MDATA
Read command
MLD
MCLK
STAT pin
Indefinite
S0
S1
S2
S3
S4
S5
S6
S7
Min. 25 s Figure 7-1-6 Timing chart for reading data
(A) Status command Table 7-1-6 (6) Command (HEX) (B7 to B0) 90 Output bit S0 Symbol
FLAG6
Function
L: FLAG6I input normal H: FLAG6I input abnormal L: Normal H: Write overflow L: Normal H: During comparison connection L: Normal H: No enabled data L: Normal H: Write overflow
S1
MSOVF
S4
DCOMP
91
S0 S1
MSEMP
OVFL
SDD00026AEM
58
MN662785TBUC
(B) Remaining enabled data Table 7-1-6 (7) Command (HEX) (B7 to B0) 92 Output bit
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 H: 8M bits H: 4M bits H: 2M bits H: 1M bits H: 512K bits H: 256K bits H: 128K bits H: 64K bits H: 32K bits H: 16K bits H: 8K bits H: 4K bits H: 2K bits H: 1K bits H: 512 bits H: 256 bits
Function
(C) Expansion I/O port Table 7-1-6 (8) Command (HEX) (B7 to B0) 93 Output bit
S5
Symbol
EXT2RD
Function
Expansion I/O port EXT2 input data
S6
EXT1RD
Expansion I/O port EXT1 input data
S7
EXT0RD
Expansion I/O port EXT0 input data
SDD00026AEM
59
MN662785TBUC
7-1 (7) Automatic adjustment
Following is a list of automatic adjustment. Table 7-1-7 Command (HEX) (B7 to B0) Offset AOC1 (Note) F9 Description Averages and corrects the focus error values and tracking error values as offset when the laser is turned on or off. Inputs the disturbance into the focus servo loop, and makes corrections so that the envelope ripple for the 3T component of the RF signal in the positive and negative parts of the FE signal should be balanced. The output pin for corrections is FBAL. The average tracking error value without the tracking servo is used as a balancing value to make corrections. The output pin for corrections is TBAL. Traverse Time required operation 50 ms FWD/REV to enabled 140 ms
Fo balance ABC1
F7
Within 0.5 s
STOP
Tr balance ABC2
FB
Within 1s
STOP
Fo rough gain AGC1 Tr rough gain AGC2 Fo fine gain FAGC Tr fine gain TAGC
FC
FWD/REV Set Focus search is performed at approx. 5.4 Hz or between enabled 1.3 Hz, and the disturbance input amount for the fine AGC is determined using focus error S-curve 190 ms and p-p value. The gain will be unchanged. 780 ms The p-p value of the tracking error without the tracking servo determines the disturbance input amount for the fine AGC. The gain will be unchanged. Inputs the disturbance into the focus servo loop, and adjusts the gain crossover to the frequency set by the microcomputer command. Set between 135 ms and 350 ms Within 0.5 s STOP
FD
FE
STOP
FF
Inputs the disturbance into the tracking servo loop, and adjusts the gain crossover to the frequency set by the microcomputer command.
Within 0.5 s
STOP
Note) Do not use FAh, a conventional AOC2 command.
SDD00026AEM
60
MN662785TBUC
7-2 Input timing 7-2 (1) Subcode interface
A. SUBQ data read Subcode data can be read at the timing shown in the figure below.
BLKCK
NCLDCK 80 clocks SQCK
SUBQ
CRC
Q1 Q2 Q3 Q4
Q79 Q80
CRC
STAT (=CRC) SQOK
H: CRC=OK
L: CRC=NG
8.7 ms
Figure 7-2-1 BLKCK, NCLDCK, SQCK, SUBQ, and CRC timing chart
SDD00026AEM
61
MN662785TBUC
B. Subcode data read By inputting a clock from SBCK pin, subcode data, P to W, can be read from SUBC pin. The timing is shown in the figure below. Since subcode data varies every falling edge of NCLDCK, input 8 clocks of SBCK every falling edge of NCLDCK, and switch the content of SUBC output to P to W. Then SUBC output which varies in synchronization with the falling edge of SBCK is received at the timing of the rising edge of SBCK. All subcode data can be read by repeating the operation above for each NCLDCK. By inputting SBCK, the content of FLAG output will vary. So measuring the error rate while reading subcode is not possible. Take it into consideration when designing the system.
Typ. 136 s BLKCK NCLDCK
Typ. 1.6 s
SBCK
SUBC
S0
S1
P1 to W1 P2 to W2 P3 to W3 P4 to W4 P5 to W5 P6 to W6 P7 to W7
NCLDCK
SBCK
SUBC
P
Q
R
S
T
U
V
W
: Refer to the values specified in the PRODUCT STANDARDS.
Figure 7-2-2 NCLDCK, SUBC, and SBCK timing chart
SDD00026AEM
62
MN662785TBUC
7-2 (2) Serial data output
A. Serial data output mode 1 By executing the following command, the BCLK signal, LRCK signal, and SRDATA signal will be output from pins 65, 66, and 67 respectively. Table 7-3-1 Data (D15 to D0) Command (HEX) (B7 to B0) 4E Note) X can be any value. B. Serial data output mode 2 By executing the following command, the SRDATA signal, LRCK signal, and BCLK signal will be output from pins 73, 74, and 75 respectively. Table 7-3-2 (1) Command Symbol (HEX) Data (D15 to D0) (B7 to B0) 4C Note) X can be any value. Table 7-3-2 (2) Data (D15 to D0) Command (HEX) (B7 to B0) 4E Note) X can be any value. C. Serial data output selection The following command determines whether serial data in serial data output mode 1 or serial data output mode 2 is output with or without attenuation and de-emphasis. Table 7-3-3 Data (D15 to D0) Command (HEX) Symbol (B7 to B0) 41
DSPSEL SROUT2
Symbol
MPEGIF, IOSTOP
Symbol
IOSTOP
Function With no attenuation or de-emphasis With attenuation and de-emphasis
Note) X can be any value.
SDD00026AEM
63
MN662785TBUC
D. Serial data output timing The following timing chart shows the output timing of serial data. Serial data output mode 1 and 2 are the same in the output timing of serial data.
Invalid Invalid Invalid
SR D A T A
15
1413121110 9 8 7 6 5 4 3 2 1 0
15
1413121110 9 8 7 6 5 4 3 2 1 0
15
LRCK
BCLK
L- c h
R-ch
L-ch
7-2 (3) Serial data input
When the IC is in serial data output mode 1 or 2, the SRDATA signal, LRCK signal, and BCLK signal will be input into pins 57, 58, and 59 respectively so that IOSTOP bit will be set to 0. Therefore, handle pins 57, 58, and 59 as input pins in serial data output mode 1 or 2. The input timing of serial data is the same as the output timing of serial data.
SDD00026AEM
64
MN662785TBUC
PRODUCT STANDARDS
A. ABSOLUTE MAXIMUM RATINGS Parameter A1 A2 A3 A4 A5 A6 Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Symbol DVDD1,2 AVDD1,2 VI VO PD Topr Tstg Rating 0.3 to 4.6 0.3 0.3 0.3 0.3 Unit V V V mW 85 125 C Ta 25C Note DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V DVSS1,2=0 V AVSS1,2=0 V
DVSS1,2 0.3 to DVDD1,2 AVSS1,2 0.3 to AVDD1,2 DVSS1,2 0.3 to DVDD1,2 AVSS1,2 0.3 to AVDD1,2 570 40 to 55 to
Note 1) The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. Note 2) Each of DVSS1, DVSS2, AVSS1, and AVSS2 pins should be directly connected to the ground and used at the same voltage. Note 3) Each of DVDD1, DVDD2, AVDD1, and AVDD2 pins should be directly connected to the specified power supply and used at the same voltage. Note 4) DVDD1, DVDD2, AVDD1, and AVDD2 should be powered up at the same time. Note 5) The operation of the audio D/A converter is not guaranteed for operations in 2x-speed playback modes (i.e., when anti-shock memory controller is not operating). Note 6) Connect a bypass capacitor (0.1 F or more) between DVDD1 and DVSS1 pins, between DVDD2 and DVSS2 pins, between AVDD1 and AVSS1 pins, and between AVDD2 and AVSS2 pins.
SDD00026AEM
65
MN662785TBUC
B. OPERATING CONDITIONS
Ta
40C to
85C
DVSS1,2 0 V AVSS1,2 0 V Limits Conditions Min Typ
3.3 3.3 3.3
Parameter B1 B2 B3 B4
Digital system supply voltage Audio system supply voltage Analog system supply voltage D-RAM interface voltage
Symbol
DVDD1,2 AVDD1 AVDD2 DVDD3V (Note 7) (Note 7)
Unit Max
3.6 3.6 3.6 3.6 V V V V 3.0 3.0 3.0 VDD1,2
Note 7)
It is recommended to basically use AVDD1 and AVDD2 at the same voltage as DVDD.
Self-excited Oscillation B5 B6 B7
Crystal frequency External capacitance 1 External capacitance 2
(Note 8)
fxtal C1 C2 With no external resistor R
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C
33.8688 10 10 MHz pF pF
Note 8) Oscillator Circuit C2 X2 MN662785TBUC X1 C1 Xtal
SDD00026AEM
66
MN662785TBUC
C. ELECTRICAL CHARACTERISTICS (1) DC Characteristics
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Unit Min Typ
23
Parameter
Symbol
Conditions Max
46
C1 C2 C3 C4
Supply current Total power consumption Supply current Total power consumption
IDD
PT
Anti-shock memory controller is not operating. No external load (in normal-speed playback mode) Ta 25C
mA
76
152
mW
IDD
24
Anti-shock memory controller is not operating. No external load (in 2x-speed playback mode) Ta 25C
48
mA
PT
80
160
mW
SDD00026AEM
67
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Input Pins (1) Input voltage high level Input voltage C6 low level Input leakage C7 current C5 1 1 VIH1 VIL1 I LK1 VIN 0 V to 3.3 V 2.64
DVSS1,2
DVDD1,2
Unit Typ Max
V V A
0.66 1
FSEL, CSEL TMOD1, TMOD2 EXT0/ISRDATA/SRMON2, EXT1/ILRCK/VDET/PCK, EXT2/IBCLK/EFM D0, D1, D2, D3, OFT, NRFDET, BDO, NTEST, MCLK, MDATA, MLD, SQCK/BCLK1/TXTCLK1, DMUTE/SRDATA1, NRST, SBCK/TXTCLK2/LRCK2
SDD00026AEM
68
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Output Pins (1) C8 C9 Output voltage high level Output voltage low level Output Pins (2) C10 Output voltage high level C11 Output voltage low level Output leakage C12 current 2 VOH1 VOL1 3 VOH2 VOL2 ILK2 I O H2 1 mA
DVDD1,2
Unit Typ Max
IOH1
1 mA
DVDD1,2
0.6
V 0.4 V
IOL1 1 mA
0.6
V 0.4 1 V A
IOL2 1 mA Hi-Z VO 0 V to 3.3 V
2 LDON, FLAG/SRMON1, CLVS/IPFLAG, EXT0/ISRDATA/SRMON2, EXT1/ILRCK/VDET/PCK, EXT2/IBCLK/EFM, TX, BLKCK/DQSY1, SQCK/BCLK1/TXTCLK1, SUBQ/LRCK1/TXTDAT1, DMUTE/SRDATA1, STAT, SPPOL, PMCK, SMCK, SUBC/TXTDAT2/SRDATA2, SBCK/TXTCLK2/LRCK2, NCLDCK/DQSY2/BCLK2, D0, D1, NWE, NRAS, D2, D3, NCAS0, NCAS1, A8, A7, A6, A5, A4, A9, A0, A1, A2, A3 2 SPOUT, TRVP, TRVM, TRP, TRM, FOP, FOM,
SDD00026AEM
69
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol IREF
When pulled up by a 47-k resistor 25 47 80 A
Conditions Min Typ Max
Unit
Analog System Input Pin (1) C13 Input current
IREF
Analog System Input Pin (2) C14 Input signal amplitude C15 Input leakage current
VARF ILKA
ARF
Input level of the EFM signal in the application circuit of the DSL circuit block 0.5 1.0 1.0 V[p-p] A
Analog System Input Pin (3) C16 Input leakage current C17 between ARF and DRF
Internal resistance ILKD RDRF
DRF
1.0 ARF 1.65 V 10 A k
SDD00026AEM
70
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Typ Max Unit
Analog System Output Pin (1) DSLF (IREF pin is pulled up to AVDD2 by a 47-k resistor.) C18 Output current (N) C19 Output current (P)
IDSH BDO L, Tracking ON-state DSLF 1.65 V, ARF 3.3 V BDO L, Tracking ON-state DSLF 1.65 V, ARF 0 V BDO L, Tracking ON-state Normal current mode 98 130 169 A A A
IDSL
169 8.0
130 2.0
98 4.0
Output current balance C20 in normal current mode IDSBL
Analog System Output Pin (2) PLLF (IREF pin is pulled up to AVDD2 by a 47-k resistor.) C21 output current (N) C22 output current (P)
Phase comparison Phase comparison IPFH IPFL ILKP IPLBL BDO BDO Hi-Z BDO L, Tracking ON-state Normal current mode Normal- to 2x-speed jitter-free mode VCO frequency (for PCK) switching 0.5 L, Tracking OFF-state L, Tracking OFF-state 105 182 140 140 182 105 1 A A A A
C23 Input leakage current C24 in normal current mode C25 frequency
PCK oscillator Output current balance
15.0
6.0
3.0
fVCO1
4.32
8.65
MHz
Analog System Output Pin (3) VCOF (IREF pin is pulled up to AVDD2 by a 47-k resistor.) C26 output current (N) Phase comparison C27 output current (P) C28 Input leakage current C29 frequency
VCO oscillator Phase comparison IVFH IVFL ILKV fVCO4 Hi-Z Variable pitch jitter-free mode VCO frequency (for variable pitch jitter-free) switching 0.5 8.46 98 169 130 130 169 98 1 16.94 A A A MHz
Analog System Output Pins (4) TBAL, FBAL (IREF pin is pulled up to AVDD2 by a 47-k resistor.) C30 Output current (N) C31 Output current (P)
IBAH IBAL At default setting ( At default setting ( 1) 1) 23 41 32 32 41 23 A A
SDD00026AEM
71
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz
3.3 V
47 k 0.022 F 0.001 F ARF 100 k 100 k DRF AVDD2 DSLF AVSS2 0.022 F DVDD2 DVSS2 PLLF 390 0.22 F 0.1 F 220 F IREF AVDD1 220 F VARF 1.0 V[p-p] (Typ.) AVSS1
3.3 V
3.3 V
3.3 V
3.3 V
DVDD1 3.3 V DVDD3V VCOF DVSS1 0.1 F 0.1 F
0.01 F
2.2 k
0.47 F
DSL
PLL Block Recommended Circuit Diagram
SDD00026AEM
72
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Analog System Input Pins (4) C32 C33 Input voltage high level Input voltage low level V I H4 V I L4
0.1AVDD2
Unit T yp Max
TE, FE, RFENV
0.9AVDD2
V V
SDD00026AEM
73
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min A/D Converter (for Servo) C34 Resolution Integral C35 nonlinearity Differential C36 nonlinearity RES INL DNL A/D output=99 to 66 (2's complement ) 8 2 3 bit LSB LSB Typ Max Unit
SDD00026AEM
74
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min D/A Converter Analog Characteristics C37 Signal-to-noise ratio C38 Dynamic range C39 Total harmonic distortion C40 Crosstalk C41 Output level 1 Output level difference S/N D.R.
THD+N
Unit T yp Max
(Note 9), (Note 12) 90 86 97 94 0.005 0.009 80 1.04 89 1.33 1.62 dB dB % dB Vrms
EIAJ EIAJ EIAJ EIAJ Reference input signal of 1 kHz Full scale (Note 10) Difference of OUTL and OUTR pins at output level 1. 20 log (VR/VL) Reference input signal of 1 kHz Full scale (Note 11)
C42
0.99
0.99
dB
C43
Output level 2
0.69
0.88
1.07
Vrms
Note 9)
The analog characteristics indicate the values measured by inserting a 15- resistor between the AVDD1 pin and power supply. The typical values are only reference values. They are not guaranteed. The output level 1 shows the measured value at the output pins of the application circuit. Output level 2 is calculated by taking the measured value of output level 1, dividing it by the external circuit gain of the application circuit, and converting the result to the value at the output pin of this IC. The D/A converter always operates in the normal-speed playback mode.
Note 10)
Note 11)
Note 12)
SDD00026AEM
75
MN662785TBUC
DVSS
15 1 k 47 k 47 k 1.5 k 2.2 k 0.001 F 22 F 100 pF 22 F
DVDD
AVSS2
AVDD2
AVDD1
0.1 F
0.1 F
[D/A Converter Application Circuit]
560
DVSS2 AVDD1 OUTL AVSS1
100 F 0.1 F
DVDD2
AVSS2
AVDD2
0.0018 F 47 k 100 pF
47 k
SDD00026AEM
MN662785TBUC
OUTR
1 k 22 F 47 k 47 k 100 pF 22 F 47 k 1.5 k 100 pF 2.2 k 560
DVSS1
DVDD1
0.1 F 0.0018 F
0.001 F
47 k
DVSS
DVDD
AVSS1
76
MN662785TBUC
(2) AC characteristics
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits
Parameter
Symbol
Conditions Min Typ Max
Unit
Reset Timing (Note 13) C44 NRST pulse width tNRSTL 200 ms
Power Supply Ripple Noise (Note 14) C45 Ripple amplitude Ripple noise C46 amplitude Note 13) VRIP V NZ 15 50
mV[p-p] mV[p-p]
When the power is turned on, reset with the NRST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within 10% of error of the specified oscillator frequency. When designing, be careful to eliminate noise from the reset line as much as possible.
tNRSTL
NRST
0.2VDD
0.2VDD
Note 14)
The permissible ripple and noise of power supply to this IC are guaranteed on condition that the ripple frequency range is between 50 Hz and 100 Hz, the noise frequency is at 500 kHz, and that both ripple and noise are sine wave signals as shown below. Pay utmost attention to these ripple signal and noise signal because they may exceed the permissible values under the influence of the location of peripheral parts.
Noise frequency: 500 kHz
VRIP
VNZ
Ripple frequency: 50 Hz to 100 Hz
SDD00026AEM
77
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter C47 Rise time C48 Fall time C49 Rise time C50 Fall time Symbol tRA tFA tRB tFB Conditions Min T yp Max 100 100 50 50 ns ns ns ns Unit
MCLK MLD
0.8VDD 0.2VDD tRA tFA
0.8VDD 0.2VDD
SBCK
0.8VDD 0.2VDD tRB tFB
0.8VDD 0.2VDD
SDD00026AEM
78
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Microcomputer Instruction Input Timing C51 Clock frequency C52 Clock pulse width C53 Data setup time C54 Data hold time C55 Delay time C56 Latch pulse width fMCLK tCH,CL tDSU tDH t LD D tLDW 300 300 300 300 0.5 5 1.1 MHz ns ns ns ns s T yp Max Unit
1/f MCLK
MCLK
tCH tCL
MDATA
tDSU tDH
MLD
tLDD tLDW
SDD00026AEM
79
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 AVDD1,2 3.3 V, AVSS1,2 Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Subcode Interface (1) C57 Clock width High-level C58 pulse width Low-level C59 pulse width C60 Delay time C61 Setup delay time Subcode Interface (2) C62 Clock width High-level C63 pulse width Low-level C64 pulse width C65 Delay time C66 Setup delay time Symbol (FSEL tCK, tSQ tCKH, tSQH tCKL, tSQL tSBD, tSQD tSD (FSEL tCK, tSQ tCKH, tSQH tCKL, tSQL tSBD, tSQD tSD H) 500 200 200 150 150 L) 700 300 300 250 150 Conditions Min Typ Max
0V 0V
Unit
ns ns ns ns ns
ns ns ns ns ns
SDD00026AEM
80
MN662785TBUC
tCK tCKL SBCK
tCKH
SUBC tSD NCLDCK tSBD
tSQ tSQL SQCK tSQH
SUBQ
tSQD
SDD00026AEM
81
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Typ Max Unit
STAT output Interface (1) C67 C68 C69 C70
Clock width High-level pulse width Low-level pulse width Delay time tMT tMTH tMTL tMTD
(FSEL
L)
909 300 300 250 ns ns ns ns
STAT output Interface (2) C71 C72 C73 C74
Clock width High-level pulse width Low-level pulse width Delay time tMT tMTH tMTL tMTD
(FSEL
H)
909 300 300 150 ns ns ns ns
tMT tMTL MCLK tMTH
STAT
tMTD
SDD00026AEM
82
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Typ Max Unit
STAT output Interface (3) C75 C76 C77 C78
Clock width High-level pulse width Low-level pulse width Delay time tMT tMTH tMTL tMTD
(FSEL
L)
(Note 15)
909 300 300 250 ns ns ns ns
STAT output Interface (4) C79 C80 C81 C82
Clock width High-level pulse width Low-level pulse width Delay time tMT tMTH tMTL tMTD
(FSEL
H)
(Note 15)
909 300 300 150 ns ns ns ns
Note 15) STAT output data switching with MCLK when using 75h command
tMT tMTH MCLK tMTL
STAT
tMTD
SDD00026AEM
83
MN662785TBUC
VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Typ Max Unit
D/A output Interface (1) C83 C84 C85 C86 C87
Clock width High-level pulse width Low-level pulse width Setup time Hold time tBCLK tBCLKH tBCLKL tST tHD Normal-speed playback mode 70 70 354 177 177 ns ns ns ns ns
D/A output Interface (2) C88 C89 C90 C91 C92
Clock width High-level pulse width Low-level pulse width Setup time Hold time tBCLK tBCLKH tBCLKL tST tHD 2x-speed playback mode 50 50 177 88.5 88.5 ns ns ns ns ns
tBCLK tBCLKL tBCLKH BCLK1/BCLK2
SRDATA1/SRDATA2 LRCK1/LRCK2 tST tHD
SDD00026AEM
84
MN662785TBUC
VDD 3.3 V, VSS 0 V AVDD 3.3 V, AVSS 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter Symbol Conditions Min Typ Max Unit
D/A converter input timing C93 C94 C95 C96 C97 C98
BCLK frequency BCLK pulse width Data setup time Data hold time LRCK frequency BCLK-LRCK timing fBCLK tCH, tCL tDSU tDH fLRCK tBL, tLB 65 100 65 65 44.1 4 MHz ns ns ns kHz ns
1/fBCLK
IBCLK tCH ISRDATA tDSU ILRCK tBL tLB tBL tLB tDH tCL
1/fLRCK
SDD00026AEM
85
MN662785TBUC
DVDD1,2 3.3 V, DVSS1,2 0 V AVDD1,2 3.3 V, AVSS1,2 0 V Ta 40C to 85C fX1 33.8688 MHz Limits Parameter DRAM Interface C99 NRAS low-level pulse width C100 NRAS high-level pulse width C101 NCAS0 / NCAS1 low-level pulse C102
width NCAS0 / NCAS1 high-level pulse width trasl trash tcasl tcash trads tradh tcads tcadhw tcwds tcadv tradv tcadhr twcd twel tref (Playback fs 44.1 kHz) tref tref tref tref tref 16 Mbits, full bits 16 Mbits, 4-bit compression 4 Mbits, full bits 4 Mbits, 4-bit compression 1 Mbit, full bits 1 Mbit, 4-bit compression 4 1 1 2 3 3 120 300 0 3 5 5.9 23.3 3.0 11.7 1.5 5.9 2 4 6 tcy tcy tcy tcy tcy tcy tcy tcy tcy ns ns ns tcy tcy ms ms ms ms ms ms
Symbol
Conditions Min Typ Max
Unit
C103 NRAS address setup time C104 NCAS0 / NCAS1 address hold time C105 NCAS0 / NCAS1 address setup time C106 NCAS0 / NCAS1 address hold time C107 NCAS0 / NCAS1 data setup time C108 NCAS0 / NCAS1 data valid time C109 NRAS data valid time C110 Data hold time C111 NWE delay time C112 NWE pulse width C113 C114 Refresh period C115 C116 C117 C118
Memory system ON with decode sequence executed.
tcy: One system clock cycle which is indicated as 1/(16.9344 MHz) seconds.
SDD00026AEM
86
MN662785TBUC
DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A9, D0 to D3)
Write Timing
trasl trash
NRAS
trcd tcash tcasl trads tradh tcads
NCAS0 (NCAS1)
A0 to A9
tcwds tcadhw
D0 to D3 (WRITE)
twcd tcwdh
NWE (WRITE)
twel
Read Timing
trasl trash
NRAS
trcd tcash tcasl trads tradh tcads
NCAS0 (NCAS1)
A0 to A9
tcadv tradv tcadhr
D0 to D3 (READ)
NWE (READ)
"H"
SDD00026AEM
87
MN662785TBUC
Package Dimensions (Unit: mm)
* LQFP080-P-1414A (lead-free package)
16.000.20 14.000.20 60 61 41 40 (0.825) 14.000.20 80 1 (0.825) 0.65 0.300.05 20 0.13 M 21 1.70 max. 1.400.10 (1.00)
0.150.05
0.100.10
16.000.20
0 to 10 0.500.20
0.10
Seating plane
SDD00026AEM
88
Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book. (4) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 MAY

▲Up To Search▲

Price & Availability of MN662785TBUC

	To Download MN662785TBUC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .