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NT3883
Dot Matrix LCD 80-Channel Driver
Features
T T T
Provides 80-channel LCD driver Internal serial to parallel conversion circuits: 40-bit bi-direction shift register 2 80-bit latch 1 80-bit 4-level driver 1 Logic circuit supply voltage range: 4.5V - 5.5V
T T T T T
LCD driving voltage range (VDD - VEE): 3.5V to 11V Applicable LCD duty cycle: 1/2 to 1/16 Interfaces with a NT3881B/C/D LCD controller LCD bias voltage can be supplied externally Available in 100-pin QFP and in CHIP FORM
General Description
The NT3883 is a dot matrix LCD 80-channel driver fabricated by low power CMOS technology. This IC consists of two 40-bit bi-directional shift registers, 80-bit latch and 80-bit 4-level LCD driver. The NT3883 converts serial data that are received from the LCD controller, such as NT3881B/C/D, to parallel data and outputs LCD driving waveforms to drive LCD. Expansion of character-type liquid crystal display can be easily obtained according to the number and structure of characters.
Pin Configuration
SSSSSSSSSSSSSSSSSSSS 33333333348777777777 12345678900987654321 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
NT3883F
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NVVVVGCSSNNNCDDDDMNN C ED 3 2NLLLCCCLLRLR CC 21122 D112 ED
1
V2.1 November, 1999
NT3883
Pad Configuration
S 3 2 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 V
E E
S 3 3
S 3 4
S 3 5
S 3 6
S 3 7
S 3 8
S 3 9
S 4 0
S 8 0
S 7 9
S 7 8
S 7 7
S 7 6
S 7 5
S 7 4
S 7 3
S 7 2 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
99
98 97 96 95 94 93
92 91 90 89 88 87 86 85 84 83 82
NT3883H
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
33 V
D D
34 V 3
35 V 2
36 G N D
37 G L 1
38 S L 1
39 S L 2
43 C L 2
44 D L 1
45 D R 1
46 D L 2
47 D R 2
48 M
2
NT3883
Block Diagram
S1 V DD
S2
S39
S40
S41
S42
S79
S80
V2 V3 V EE
80-Bit 4-Level LCD Drivers
M
CL1
80-Bit Latch
DL2 CL2
First 40-Bit Shift Register
Second 40-Bit Shift Register
DR2
SL1
DR1 DL2
SL2
GND
3
NT3883
Absolute Maximum Ratings*
Power Supply Voltage (VDD-GND) . . . . . . -0.3V to 7.0V Power Supply Voltage (VDD-VEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD - 13.5V to VDD + 0.3V Input Voltage . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Temperature . . . . . . . . . . -20GC to + 75GC Storage Temperature . . . . . . . . . . . . . -55GC to + 125GC
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25GC)
Parameter Input Voltage Symbol VIH VIL Output Voltage VOH VOL Vi - Sj Voltage Descending Input Leakage Current Vi Leakage Current Power Supply Current VD1 VD2 IIL CL1, CL2 DL1, DL2*1 V2, V3, VEE *3 *2 Terminal CL1, CL2, DL1, DL2 *1 DR1, DR2 *1 Min. 0.7 VDD 0 VDD - 0.4 -5 Typ. Max. VDD 0.3 VDD 0.4 1.1 1.5 5 Unit V V V V V V IOH = -0.4mA IOL = +0.4mA ION = 0.1mA for one of Sj ION = 0.05mA for each of Sj VIN = 0 or VDD Conditions
2A
IVL IDD
-10 -
-
10 500
2A 2A
S1 to S80 open fCL1 = 1KHz fCL2 = 1MHz
Note *1: SL1 and SL2 determine The Input or Output of DL1, DL2, DR1 and DR2 and the configuration is as follows. Terminal DL1 DR1 DL2 DR2 SL1 = High Output Input SL1 = Low Input Output SL2 = High Output Input SL2 = Low Input Output
*2: Vi - Sj (Vi = VDD, V2, V3, VEE; j = 1 to 80) equivalent circuit (for reference) *3: Input/output current is excluded. When the input is at the intermediate level with CMOS, some excessive
1Kmax. Vi Power Switch 10Kmax. Data Swtich Sj
Current will flow through the input circuit to power supply. To avoid this, the input level must be fixed at high or low state.
4
NT3883
AC Characteristics (VDD = 5.0V, GND = 0V, VEE = 0V, TA = 25GC) Parameter
Data Shift Frequency Clock Width Data Hold Time Data Set-up Time Clock Set-up Time(CL2CL1) Clock Set-up Time(CL1CL2) Clock Rise/Fall Time Data Delay Time High Low Symbol fCL2 tCWH tCWL tDH tSUD tSUC1 tSUC2 tCL tPD Terminal CL2 CL1, CL2 CL2 DL1~2, DR1~2 DL1~2, DR1~2 CL1, CL2 CL1, CL2 CL1, CL2 Min. 800 800 300 300 500 500 Typ. Max. 400 200 500 Unit KHz ns ns ns ns ns ns ns ns
Timing Waveforms
V IH
tCWL
CL2
V IL tCL tCWH tCL tDH
DL1, DL2
tSUD
tSUC1
tPD
V OH
DR1, DR2
V OL
tSUC2
tSUC2
CL1
tCL tCWH tCL
5
NT3883
Pin and Pad Descriptions
Pin No. 1~30, 51~100 33 36 37 38 Pad No. 1~30, 51~100 33 36 37 38 Designation S1~S30, S80~S31 VDD GND CL1 SL1 I/O O P P I I External Connection LCD panel Power supply Power supply Controller MPU Description Segment signal output pins Power for logic circuits 0V Clock to latch serial data Shift left control for 1st 40-bit shift register (see NOTE*4) 39 39 SL2 I MPU Shift left control for 1st 40-bit shift register (see NOTE*4) 43 44 43 44 CL2 DL1 I I/O Controller Controller or NT3882A/NT3 883 Controller or NT3882A/NT3 883 Controller or NT3882A/NT3 883 Controller or NT3882A/NT3 883 Controller Power supply Clock to shift serial data Data input/output of 1st 40-bit shift register (see NOTE*4) Data input/output of 1st 40-bit shift register (see NOTE*4) Data input/output of 2nd 40-bit shift register (see NOTE*4) Data input/output of 2nd 40-bit shift register (see NOTE*4) Alternate signal for LCD drivers Power for LCD drivers No connection
45
45
DR1
I/O
46
46
DL2
I/O
47
47
DR2
I/O
48 31, 34, 35 32, 40, 41, 42, 49,50
48 31, 34, 35 -
M VEE, V3, V2 NC
I P -
NOTE *4: Relation of SL1, SL2, DL1, DR1, DL2 and DR2
SL1 1(High) 0(Low) -
SL2 1(High) 0(Low)
Shift Direction Left(S40 to S1) Right(S1 to S40) Left(S80 to S41) Right(S41 to S80)
DL1
Output Input -
DR1 Input Output -
DL2 Output Input
DR2 Input Output
6
NT3883
Functional Description
NT3883 is a dot matrix LCD segment driver LSI. It operates with the controller, such as NT3881B/C/D, and/or another segment driver LSI NT3882A/3883. NT3883 receives serial data from the controller or another NT3883, converts it to parallel data and then supplies the LCD driving waveforms to the LCD panel. 1. CL1 This signal is used for latching the shift register contents. When CL1 is set at high, the shift register contents are transferred to the 80-bit 4level LCD driver. When CL1 is set at low, the last display output data (S1 to S80) is held. 2. CL2 Clock pulse inputs for the two 40-bit shift registers. The data is shifted to an 80-bit latch at the falling edge of CL2. The clock signal CL2 must be active when operating to refresh shift registers' contents. 3. DL1 Data input/output of the 1 - 40 register. When SL1 is connected to GND or open, the data from LCD controller st th is fed into the 1 - 40 register through DL1 serially. If SL1 is connected to VDD, the DL1 becomes the output of st th the 1 - 40 register. 4. DR1 Data input/output of the 1 - 40 register. When SL1 is th st th connected to GND, the 20 bit of the 1 - 40 register output from DR1. By connecting DR1 to DL2, two 40-bit shift registers cascaded to one 80-bit shift register. If SL1 is connected to VDD, the DR1 becomes the input of st th the 1 - 40 register, in this case, the data may come from DL2. Latched Data 1(High) (Selected) 0(Low) (Non-selected) M 1(High) 0(Low) 1(High) 0(Low)
st th st th
5. DL2 Data input/output of the 41 - 80 register. When SL2 is connected to GND, the data from LCD controller is fed st th into the 41 - 80 register through DL2 serially. If SL2 is connected to VDD, the DL2 becomes the output of the st th 41 - 80 register. 6. DR2 Data input/output of the 41 - 80 register. When SL2 is th st th connected to GND, the 80 bit of the 41 - 80 register output from DR2. By connecting DR2 to DL1 of next NT3882A/3883, the cascade structure is obtained to drive a wider LCD panel. If SL2 is connected to VDD, the st th DR2 becomes the input of the 41 - 80 register, in this case, the data may come from the next NT3882A/3883. 7. SL1 The shift direction of S1 to S40, i.e. 1 to 40 shift register, is selected by SL1. The detail function description is listed in Note*4 of Page5. 8. SL2 The shift direction of S41 to S80, i.e. 41 to 80 shift register, is selected by SL2. The detail function description is listed in Note*4 of Page5. 9. S1 to S80 LCD driver output pins. These 80 bits represent the 80 data bits in the 80-bit latch and one of VDD, V2, V3 and VEE is selected as a LCD driving voltage source according to the combination of latched data level and the alternate signal (M). The truth table is listed as follows:
st th st th st th st th
Output Level of S1 to S80 VEE VDD V3 V2
7
NT3883
Application Circuit (for reference only)
20 Chars x 4 Lines LCD PANEL
C1 - C16
S1
-
S40 D DL1
S1
-
S80 DR2 DL1 CL2 CL1 DR1 M V DD
S1
-
S80 DR2 DL2
CL2
DL2
CL1 M V DD GND
NT3883
NT3883
DR1
V2
V3
V EE
GND
V2
V3
V EE
CL2 CL1
NT3881D
M V DD GND
V1 V2 V3 V4 V5
VR R R R R R
C
C
C
C
C
GND or other negative voltage
8
NT3883
Bonding Diagram
S 3 2 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 V E E 33 V D D 34 V 3 35 V 2 36 G N D 37 G L 1 38 S L 1 39 S L 2 43 C L 2 44 D L 1 45 D R 1 46 D L 2 47 D R 2 48 M 99 S 3 3 98 S 3 4 97 S 3 5 S 3 6 S 3 7 94 S 3 8 93 S 3 9 92 S 4 0 91 S 8 0 S 7 9 S 7 8 88 S 7 7 87 S 7 6 86 S 7 5 85 S 7 4 84 S 7 3 83 S 7 2 82 81 80 79 78 77 76 75 74 73 72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
96 95
90 89
NT3883H
71 70 69 68 67
3 9 4 0 2m
Y
66 65 64
(0,0)
X
63 62 61 60 59 58 57 56 55 54 53 52 51
2 5 9 0 2m
* Connecting IC substrate to VDD or keeping floating is recommended. * Pad window area 1002m
1002m.
9
NT3883
Bonding Dimensions
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 43 44 45 46 47 48 51 52 53 Designation S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE VDD V3 V2 GND CL1 SL1 SL2 CL2 DL1 DR1 DL2 DR2 M S41 S42 S43 X -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1184 -945 -807 -670 -520 -353 -204 -54 95 245 395 545 695 845 995 1185 1195 1195 Y 1677 1557 1437 1317 1197 1077 957 837 717 597 477 357 237 117 -2 -122 -242 -362 -482 -602 -722 -842 -962 -1082 -1202 -1322 -1442 -1562 -1682 -1812 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1812 -1682 -1562 Pad No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 X 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1185 995 875 755 635 515 395 275 155 35 -84 -204 -324 -444 -564 -684 -805 -925 -1045 -1184 unit: 2m Y -1442 -1311 -1202 -1082 -962 -842 -722 -602 -482 -362 -242 -122 -2 117 237 357 477 597 717 837 957 1077 1197 1317 1437 1557 1677 1811 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1811
10
NT3883
Ordering Information
Part No. NT3883H NT3883F Package CHIP FORM 100L QFP
11
NT3883
Package Information QFP 100L Outline Dimensions
HD D 80 65
unit: inches/mm
1
64
24
41
25
e GD
b 40
HE
GE
E
GD c
~ ~
A2 See Detail F Seating Plane
A
y
D
A1
L L1
Detail F
Symbol A A1 A2 b
Dimensions in inches 0.130 Max. 0.004 Min. 0.1120.005 0.014 +0.004 -0.002 0.006 +0.004 -0.002 0.5510.005 0.7870.005 0.0310.006 0.693 NOM. 0.929 NOM. 0.7400.012 0.9760.012 0.0470.008 0.0950.008 0.006 Max. 0G ~ 12G
Dimensions in mm 3.30 Max. 0.10 Min. 2.850.13 0.35 +0.10 -0.05 0.15 +0.10 -0.05 14.000.13 20.000.13 0.800.15 17.60 NOM. 23.60 NOM. 18.800.31 24.790.31 1.190.20 2.410.20 0.15 Max. 0G ~ 12G
c D E e GD GE HD HE L L1 y
6
Notes: 1. Dimensions D & E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only
12

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