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EM78911 8-bit micro-controller micro-
EM78911
I.General Description
The EM78911 is an 8-bit CID (Call Identification) RISC type microprocessor with low power , high speed CMOS technology . Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time clock /counter , internal interrupt , power down mode , LCD driver , FSK decoder ,CALL WAITING decoder, DTMF generator and tri-state I/O . The EM78911 provides a single chip solution to design a CID of calling message_display .
II.Feature
CPU
*Operating voltage range : 2.5V5.5V *16Kx 13 on chip ROM *2.8Kx 8 on chip RAM *Up to 36 bi-directional tri-state I/O ports *8 level stack for subroutine nesting *8-bit real time clock/counter (TCC) *Two sets of 8 bit counters can be interrupt sources *Selective signal sources and trigger edges , and with overflow interrupt *Programmable free running on chip watchdog timer *99.9 single instruction cycle commands *Four modes (internal clock 3.579MHz) 1. Sleep mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn off 2. Idle mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn on 3. Green mode : 3.579MHz clock turn off, CPU and 32.768KHz clock turn on 4. Normal mode : 3.579MHz clock turn on , CPU and 32.768KHz clock turn on *Ring on voltage detector and low battery detector *Input port wake up function *9 interrupt source , 4 external , 5 internal *100 pin QFP or chip *Port key scan function *Clock frequency 32.768KHz *Eight R-option pins
CID
*Operation Volltage 3.5 6V for FSK *Operation Volltage 2.5 6V for DTMF *Bell 202 , V.23 FSK demodulator *DTMF generator *Ring detector on chip
CALL WAITING
*Operation Volltage 3.6 5.5V *Compatible with Bellcore special report SR-TSV-002476 *Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector *Good talkdown and talkoff performance *Sensitivity compensated by adjusting input OP gain
LCD
*LCD operation voltage chosen by software *Common driver pins : 16 *Segment driver pins : 60 *1/4 bias
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EM78911 8-bit micro-controller micro-
*1/8,1/16 duty
III.Application
1. adjunct units 2. answering machines 3. feature phones
IV.Pin Configuration
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 VSS TEST COM8/P60 COM9/P61 COM10/P62 COM11/P63 COM12/P64 COM13/P65 COM14/P66 COM15/P67 SEG40/P54 SEG41/P55 SEG42/P56 SEG43/P57 SEG44/P80 SEG45/P81 SEG46/P82 SEG47/P83 SEG48/P84 SEG49/P85 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
OTP writer PIN NAME 1.VDD 2.VPP 3.DINCK 4.ACLK 5.PGMB 6.OEB 7.DATA 8.GND
AVSS DTMF PLLC RINGTIME RDET1 RING TIP GAIN CWTIP XIN XOUT AVDD COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SEG50/P86 SEG51/P87 SEG52/P90 SEG53/P91 SEG54/P92 SEG55/P93 SEG56/P94 SEG57/P95 SEG58/P96 SEG59/P97 P70/INT0 P71/INT1 P72/INT2 P73/INT3 P74 P75 P76 P77 /RESET VDD
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Fig1. Pin Assignment
MASK ROM PIN NAME VDD,AVDD /RESET P77 P76 P75 P74 P73 VSS,AVSS P.S.
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EM78911 8-bit micro-controller micro-
V.Functional Block Diagram
CPU CPU
RAM RAM
TIMING CONTROL TIMING CONTROL
LCD DRIVER LCD DRIVER
LCD
TIMER TIMER
IO PORT IO PORT
I/O
ROM ROM
FSK FSK DTMF DTMF CALL WAITING CALL WAITING
Fig2. Block diagram1
Xin Xout WDT timer Oscillator timing control R1(TCC) Control sleep and wake-up on I/O port GENERAL RAM R4 prescalar Interruption control Instruction register R3 R5 ALU ROM R2 STACK
ACC
Instruction decoder
DATA & CONTROL BUS
2.5k RAM PORT5 FSK DTMF CALL WAITING IOC5 R5 PORT6 IOC6 R6 PORT7 IOC7 R7 PORT8 IOC8 R8 PORT9 IOC9 R9
P54~P57
P60~P67
P70~P77
P80~P87
P90~P97
Fig3. Block diagram2
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EM78911 8-bit micro-controller micro-
VI.Pin Descriptions
PIN VDD AVDD GND AVSS Xtin Xtout COM0..COM7 COM8..COM15 SEG0...SEG43 SEG44..SEG51 SEG52..SEG59 PLLC TIP RING CWTIP GAIN RDET1 /RING TIME INT0 INT1 INT2 INT3 P5.4 ~P5.7 P6.0 ~P6.7 P7.0 ~P7.7 I/O POWER POWER I O O O (PORT6) O O (PORT8) O (PORT9) I I I I I I I DESCRIPTION digital power analog power digital ground analog ground Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Common driver pins of LCD drivers Segment driver pins of LCD drivers PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG. Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with AVSS Should be connected with TIP side of twisted pair lines for FSK. Should be connected with RING side of twisted pair lines for FSK. Should be connected with TIP side of twisted pair lines for CW. OP output pin for gain adjustment. Detect the energy on the twisted pair lines . These two pins coupled to the twisted pair lines through an attenuating network. Determine if the incoming ring is valid.An RC network may be connected to the pin. PORT7(0)~PORT7(3) signal can be interrupt signals.
P8.0 ~P8.7 P9.0 ~P9.7
TEST DTMF RESET
PORT7(0) PORT7(1) Int2 and int3 has the same interrupt flag. PORT7(2) PORT7(3) PORT7(4:7) IO port PORT5 PORT 5 can be INPUT or OUTPUT port each bit. Shared with LCD segment signals PORT6 PORT 6 can be INPUT or OUTPUT port each bit. Shared with LCD common signals PORT7 PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Key scan function. PORT8 PORT 8 can be INPUT or OUTPUT port each bit. And shared with Segment signal. PORT9 PORT 9 can be INPUT or OUTPUT port each bit. And can be set to wake up watch dog timer. And shared with Segment signal. I Test pin into test mode , normal low O DTMF tone output I
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EM78911 8-bit micro-controller micro-
VII.Functional Descriptions
VII.1 Operational Registers
1. R0 (Indirect Addressing Register) * R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). 2. R1 (TCC) * Increased by an external signal edge applied to TCC , or by the instruction cycle clock. Written and read by the program as any other register. 3. R2 (Program Counter) * The structure is depicted in Fig. 4. * Generates 16K x 13 on-chip ROM addresses to the relative programming instruction codes. * "JMP" instruction allows the direct loading of the low 10 program counter bits. * "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. * "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. * "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. * "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. * "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
PC
A13 A12 A11 A10
A9 A8
A7~A0 RET RETL RETI
0000 PAGE0 0000~03FF 0001 PAGE1 0400~07FF 0010 PAGE3 0800~0BFF
STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8
1110 PAGE14 3800~3BFF 1111 PAGE15 3C00~3FFF
Fig.4 Program counter organization
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EM78911 8-bit micro-controller micro-
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F
REGISTER R0 R1(TCC) R2(PC) R3(STATUS) R4(RSR) R5(ROM PAGE & R5) R6(PORT6) R7(PORT7) R8(PORT8) R9(PORT9) RA(CLK,FSK) RB(DTMF) RC(2.5K RAM ADDRESS) RD(2.5K RAM DATA) RE(WDT) RF(INT FLAG) 16X8 COMMON REGISTER BANK0 ~BANK3 32X8 ~32X8 REGISTER
CONTROL REGISTER (PAGE0)
CONTROL REGISTER (PAGE1)
page0 IOC6 IOC7 IOC8 IOC9 IOCA IOCB(LCD ADDRESS) IOCC(LCD DATA) IOCD(PULL HIGH) IOCE(IO, LCD) IOCF(INT CONTROL)
page1 IOCB(COUNTER1) IOCC(COUNTER2) IOCD(R-OPTION)
RC(ADDRESS) RD(DATA) 0 BANK1 BANK2 ..............BANK10 : 256X8 256X8 ................256X8 255
Fig.5
Data memory configuration
4. R3 (Status Register) 7 6 5 4 3 2 1 0 CAS PAGE T P Z DC C * Bit 0 (C) Carry flag * Bit 1 (DC) Auxiliary carry flag * Bit 2 (Z) Zero flag * Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. * Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 x x .. don't care REMARK
* Bit 5 unused * Bit 6 PAGE : change IOCB ~ IOCE to another page , 0/1 => page0 / page1 * Bit7 (CAS : CALL WAITING Output) 0/1= CW data valid/No data
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EM78911 8-bit micro-controller micro-
5. R4 (RAM Select Register) * Bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode. * Bits 6 ~ 7 determine which bank is activated among the 4 banks. * See the configuration of the data memory in Fig. 5. 6. R5 (Program Page Select Register) 7 6 R57 R56 5 R55 4 R54 3 PS3 2 PS2 1 PS1 0 PS0
* Bit 0 (PS0) ~ 3 (PS3) Page select bits Page select bits PS3 PS2 PS1 PS0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Program memory page (Address) Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15
*User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained by EMC's complier. It will change user's program by inserting instructions within program. *Bit4~7 : PORT5 4-bit I/O register
6. R6 ~ R9 (Port 6 ~ Port 9) * Four 8-bit I/O registers. 7. RA (FSK Status Register)(bit 0,1,2,4 read only) 7 6 5 4 3 2 1 /358E /LPD /LOW_BAT /FSKPWR DATA /CD IDLE * Bit0 (Read Only) (Ring detect signal) 0/1 : Ring Valid/Ring Invalid * Bit1(Read Only)(Carrier detect signal) 0/1 : Carrier Valid/Carrier Invalid * Bit2(Read Only)(FSK demodulator output signal) Fsk data transmitted in a baud rate 1200 Hz. * Bit3(read/write)(FSK block power up signal) 1/0 : FSK demodulator block power up/FSK demodulator power down
0 /RD
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EM78911 8-bit micro-controller micro-
* The relation between Bit0 to Bit3 is shown in Fig.6.
SLEEP MODE Begin set /FSKPWR='0' sleep mode /RINGTIME ='0' or external keys pressed
No
/RD and /CD ='1' /RD and /CD ='1' and nothing to do for 30 sec , /FSKPWR='0' wake up mode
/RINGTIME ='0' or external keys pressed Yes WAKE UP MODE 8-bit wake up and set /FSKPWR='1' accept data from FSK decoder
/FSKPWR='1' FSK decoder begin its work
DATA transfer to Micro Yes /RD and /CD ='1' data end and 30 sec nothing to do. No
STATE Diagram between 8-bit and FSK decoder
Flow Diagram between 8-bit and FSK decoder
Fig6. The relation between Bit0 to Bit3. * Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal . If the VDD voltage is under low power range (controlled by IOCA bit0) then sends a '0' signal to /LOW_BAT bit or a '1' signal to this Bit. * Bit5(read/Write)(Low battery detect enable) 0/1 = low battery detect DISABLE/ENABLE. The relation between /LPD,/POVD and /LOW_BAT can see Fig7.
Vdd s2 1 on 0 off 1 on To reset /POVD /LPD
to Low bat + 1 on Vref s2 1 on 0 off
/LPD
Fig7. The relation between /LPD,/POVD * Bit6(read/write)(PLL enable signal) 0/1=DISABLE/ENABLE The relation between 32.768K and 3.579M can see Fig8.
PLL 3 .5 7 9 M H z S u b -c lo c k 3 2 .7 6 8 K H z 1 R A b it6 s w itc h 0 T o s y s te m c lo c k
Fig8. The relation between 32.768K and 3.579K .
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EM78911 8-bit micro-controller micro-
* Bit7 IDLE: sleep mode selection bit 0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go. These two modes can be waken up by TCC clock or Watch Dog or PORT9 and run from "SLEP" next instruction.
IDLE mode GREEN mode NORMAL mode RA(7,6)=(1,0) RA(7,6)=(x,0) RA(7,6)=(x,1) + SLEP no SLEP no SLEP TCC time out Wake-up Interrupt Interrupt + Interrupt + Next instruction WDT time out RESET Wake-up RESET RESET + Next instruction Port9 RESET Wake-up X X /RINGTIME pin + Next instruction PORT70~73 X Wake-up Interrupt Interrupt + Interrupt + Next instruction *P70 ~ P73 's wakeup function is controlled by IOCF(1,2,3) and ENI instruction. *P70 's wakeup signal is a rising or falling signal defined by CONT REGISTER bit7. */RINGTIME pin , Port9 ,Port71,Port72 and Port73 's wakeup signal is a falling edge signal.
Wakeup signal
SLEEP mode RA(7,6)=(0,0) + SLEP X
8.
RB(DTMF tone row and column register) (read/write) 7 6 5 4 3 2 1 c7 c6 c5 c4 r3 r2 r1 * Bit 0 - Bit 3 are row-frequency tone. * Bit 4 - Bit 7 are column-frequency tone. * Initial RB is equal to high. Bit 7 ~ 0 are all "1" , turn off DTMF power . bit 3~0 1110 1101 1011 0111 Column freq bit 7~4 Row freq 699.2Hz 771.6Hz 854Hz 940.1Hz
0 r0
1 4 7 * 1203Hz 1110
2 5 8 0 1331.8Hz 1101
3 6 9 # 1472Hz 1011
A B C D 1645.2Hz 0111
9.
RC(CALLER ID address)(read/write) 7 6 5 4 3 2 CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2 * Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256. RD(CALLER ID RAM data)(read/write) * Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
1 CIDA1
0 CIDA0
10.
User can see IOCA register how to select CID RAM banks.
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EM78911 8-bit micro-controller micro-
11.
RE(LCD Driver,WDT Control)(read/write) 7 6 5 4 3 2 1 0 CWPWR /WDTE /WUP9H /WUP9L /WURING LCD_C2 LCD_C1 LCD_M * Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency. * Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the "LCD_C2,LCD_C1" to "00". LCD_C2,LCD_C1 00 0 1 1 1 LCD Display Control change duty Disable(turn off LCD) Blanking LCD display enable LCD_M 0 1 : : duty 1/16 1/8 : : bias 1/4 1/4
* Bit3 (/WURING, RING Wake Up Enable): used to enable the wake-up function of /RINGTIME input pin. (1/0=enable/disable) * Bit4 (/WUP9L, PORT9 low nibble Wake Up Enable): used to enable the wake-up function of low nibble in PORT9.(1/0=enable/disable) * Bit5 (/WUP9H, PORT9 high nibble Wake Up Enable): used to enable the wake-up function of high nibble in PORT9.(1/0=enable/disable) * Bit6 (/WDTE,Watch Dog Timer Enable) Control bit used to enable Watchdog timer.(1/0=enable/disable) The relation between Bit3 to Bit6 can see the diagram 9. * Bit7(Power control of Call Waiting circuit) .(1/0=enable circuit /disable circuit) Please enable PLL before enable Call Waiting circuit.
/WURING /RINGTIME /WUP9L PORT9(3:0) /WUP9H PORT9(7:4) /WDTE /WDTEN 0/1=enable/disable
fig.9 12. RF (Interrupt Status Register) 7 6 INT3 FSK/CW
Wake up function and control signal
5 C8_2
4 C8_1
3 2 1 INT2 INT1 INT0
0 TCIF
* "1" means interrupt request, "0" means non-interrupt * Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows . * Bit 1 (INT0) external INT0 pin interrupt flag . * Bit 2 (INT1) external INT1 pin interrupt flag . * Bit 3 (INT2) external INT2pin interrupt flag . * Bit 4 (C8_1) internal 8 bit counter interrupt flag . * Bit 5 (C8_2) internal 8 bit counter interrupt flag . * Bit 6 ( FSK/CW ) FSK data or Call waiting data interrupt flag * Bit 7 (INT3) external INT3 pin interrupt flag. * High to low edge trigger , Refer to the Interrupt subsection. * IOCF is the interrupt mask register. User can read and clear.
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EM78911 8-bit micro-controller micro-
13. R10~R3F (General Purpose Register) * R10~R3F (Banks 0~3) all are general purpose registers.
VII.2 Special Purpose Registers
1. A (Accumulator) * Internal data transfer, or instruction operand holding * It's not an addressable register. 2. CONT (Control Register) 7 6 5 4 3 2 1 0 TS TE PAB PSR2 PSR1 PSR0 INT_EDGE INT * Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 PSR1 PSR0 TCC Rate WDT Rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 * Bit 3 (PAB) Prescaler assignment bit. 0/1 : TCC/WDT * Bit 4 (TE) TCC signal edge 0: increment from low to high transition on TCC 1: increment from high to low transition on TCC * Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: 16.384KHz * Bit 6 : (INT)INT enable flag
0: interrupt masked by DISI or hardware interrupt 1: interrupt enabled by ENI/RETI instructions
* Bit 7 : INT_EDGE 0:P70 's interruption source is a rising edge signal. 1:P70 's interruption source is a falling edge signal. * CONT register is readable and writable.
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EM78911 8-bit micro-controller micro-
3. IOC5 (I/O Port Control Register)
7 IOC57
6 IOC56
5 IOC55
4 IOC54
3 0
2 0
1 0
0 P5S
* Bit0: P5S is switch register for I/O port or LCD signal switching. 0/1= normal I/O port/SEGMENT output . * Bit1~3: unused * Bit 4 to Bit7 are PORT5 I/O direction control registers. * "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output. 4. IOC6 ~ IOC9 (I/O Port Control Register) * four I/O direction control registers. * "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output. * User can see IOCB register how to switch to normal I/O port. 5. IOCA (CALLER ID RAM,IO ,PAGE Control Register)(read/write,initial "00000000")
7 P8SH
6 P8SL
5 0
4 3 2 1 0 CALL_4 CALL_3 CALL_2 CALL_1 RANGE
* Bit0 : register to control low power detection range . 0/1=3.2V/3.6V * Bit4~Bit1:"000" to "1001" are ten blocks of CALLER ID RAM area. User can use 2.5K RAM with RD ram address. * Bit 5 unused * Bit6: port8 low nibble switch, 0/1= normal I/O port/SEGMENT output . * Bit7: port8 high nibble switch , 0/1= normal I/O port/SEGMENT output 6. IOCB (LCD ADDRESS) PAGE0 : Bit6 ~ Bit0 = LCDA6 ~ LCDA0 The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below: COM15 ~ COM8 40H (Bit15 ~ Bit8) 41H : : : : 7AH 7BH 7CH : 7FH COM7 ~ COM0 00H (Bit7 ~ Bit0) 01H : : : : 4AH 3BH 3CH : 3FH
SEG0 SEG1 : : : : SEG58 SEG59 Empty : Empty
PAGE1 : 8 bit up-counter (COUNTER1) preset and interruption , it will count from "00".
read out register . ( write = preset ) . After a
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EM78911 8-bit micro-controller micro-
7. IOCC (LCD DATA) PAGE0 : Bit7 ~ Bit0 = LCD RAM data register PAGE1 : 8 bit up-counter (COUNTER2) preset and read out register . ( write = preset) will count from "00". 8. IOCD (Pull-high Control Register) PAGE0: 7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 * Bit 0 ~ 7 (/PH#) Control bit used to enable the pull-high of PORT7(#) pin. 1: Enable internal pull-high 0: Disable internal pull-high PAGE1: 7 6 5 4 3 2 1 0 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 * Bit 7 ~ 0 (RO7~0) Control bit used to enable the R-OPTION of PORT97~PORT90 pin. 1: Enable 0: Disable RO is used for R-OPTION . Setting RO to `1' will enable the status of R-option pin (P90 ~ P97) to read by controller. Clearing RO will disable R-option function. If the R-option function is used, user must connect PORT9 pins to GND by 560K external register . If the register is connected/disconnected , the R9 will read as " 0/1" when RO is set to `1'. After a interruption , it
9. IOCE (Bias,PLL Control Register) PAGE0 : 7 6 5 4 3 2 1 0 P9SH P9SL P6S Bias3 Bias2 Bias1 0 SC * Bit 0 :SC (SCAN KEY signal ) 0/1 = disable/enable. Once you enable this bit , all of the LCD signal will have a low pulse during a common period. This pulse has 30us width. Please use the procedure to implement the key scan function. a. set port7 as input port b. set IOCD page0 port7 pull high c. enable scan key signal d. Once push a key . Set RA(6)=1 and switch to normal mode. e. Blank LCD. Disable scan key signal. f. Set P6S =0. Port6 sent probe signal to port7 and read port7. Get the key. g. Note!! A probe signal should be delay a instruction at least to another probe signal. h. Set P6S =1. Port6 as LCD signal. Enable LCD.
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EM78911 8-bit micro-controller micro-
KEY5 P63
KEY1 KEY2
P62 KEY3 P61 KEY4 P60
P73
P72
P71
P70
Fig.10. Key scan circuit
com2
vdd v1 v2 v3 vlcd Gnd vdd v1 v2 v3 vlcd Gnd
seg
30us
Fig.11.key scan signal * Bit 1 :PORT7 PULL HIGH register option. Please use default value.
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EM78911 8-bit micro-controller micro-
* Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage . LCD operate voltage Vop (VDD 5V) VDD=5V 3.0V 0.60VDD 000 3.3V 0.66VDD 001 3.7V 0.74VDD 010 4.0V 0.82VDD 011 4.4V 0.87VDD 100 4.7V 0.93VDD 101 4.8V 0.96VDD 110 5.0V 1.00VDD 111 * Bit5:port6 switch , 0/1= normal I/O port/COMMON output * Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch PAGE1 : 7 6 5 4 3 2 1 0 OP77 OP76 C2S C1S PSC1 PSC0 CDRD 0 * Bit0: unused * Bit1: cooked data or raw data select bit , 0/1 ==> cooked data/raw data * Bit3~Bit2: counter1 prescaler , reset=(0,0) (PSC1,PSC0) = (0,0)=>1:1 , (0,1)=>1:4 , (1,0)=>1:8 , (1,1)=>reserved * Bit4:counter1 source , (0/1)=(32768Hz/3.579MHz if enable) scale=1:1 * Bit5:counter2 source , (0/1)=(32768Hz/3.579MHz if enable) scale=1:1 * Bit6:P76 opendrain control (0/1)=(disable/enable) * Bit7:P77 opendrain control (0/1)=(disable/enable)
10. IOCF (Interrupt Mask Register) 7 6 INT3 FSK/CW
5 C8_2
4 C8_1
3 2 1 INT2 INT1 INT0
0 TCIF
* Bit 0 ~ 7 interrupt enable bit. 0: disable interrupt 1: enable interrupt * IOCF Register is readable and writable.
VII.3 TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. * An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. * See the prescaler ratio in CONT register. * Fig. 10 depicts the circuit diagram of TCC/WDT. * Both TCC and prescaler will be cleared by instructions which write to TCC each time. * The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
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EM78911 8-bit micro-controller micro-
* The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
16.38KHz
Fig. 10 Block diagram of TCC WDT
VII.4 I/O Ports
The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by software control. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC6 ~ IOC9 ) under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.11.
Fig. 11 The circuit of I/O port and I/O control register
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EM78911 8-bit micro-controller micro-
VII.5 RESET and Wake-up
The RESET can be caused by (1) Power on reset, or Voltage detector (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit. If Voltage detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 12.
Fig. 12 Block diagram of Reset of controller
Once the RESET occurs, the following functions are performed.
* * * * * * * The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler are cleared. The Watchdog timer is disabled. The CONT register is set to all "1" The other register (bit7..bit0) R5 = PORT IOC5 = "11110000" R6 = PORT IOC6 = "11111111" R7 = PORT IOC7 = "11111111" R8 = PORT IOC8 = "11111111" R9 = PORT IOC9 = "11111111" RA = "x00x0xxx IOCA = "00000000" RB = "11111111" Page0 IOCB = "00000000" Page1 IOCB = "00000000" RC = "00000000" Page0 IOCC = "0xxxxxxx" Page1 IOCC = "00000000" RD = "xxxxxxxx" Page0 IOCD = "00000000" Page1 IOCD = "00000000" RE = "00000000" Page0 IOCE = "00000000" Page1 IOCE = "00000000" RF = "00000000" IOCF = "00000000"
The controller can be awakened from SLEEP mode or IDLE mode (execution of "SLEP" instruction, named as SLEEP MODE or IDLE mode) by (1)TCC time out (2) WDT time-out (if enabled) or, (3) external input at PORT9. The three cases will cause the controller wake up and run from next instruction. After wake-up , user should control WATCH DOG in case of reset in GREEN mode or NORMAL mode. The last two should be open
17
EM78911 8-bit micro-controller micro-
RE register before into sleep mode or IDLE mode . The first one case will set a flag in RF bit0 .But it will not go to address 0x08.
18
EM78911 8-bit micro-controller micro-
VII.6 Interrupt
The CALLER ID IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow interrupt (internal) , two 8-bit counters overflow interrupt . If these interrupt sources change signal from high to low , then RF register will generate '1' flag to corresponding register if you enable IOCF register. RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal interrupt available. Internal signals include TCC,CNT1,CNT2,FSK and CALL WAITING data. The last two will generate a interrupt when the data trasient from high to low. External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these signal will cause interrupt , or these signals will be treated as general input data . After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the hardware inturrept is 008H. TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next instruction from "SLEP" instruction. These two cases will set a RF flag.
It is very important to save ACC,R3 and R5 when processing a interruption. Address Instruction Note 0x08 DISI ;Disable interrupt 0x09 MOV A_BUFFER,A ;Save ACC 0x0A SWAP A_BUFFER 0x0B SWAPA 0x03 ;Save R3 status 0x0C MOV R3_BUFFER,A 0x0D MOV A,0x05 ;Save ROM page register 0x0E MOV R5_BUFFER,A : : : : : MOV A,R5_BUFFER ;Return R5 : MOV 0X05,A : SWAPA R3_BUFFER ;Return R3 : MOV 0X03,A : SWAPA A_BUFFER ;Return ACC : RETI
VII.7 Instruction Set
Instruction set has the following features: (1). Every bit of any register can be set, cleared, or tested directly. (2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
19
EM78911 8-bit micro-controller micro-
The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 0110 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 0010 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 0100 rrrr 0000 rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) STATUS AFFECTE D None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C
20
EM78911 8-bit micro-controller micro-
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0110 0110 0111
10rr 11rr 00rr
rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001
06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk
RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
0111 01rr 0111 10rr 0111 11rr 100b bbrr 101b bbrr 110b bbrr 111b bbrr 00kk kkkk 01kk kkkk 1000 kkkk 1001 kkkk 1010 kkkk 1011 kkkk 1100 kkkk 1101 kkkk 1110 0000 1110 1111
R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(3:0) k+A A
C C None None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC
1000 kkkk kkkk kkkk
VII.8 CODE Option Register
The CALLER ID IC has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 7 6 5 4 3 2 1 0 /POVD MCLK * Bit 0 : main clock selection. 0/1 = 3.58MHZ / 1.84MHZ * Bit 1 :(/POVD) : Power on voltage detector. 0: enable 1: disable /POVD 2.2V reset power on reset Low power Low power detect sleep mode detect without controlled by current reset RA(5) 1 no yes Yes Yes 1uA 0 yes yes Yes yes 15uA * Bits 2~7 : unused, must be "0"s.
VII.9 FSK FUNCTION
21
EM78911 8-bit micro-controller micro-
VII.9.1 Functional Block Diagram
Tip Ring
Band Pass Filter
FSK demodul
Data Valid Energy Det Circuit /FSKPWR
DATA OUT /CD
Ring det1 /Ring Time
Ring Det Circuit
Power Up
/RD
OSC in OSC out
CLOCK
Fig13. FSK Block Diagram
VII.9.2 Function Descriptions
The CALLER ID IC is a CMOS device designed to support the Caller Number Deliver feature which is offered by the Regional Bell Operating Companies.The FSK block comprises two paths: the signal path and the ring indicator path. The signal path consist of an input differential buffer,a band pass filter, an FSK demodulator and a data valid with carrier detect circuit. The ring detector path includes a clock generator, a ring detect circuit . In a typical application, the ring detector maintains the line continuously while all other functions of the chip are inhibited. If a ring signal is sent, the /RINGTIME pin will has a low signal. User can use this signal to wake up whole chip or read /RD signal from RA register. A /FSKPWR input is provided to activate the block regardless of the presence of a power ring signal. If /FSKPWR is sent low, the FSK block will power down whenever it detects a valid ring signal, it will power on when /FSKPWR is high. The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter. The output data is then made available at DATA OUT pin. This data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date , time and calling number. If no data is present, the DATA OUT pin is held in a high state. This is accomplished by an carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid and thus the demodulated data is transferred to DATA OUT pin . If it is not, then the FSK demodulator is blocked.
VII.9.3 Ring detect circuit
When Vdd is applied to the circuit, the RC network will charge cap C1 to Vdd holding /RING TIME off . The resistor network R2 to R3 attenuates the incoming power ring applied to the top of R2. The values given
22
EM78911 8-bit micro-controller micro-
have been chosen to provide a sufficient voltage at DET1 pin, to turn on the Schmitt trigger input. When Vt+ of the Schmitt is exceeded, cap C1 will discharge. The value of R1 and C1 must be chosen to hold the /RING TIME pin voltage below the Vt+ of the Schmitt between the individual cycle of the power ring. With /RINGTIME enabled, this signal will be a /RD signal in RA throught a buffer.
/Ring Time
R1
/Ring Time
Vdd
C1 R2
/RD
Det1
R3
Fig14. ring detect circuit
VII.10 DTMF ( Dual Tone Multi Frequency ) Tone Generator
Built-in DTMF generator can generate dialing tone signals for telephone of dialing tone type. There are two kinds of DTMF tone . One is the group of row frequency, the other is the group of column frequency, each group has 4 kinds of frequency , user can get 16 kinds of DTMF frequency totally. DTMF generator contains a row frequency sine wave generator for generating the DTMF signal which selected by low order 4 bits of RB and a column frequency sine wave generator for generating the DTMF signal which selected by high order 4 bits of RB. This block can generate single tone by filling one bit zero to this register. If all the values are high , the power of DTMF will turn off until one or two low values. Either high or low 4 bits must be set by an effective value, otherwise, if any ineffective value or both 4 bits are load effective value, tone output will be disable. Recommend value refer to table as follow please :
SYSTEM CLOCK Low frequency generator ROW Register
DTMF low-freq selection
Sine wave generator
DTMF tone Adder output
COLUMN Register
DTMF high-freq selection
Sine wave generator
High frequency generator
23
EM78911 8-bit micro-controller micro-
Fig15. DTMF Block Diagram
* RB ( DTMF Register )
. Bit 0 - Bit 3 are row-frequency tone. . Bit 4 - Bit 7 are column-frequency tone. . Initial RB is equal to HIGH. . Except below values of RB ,the other values of RB are not effect. output will be disable and there is no tone output. . Bit 7 ~ 0 are all "1" , turn off DTMF power . bit 3~0 1110 1101 1011 0111 Column freq bit 7~4 Row freq 699.2Hz 771.6Hz 854Hz 940.1Hz
If RB is set by ineffective value, the DTMF
1 4 7 * 1203Hz 1110
2 5 8 0 1331.8Hz 1101
3 6 9 # 1472Hz 1011
A B C D 1645.2Hz 0111
VII.11 LCD Driver
The CALLER ID IC can drive LCD directly and has 60 segments and 16 commons that can drive 60*16 dots totally. LCD block is made up of LCD driver , display RAM, segment output pins , common output pins and LCD operating power supply pins. Duty , bias , the number of segment , the number of common and frame frequency are determined by LCD mode register . LCD control register. The basic structure contains a timing control which uses the basic frequency 32.768KHz to generate the proper timing for different duty and display access. RE register is a command register for LCD driver, the LCD display( disable, enable, blanking) is controlled by LCD_C and the driving duty and bias is decided by LCD_M and the display data is stored in data RAM which address and data access controlled by registers IOCB and IOCC.
32.768KHz IOCB(address) LCD timing control IOCC(data) RAM
RE(LCD_C,LCD_M)
LCD duty control Display data control
Bias control
LCD COMMON control
LCD SEGMENT control
Vdd-Vlcd
COM
SEG
Fig16. LCD DRIVER CONTROL 24
EM78911 8-bit micro-controller micro-
VII.11.1 LCD Driver Control
RE(LCD Driver Control)(initial state "00000000") 7 6 5 4 3 2 1 0 LCD_C2 LCD_C1 LCD_M *Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency. *Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the LCD_C to "00". LCD_C2,LCD_C1 LCD Display Control LCD_M duty bias 00 change duty 0 1/16 1/4 Disable(turn off LCD) 1 1/8 1/4 01 Blanking : : 11 LCD display enable : :
VII.11.2
LCD display area
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15 ~ COM8 40H (Bit15 ~ Bit8) 41H : : 7BH 7CH 7DH 7EH 7FH
COM7 ~ COM0 00H (Bit7 ~ Bit0) 01H : : 3BH 3CH 3DH 3EH 3FH
SEG0 SEG1 : : SEG59 empty empty empty empty
*IOCB(LCD Display RAM address) 7 6 5 4 3 2 1 0 LCDA6 LCDA5 LCDA4 LCDA3 LCDA2 LCDA1 LCDA0 Bit 0 ~ Bit 6 select LCD Display RAM address up to 120. LCD RAM can be write whether in enable or disable mode and read only in disable mode. *IOCC(LCD Display data) : Bit 0 ~ Bit 8 are LCD data.
VII.11.3
LCD COM and SEG signal
* COM signal : The number of COM pins varies according to the duty cycle used, as following: in 1/8 duty mode COM8 ~ COM15 must be open. in 1/16 duty mode COM0 ~ COM15 pins must be used. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 .. COM15 1/8 o o o o o o o o x .. x 1/16 o o o o o o o o o .. o x:open,o:select
25
EM78911 8-bit micro-controller micro-
* SEG signal: The 60 segment signal pins are connected to the corresponding display RAM address 00h to 3Bh. The high byte and the low byte bit7 down to bit0 are correlated to COM15 to COM0 respectively . When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a nonselect signal is sent to the corresponding segment pin. *COM, SEG and Select/Non-select signal is shown as following:
frame com0
Vdd V1 V2 V3 VLCD Vdd V1 V2 V3 VLCD Vdd V1 V2 V3 VLCD Vdd V1 V2 V3 VLCD dark Vdd V1 V2 V3 VLCD light
com1
com2
seg
seg
Fig.17 Lcd wave 1/4 bias
26
EM78911 8-bit micro-controller micro-
VII.11.4
LCD Bias control
IOCE (Bias Control Register) 7 6 5
4 3 2 1 0 Bias3 Bias2 Bias1 * Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage . The circuit can refer ti figure15. LCD operate voltage Vop (VDD 5V) VDD=5V 3.0V 0.60VDD 000 3.3V 0.66VDD 001 3.7V 0.74VDD 010 4.0V 0.82VDD 011 4.4V 0.87VDD 100 4.7V 0.93VDD 101 4.8V 0.96VDD 110 5.0V 1.00VDD 111 * Bit 5~7 unused
78810/78910 Vdd R R Vop R R V2 V3 Vlcd : : 000 001 010 011 100 101 110 Vss 111 0.4R 0.4R 0.3R 0.3R 0.2R 0.1R 0.1R V1 8.2R
Vop=Vdd-Vlcd R=1K
Bias3~1
MUX
Fig.18 LCD bias circuit
27
EM78911 8-bit micro-controller micro-
VII.12 CALL WAITING Function Description
TIP FSK data RING FSK BLOCK
GAIN CWTIP + Vdd/2 Band Pass Filter Voltage Reference Clock Generator Level Detect Digital Detection Algorithm CAS 0: DATA valid 1: DATA invalid
call waiting circuit power control
Fig.19 Call Waiting Block Diagram
Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. This way the customer can still receive important calls while engaged in a current call. The CALL WAITING DECODER can detect CAS(Call-Waiting Alerting Signal 2130Hz plus 2750Hz) and generate a valid signal on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. The call waiting decoder has four blocks, including pre-amplifier, band pass filter, level detect and digital detection algorithm. In a typical application, after enabling CW circuit (by RE BIT7 CWPWR) this IC receives Tip and Ring signals from twisted pairs. The signals as inputs of pre-amplifier, and the amplifier sends input signal to a band pass filter. Once the signal is filtered, the digital detection block decodes the information and sends it to R3 register bit7 . The output data made available at R3 CAS bit. The data is CAS signals. The CAS is normal high. When this IC detects 2130Hz and 2750Hz frequency, then CAS pin goes to low.
28
EM78911 8-bit micro-controller micro-
VIII.Absolute Operation Maximum Ratings
RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL Vdd Vin Ta VALUE -0.3 To 6 -0.5 TO Vdd +0.5 0 TO 70 UNIT V V
IX DC Electrical Characteristic
(Ta=0C ~ 70C, VDD=5V5%, VSS=0V) (VDD=2.5V to 6V for CPU ; VDD=3.5V to 6V for FSK ; VDD=2.5V to 6V for DTMF ) Symbol Parameter Condition Min Typ Max IIL1 Input Leakage Current for VIN = VDD, VSS 1 input pins IIL2 Input Leakage Current for VIN = VDD, VSS 1 bi-directional pins VIH Input High Voltage 2.5 VIL Input Low Voltage 0.8 VIHT Input High Threshold /RESET, TCC, RDET1 2.0 Voltage VILT Input Low Threshold /RESET, TCC,RDET1 0.8 Voltage VIHX Clock Input High Voltage OSCI 3.5 VILX Clock Input Low Voltage OSCI 1.5 VHscan Key scan Input High Voltage Port6 for key scan 3.5 VLscan Key scan Input Low Voltage Port6 for key scan 1.5 VOH1 Output High Voltage IOH = -1.6mA 2.4 (port6,7,8) (port9) IOH = -6.0mA 2.4 VOL1 Output Low Voltage IOL = 1.6mA 0.4 (port6,7,8) (port9) IOL = 6.0mA 0.4 Vcom Com voltage drop Io=+/- 50 uA 2.9 Vseg Segment voltage drop Io=+/- 50 uA 3.8 Vlcd LCD drive reference voltage Contrast adjustment IPH Pull-high current Pull-high active input pin -10 -15 at VSS ISB1 Power down current All input and I/O pin at 1 4 (SLEEP mode) VDD, output pin floating, WDT disabled 65 80 ISB2 Low clock current CLK=32.768KHz, FSK, (GREEN mode) DTMF, CW block disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD enable 45 60 ISB3 Low clock current CLK=32.768KHz, FSK, (IDLE mode) DTMF, CW block disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD enable Unit A A V V V V V V V V V V V V V V A A A
A
29
EM78911 8-bit micro-controller micro-
ICC
Operating supply current (NORMAL mode)
CPU disable /RESET=High, CLK=3.579MHz, output pin floating,LCD enable, FSK, DTMF, CW Fblock disable
1.5
1.8
mA
IX AC Electrical Characteristic
(Ta=0C ~ 70C, VDD=5V, VSS=0V) Parameter Symbol Input CLK duty cycle Dclk Instruction cycle time Tins Device delay hold time Tdrh TCC input period Ttcc Watchdog timer period Twdt Note 1: N= selected prescaler ratio. Conditions 32.768K 3.579M Note 1 Ta = 25C (Tins+20)/N 18 Min 45 Typ 50 60 550 18 Max 55 Unit % us ns ms ns ms
(FSK Band Pass Filter AC Characteristic)(Vdd=+5V,Ta=+25) CHARACTERISTIC MIN input sensitivity TIP and RING -40 pin1 and pin2 Vdd=+5V (call waiting Band Pass Filter AC Characteristic) (VDD=+5V,Ta=+25C) CHARACTERISTIC MIN input sensitivity TIP and RING pins ,Vdd=+5V, Input G=1
TYP -48
MAX --
UNIT dBm
TYP -38
MAX
UNIT dBm
Description OSC start up(32.768KHz) (3.579MHz PLL) (FSK AC Characteristic) Carrier detect low Data out to Carrier det low Power up to FSK(setup time) /RD low to Ringtime low End of FSK to Carrier Detect high (Call waiting AC Characteristic)
Symbol Tosc
Min --
Typ 300
Max 400 10
Unit ms
Tcdl Tdoc Tsup Trd Tcdh
----
10 10 15
14 20 20 50 --
ms ns ms ms ms
8
--
CAS input signal length (2130 ,2750 Hz @ -20dBm ) Data detect delay time Data release time
Tcasi Td Tr
80 42 26
ms ms ms
30
EM78911 8-bit micro-controller micro-
XI. Timing Diagrams
LQV
Fig.20 AC timing
31
EM78911 8-bit micro-controller micro-
FIRST RING 2 SECONDS TIP/RING /RING TIME /RD Trd /CD
0.5 SEC
0.5 SEC
SECOND RING 2 SECONDS
Tpd Tcdh Tcdl Tdoc
DATA Tosc OSC /358E Tsup 3.579 MHz
DATA
Fig.21 FSK Timing Diagram
plug in on hook events normal in use
CAS Tcasi
Td CAS Tr
PCW Power on/off
power off
power on
Fig.22 Call Waiting Timing Diagram
32
EM78911 8-bit micro-controller micro-
XII. Application Circuit
1
2
3
4
D
D
VDD
10K 1000P TIP RING 10K AVDD VDD 100 0.1u
VSS
TIP
C FUSE
1000P
DET1
0.1u EST ST/GT 300K C
VDD
0.1u 250V 270K
RINGTIME 0.22u
VSS RING
470K AVSS PLLC VSS XIN TEST 33K 0.1u 250V CWTIP MATCHING NETWORK 10K 103 GAIN 10K B COMMON SEGMENT 100K 0.1u 100K B 470K RESET 27 XOUT 32768 27 0.01u
AVSS
DET1
VSS VDD
TO PHONE
LCD DISPLAY
NPN
A
Title Size A Date: File: 1 2 3 18-May-1999 C:\ADVSCH\78911_1.SCH Sheet of Drawn By: 4 Number Revision
A
Fig23. APPLICATION CIRCUIT
33
EM78911 8-bit micro-controller micro-
: EM78R911 SPEC. IV.Pin Configuration
SEG40 SEG41 SEG42 SEG43 TEST P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 VDD NC GND IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 INSEND IRSEL PH1OUT X2OUT /HOLD /POVD ENTCC MCLK 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
NC AVSS DTMF PLLC RINGTIME RDET1 RING TIP CWRING GAIN XIN XOUT AVDD SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 VDD NC GND SE10 SE11 SE12 SE13 SE14 SE15 SE16 VDD2 SE17 SE18 SE19 EPS CA-1 CA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 GND NC VDD CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC SEG39 SEG38 SEG37 SEG36 RESET P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 GND NC VDD COM7 COM6 COM5 COM4 COM3 VSS2 COM2 COM1 COM0 SEG35 SEG34 SEG33 SEG32 SEG31 NC
Fig1. Pin Assignment
34
EM78911 8-bit micro-controller micro-
VI.Pin Descriptions
PIN VDD1,VDD2 AVDD VSS1,VSS2 AVSS Xtin Xtout COM0..COM7 COM8..COM15 SEG0...SEG43 SEG44..SEG51 SEG52..SEG59 PLLC TIP RING CWTIP GAIN RDET1 /RING TIME INT0 INT1 INT2 INT3 P5.4 ~P7.7 P6.0 ~P6.7 P7.0 ~P7.7 I/O POWER POWER I O O O (PORT6) O O (PORT8) O (PORT9) I I I I I I I DESCRIPTION digital power analog power digital ground analog ground Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Common driver pins of LCD drivers Segment driver pins of LCD drivers PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG. Phase loop lock capacitor Should be connected with TIP side of twisted pair lines Should be connected with TIP side of twisted pair lines Should be connected with TIP side of twisted pair lines for CW. OP output pin for gain adjustment. Detect the energy on the twisted pair lines . These two pins coupled to the twisted pair lines through an attenuating network. Determine if the incoming ring is valid.An RC network may be connected to the pin. PORT7(0)~PORT7(3) signal can be interrupt signals.
P8.0 ~P8.7 P9.0 ~P9.7
TEST DTMF RESET X2OUT CA-1
PORT7(0) PORT7(1) Int2 and int3 has the same interrupt flag. PORT7(2) PORT7(3) PORT7(4:7) IO port PORT5 PORT 5 can be INPUT or OUTPUT port each bit. Shared with LCD segment signals PORT6 PORT 6 can be INPUT or OUTPUT port each bit. Shared with LCD common signals PORT7 PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Key scan function. PORT8 PORT 8 can be INPUT or OUTPUT port each bit. And shared with Segment signal. PORT9 PORT 9 can be INPUT or OUTPUT port each bit. And can be set to wake up watch dog timer. And shared with Segment signal. I Test pin into test mode , normal low O DTMF tone output I O O
System clock output. CA-1 is used as address line to select low-order data (8 bits, through CD0~CD7) or high-order data (5 bits, through CD0~CD4) ERS=1 => CA-1 NO USE ERS=0 => CA-1=0 HIGH ORDER DATA
35
EM78911 8-bit micro-controller micro-
ERS
I
ENTCC
I
CA0~CA13 CD0~CD12 IRSEL INSEND /HOLD /POVD MCLK RC4M 4MPD IOD0~IOD7 PH1OUT
O I O O I I I O I O O
CA-1=1 LOW ORDER DATA Input pin used to select the external ROM data bus through bus CD0~D12 or CD0~CD7 only. HIGH/LOW = CD0~CD12 / CD0~CD7. TCC control pin with internal pull-high (560K). TCC works normally when ENTCC is high, and TCC counting is stopped when ENTCC is low. Program code address bus. CA0~CA13 are address output pins for external programming ROM access. Data access in terms of CA0 ~ CA12 addressing. IRSEL is an output pin used to select an external EVEN/ODD ROM. Used to indicate the instruction completion and ready for next instruction. Microcontroller hold request. Input pin used to enable Power on voltage detector. Power on voltage detector is enabled if /POVD is low and is disabled if /POVD is high. Input pin for main clock selection. Internal pull low through a register. RC clock for program down load RC 4M power control pin. This pin pull low internally to enable clock. To pull high externally for disabling clock. I/O data bus. Phase 1 output
IX AC Electrical Characteristic
Tdiea Tdiei Tiew Tdca Tacc Tcds Tcdh Tdca-1 Delay from Phase 3 end to INSEND active Delay from Phase 4 end to INSEND inactive INSEND pulse width Delay from Phase 4 end to CA Bus valid ROM data access time ROM data setup time ROM data hold time Delay time of CA-1 Cl=100pF Cl=100pF 30 C1=100pF 100 20 20 C1=100pF 30 30 30 30 ns ns ns ns ns ns ns ns
Note 1: N= selected prescaler ratio.
36
EM78911 8-bit micro-controller micro-
3 CLK
4
1
2
3
4
1
2
3
Tdiea
Tdiei Tiew
/INSEND Tdca CA13:0
CD12:0 Tacc Tcds EPS=1 CA-1=DISABLE 3 CLK Tdiea Tdiei 4 1 2 3 4 1 2 3 Tcdh
/INSEND Tdca CA-1 Tdca-1
Tiew
CA13:0
CD7:0
Tacc
HIGH ORDER DATA Tcds Tcdh
LOW ORDER DATA
EPS=0 CA-1=0 HIGH ORDER DATA CA-1=1 LOW ORDER DATA
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