View M61110GPNBSP_310770.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M61110FP/GP
Coil-less VIF/SIF
REJ03F0021-0200Z Rev.2.0 Mar.12.2004
Description
M61110FP is a semiconductor integrated circuit consisting of VIF/SIF signal processing for CTVs and VCRs. M61110FP provides low cost and high performance system with the coil-less AFT
Feature
* * * * * * * * * Coil-less AFT PLL FM demodulation for Audio. No external parts and adjustment. (Target S/N=70dB) The PLL-SPLIT system provides good sound sensitivity and reduces buzz. Video output is 2.2Vp-p through EQ AMP Easy to add Buzz cancel Hi speed IF AGC Built-in QIF AGC Improve over modulation characteristics and Vcc ripple rejection Open collector RF AGC output (5-9V available).
Application
TV set, VCR tuners.
Recommended Operating Condition (Ta = 25C, unless otherwise noted)
Supply Voltage Range (Vcc)...............4.75 to 5.25 V Rated Supply Voltage (Vcc)..............................5.0 V
Pin configuration
EQ OUT Vreg.OUT APC FILTER EQ IN Vcc VCO COIL VCO COIL IF AGC FILTER VIDEO OUT QIF OUT GND LIMITER IN
1 2 24 23
EQ F / B IF AGC FILTER RF AGC DELAY VIF IN VIF IN GND AFT OUT RF AGC OUT QIF DET IN NFB AUDIO OUT QIF AGC FILTER
M61110FP/GP
3 4 5 6 7 8 9 10 11 12
22 21 20 19 18 17 16 15 14 13
Rev.2.0, Mar.12.2004, page 1 of 19
M61110FP/GP
Block diagram and peripheral circuit
IF IN
Vcc
RF AGC Delay AF OUT AFT OUT RF AGC OUT
24
23 IF AGC
22
21
20
19
18
17
16
15
14 AF AMP
13
VIF AMP RF AGC QIF AMP
FM DET
EQ AMP AFT REG
APC
VIDEO DET
QIF AGC QIF DET
LIM AMP
VCO 1 2
Vreg. OUT
3
4 +
5
Vcc
6
7
8
9
10
11
12
EQ OUT
+
VIDEO OUT 4.5MHz Trap
4.5MHz B.P.F.
Rev.2.0, Mar.12.2004, page 2 of 19
M61110FP/GP
Absolute maximum ratings (Ta = 25C, unless otherwise noted)
Parameter Supply Voltage Power Consumption Operating Temperature Storage Temperature Symbol Vcc Pd Topr Tstg Ratings 6.0 1190(FP), 728(GP) -20 to +75 -40 to +150 Unit V mW C C Note
Temperature Characteristics
( maximum ratings ) Mounting in standard circuit board
Allowable power consumption Pd ( mW )
1750 1500 1250 1000
728 1190 FP
750
GP
714
500
438
250 0 -20 0 25 50 75 100 125 150
Ambient temperature Ta ( C )
Rev.2.0, Mar.12.2004, page 3 of 19
M61110FP/GP
Electrical Characteristics (Vcc=5V, Ta=25C, unless otherwise noted)
VIF Section
Measurement No. Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Circuit Current Vreg. Output Voltage Video Output Voltage 9 Video Output Voltage 1 Video S/N Video Band Width Symbol Icc Vreg. Vo det9 Vo det Test Test Input Input switches set to Circuit Point Point SG position 1 unless otherwise noted 1 1 1 1 A TP2 TP9 -- -- -- -- SW5 = 2 Limits Min 40 3.2 0.85 1.85 SW1 = 2 SW8 = 2 V8 = Variable 51 5.0 -- 104 55 2.8 2.8 4.5 -- 86 1.0 1.1 2.3 22 4.4 -- 2.2 35 -- -- Typ 50 3.5 1.1 2.2 56 7.0 48 110 62 3.1 3.1 4.9 0.1 89 1.5 1.6 3.1 32 4.8 0.1 2.5 40 2 2 Max Unit 60 3.8 mA V Note
VIF IN SG1
1.35 Vp-p 2.55 Vp-p -- -- 52 -- -- 3.4 3.4 -- 0.5 92 -- -- -- 44 -- 0.5 2.8 -- 5 5 dB MHz dB dB dB V V V V dB MHz MHz MHz
mV
TP1A VIF IN SG1 TP1B VIF IN SG2 TP1A VIF IN SG3 TP1A VIF IN SG4 TP1A VIF IN SG5 -- TP8 -- --
Video S/N 1 BW 1
1 2 3 4 5
Input Sensitivity VIN MIN 1 Maximum VIN MAX 1 Allowable AGC Control GR Range Input IF AGC Voltage V8 1 IF AGC Voltage V23 2 Maximum RF V17H AGC Minimum RF AGC RF AGC Delay Point V17L V17 -- 1 1 1 1 1 1 1 -- 1 1 1 1 1 1 1
VIF IN SG6
TP23 VIF IN SG6 TP17 VIF IN SG6 TP17 VIF IN SG7 TP17 VIF IN SG8 TP1A VIF IN SG9 TP1A VIF IN SG9 -- -- --
6 7 8 9 10 10 10
Capture Range CR-U U Capture Range CR-L L Capture Range CR-T T AFT Sensitivity AFT Minimum Voltage AFT Maximum Voltage V18H V18L
TP18 VIF IN SG10 TP18 VIF IN SG10 TP18 VIF IN SG10 TP18 VIF IN -- TP1A VIF IN SG11 SW8 = 2 V8 = Variable TP1A VIF IN SG12 TP1A VIF IN SG12
/ kHz
V V V dB % deg
AFT defeat AFT def Inter Modulation IM Differential Gain Differential Phase DG DP
11
Rev.2.0, Mar.12.2004, page 4 of 19
M61110FP/GP
Electrical Characteristics (Vcc=5V, Ta=25C, unless otherwise noted)
SIF Section
Measurement No. Parameter 25 26 27 28 29 30 31 Symbol Test Test Input Circuit Point Point 1 1 1 1 1 1 1 TP10 VIF IN QIF IN TP10 VIF IN QIF IN TP14 SIF IN TP14 SIF IN TP14 SIF IN TP14 SIF IN TP14 SIF IN Input SG SG2 SG13 SG2 SG14 SG16 SG16 SG17 SG18 SG19 switches set to position 1 unless Min otherwise noted 94 94 400 -- -- 61 63 Limits Typ 100 100 600 0.2 42 68 70 Max 106 106 880 0.9 55 -- -- Unit dB dB mVrms % dB dB dB 12 13 14 Note
QIF det OUT1 QIF1 QIF det OUT2 QIF2 AF Output AFOutput Distortion VoAF THD AF
Limiting LIM Sensitivity AM Rejection AMR AF S/N AF S/N
Rev.2.0, Mar.12.2004, page 5 of 19
M61110FP/GP
Measurement Circuit Diagram
VIF IN
51 Vcc 150K 22K TP23 33K 1K 1:1 TP18 150K 39K Vcc 51
SIF IN
0.1u TP17 20K 7.5K
TP14 0.1u
24
23 IF AGC
22
21
20
19
18
17
16
15
14
13
VIF AMP RF AGC QIF AMP
AF AMP
FM DET
EQ AMP AFT REG
APC
VIDEO DET
QIF AGC QIF DET
LIM AMP
VCO 1 2 +
33u
3
0.47u
4
5 +
33u
6
7
8 TP8 9
0.22u
10
11
12
+
SW1 1 2 1K 51 1000p TP2 15u
TP10 VCO COIL 1 2 V8 51
L TP1A P F
TP1B
330 LIM IN TP9
4.5MHz Trap SW5 1 Vcc 2 A
* All the capacitors are 0.01uF, unless otherwise noted. * The Measurement Circuit 1 is Mitsubishi standard evaluation fixture.
Rev.2.0, Mar.12.2004, page 6 of 19
M61110FP/GP Input Signal
SG 1 2 3 4 5 6 7 8 9 10 11 50 Termination f0 = 45.75MHz AM 20kHz 77.8% 90dB f0 = 45.75MHz 90dB CW f1 = 45.75MHz 90dB CW f2 = Frequency Variable 70dB
}
CW Mixed Signal
f0 = 45.75MHz AM 20kHz 77.8% Level Variable f0 = 45.75MHz AM 20kHz 14.0% Level Variable f0 = 45.75MHz 80dB CW f0 = 45.75MHz 110dB CW f0 = 45.75MHz Level Variable CW f0 = Frequency Variable AM 20kHz 77.8% 90dB f0 = Frequency Variable 90dB CW f1 = 45.75MHz 90dB CW f2 = 42.17MHz 80dB CW Mixed Signal f3 = 41.25MHz 80dB CW
}
12 13 14 15 16 17 18 19 20
f0 = 45.75MHz 87.5% TV modulation 10stair-steps waveform Sync Tip Level 90dB f1 = 41.25MHz 95dB CW f1 = 41.25MHz 75dB CW f1 = 45.75MHz 90dB CW f2 = 41.25MHz 70dB CW
}
Mixed Signal
f0 = 4.5MHz 90dB FM 400Hz +/-25kHzdev f0 = 4.5MHz Level Variable FM 400Hz +/-25kHzdev f0 = 4.5MHz 90dB AM 400Hz 30% f0 = 4.5MHz 90dB CW f0 = 4.5MHz Level Variable CW
Rev.2.0, Mar.12.2004, page 7 of 19
M61110FP/GP
Notes
1. Video S/N Input SG2 to VIF IN and measure the video out (Pin 1) noise in r.m.s. at TP1B through a 5MHz (-3dB) L.P.F.
S/N=20 log
( ------------ )
NOISE
0.7 x Vo det
[dB]
2. Video Band Width : BW 1. Measure the 1MHz component level of Video output TP1A with a spectrum analyzer when SG3 (f2 = 44.75MHz) is input to VIF IN. At that time, measure the voltage at TP8 with SW8, set to position 2, and then fix V8 at that voltage. 2. Reduce f2 and measure the value of (f2-f1) when the (f2-f1) component level reaches -3dB from the 1MHz component level as shown below.
TP1A
-3dB
( f2 - f1 ) 1MHz BW
3. Input Sensitivity : VIN MIN Input SG4 (Vi = 90dB) to VIF IN , and then gradually reduce Vi and measure the input level when the 20kHz component of Video output TP1A reaches -3dB from Vo det level. 4. Maximum Allowable Input : VIN MAX 1. Input SG5 (Vi = 90dB) to VIF IN , and measure the level of the 20kHz component of Video output. 2. Gradually increase the Vi of SG and measure the input level when the output reaches -3dB. 5. AGC Control Range: GR
GR = VIN MAX - VIN MIN [dB]
Rev.2.0, Mar.12.2004, page 8 of 19
M61110FP/GP 6. RF AGC Operating Voltage: V17 Input SG8 to VIF IN and gradually reduce Vi and then measure the input level when RF AGC output TP17 reaches 1/2Vcc, as shown below.
TP17 Voltage V17H
1/2VCC
V17L Vi Vi (dBu)
7. Capture range: CR-U 1. Increase the frequency of SG9 until the VCO is out of locked-oscillation. 2. And decrease the frequency of SG9 and measure the frequency fU when the VCO is locked.
CR-U = fU - 45.75 [MHz]
8. Capture range: CR-L 1. Decrease the frequency of SG9 until the VCO is out of locked-oscillation. 2. And increase the frequency of SG9 and measure the frequency fL when the VCO is locked.
CR-L = 45.75 - fL [MHz]
9. Capture range: CR-T
CR-T = CR-U + CR-L [MHz]
10. AFT sensitivity : , Maximum AFT voltage : V18H , Minimum AFT voltage : V18L 1. Input SG10 to VIF IN, and set the frequency of SG10 so that the voltage of AFT output TP18 is 3[V] . This frequency is named f(3). 2. Set the frequency of SG10 so that the AFT output voltage is 2[V]. This frequency is named f(2). 3. IN the graph shown below, maximum and minimum DC voltage are V 18H and V18L , respectively.
TP18 Voltage 3V
=
1000 f(2) - f(3)
[mV] [kHz]
[mV/kHz]
2V
V18H
V18L f(3) f(2) f(MHz)
Rev.2.0, Mar.12.2004, page 9 of 19
M61110FP/GP 11. Inter modulation: IM 1. Input SG11 to VIF IN, and measure video output TP9 with an oscilloscope. 2. Adjust AGC filter voltage V8 so that the minimum DC level of the output waveform is 1.5V. 3. At that time, measure TP1A with a spectrum analyzer . The inter modulation is defined as a difference between 0.92MHz and 3.58 MHz frequency components. 12. Limiting Sensitivity: LIM 1. Input SG17 to LIM IN, and measure the 400Hz component level of AF output TP14. 2. Input SG20 to LIM IN, and measure the noise level of AF output TP14 . 3. The input limiting sensitivity is defined as the input level when the difference between each 400Hz components of audio output (TP14) is 30dB, as shown below.
Audio Output (mVrms) 30dB Audio output while SG17 is input.
Audio output while SG20 is input.
LIM Input level (dB)
13. AM Rejection: AMR 1. Input SG18 to LIM IN, and measure the output level of Audio output (TP14). This level is named VAM. 2. AMR is;
AMR = 20log
( -------------- ) VAM (mVrms)
VoAF (mVrms)
[dB]
14. AF S/N: AF S/N 1. Input SG19 to LIM IN, and measure the output noise level of Audio output (TP14). This level is named VN. 2. S/N is;
S/N = 20log
( -------------- ) VN (mVrms)
VoAF (mVrms)
[dB]
Rev.2.0, Mar.12.2004, page 10 of 19
M61110FP/GP
Pin peripheral circuit explanation
*Pin 1 (EQ OUT)
EQ output amplitude is positive 2.2Vp-p in case of 87.5% video modulation.
1
internal current : 1.2mA
1.1Vo-p *Pin 2 (Vreg.OUT)
2
+
It is a regulated 3.5V output which has current drive capability of approximately 1mA. In the locked state, the cut-off frequency of the filter is adjusted effectively by an external resistor so that it will be in the range of around 30 to 200kHz. In case the cut-off frequency is lower, the pull-in speed becomes slow. On the other hand, a higher cut-off frequency widen the pull-in range and band width, which results in a degradation in the S/N ratio. So, in the actual TV system design, the appropriate constant should be chosen for getting desirable performance considering above conditions.
*Pin3 (APC FILTER)
Bias 12K
3
[V3] 2.8Vo-p fo
[IF input frequency]
Pin 3 output
FM mod.frequency 100KHz
Rev.2.0, Mar.12.2004, page 11 of 19
M61110FP/GP
*PIN 4 (EQ IN)
The input is open base. If DC information is not input to pin9, IF AGC dose not work normally. Please pay attention.
4
*PIN 5 (Vcc)
Vcc
It is Vcc pin. (only one Vcc pin in this IC)
5
*PIN 6, PIN 7 (VCO COIL)
Connecting a tuning coil and capacitor to these pins enables an oscillation. The oscillation frequency is tuned in 'fo' .In the actual adjustment, the coil is tuned so that the AFT voltage reaches to Vcc/2 with 'fo' as an input. The printed pattern around these pins should be designed carefully to prevent an pull-in error of VCO, caused by the leakage interference from the large signal level oscillator to adjacent pins. The interconnection should be designed as short as possible. In case the printed pattern has the interference problem, a capacitor of about 1pF is connected between pin6 or pin7 and GND so as to cancel the interference and keep enough pull-in range even in a low input level.
800
800 6 7
Rev.2.0, Mar.12.2004, page 12 of 19
M61110FP/GP
*PIN 8, PIN 23 (IF AGC FILTER)
2-pins filter characteristics are available by utilizing the dynamic AGC circuit . And AGC speed can be changed, if pin23 on the external resistor is variable.
8 1K 10K
[V8] [V23]
23
weak electric field 0 [IF input]
strong electric field
*PIN 9 (VIDEO OUT)
Video output amplitude is positive 1.1Vp-p in case of 87.5% video modulation.
9
internal current: 4mA
*PIN 10 (QIF OUT)
In the split carrier system, the carrier signal to SIF is provided from pin10 through the emitter follower. And please open this pin, when it is used in the inter carrier system.
10
internal current: 1mA
*PIN 11 (GND)
11
This is GND of the SIF part .
Rev.2.0, Mar.12.2004, page 13 of 19
M61110FP/GP
*PIN 12 (LIMITER IN)
12 Bias 150 6K
The input impedance is 6.15K.
6K
*PIN 13 (QIF AGC FILTER)
AGC speed can be changed by this pin's external capacity.
13
*PIN 14 (AUDIO OUT)
14
internal current : 0.8mA
The FM detector can respond to SIF signals without an adjustment and external components by adopting the PLL technique. The capacitor between pin14 and pin15, which fixes the de-emphasis characteristics, can be determined considering the combination of an equivalent resistance of the IC and this capacitor itself. Frequency response of audio output is decided with external capacitor value of pin15. And audio output level can be made it small when it connected external capacitor to pin15 and resistance in series.
*PIN 15 (NFB)
15 50K
50K
Rev.2.0, Mar.12.2004, page 14 of 19
M61110FP/GP
*PIN 16 (QIF DET IN)
16 Bias 1.5K
SAW
1.5K
The input impedance is 1.5K.
*PIN 17 (RF AGC OUT)
Vcc (MAX 9V)
Vcc
17
Tuner
[V17] Low
( in open-loop condition )
inflow current : 2 mA (max)
High
[ IF input ]
0
Connecting a non-polarity capacitor of 1uF between pin17 to pin22 improves AGC operating speed. In that case, the capacitors between pin17 and pin22 to ground should be removed. It is possible for Pin17 to connect to Vcc with 9V.
*PIN 18 (AFT OUT)
AFT output is provided by a high impedance source,the detection sensitivity can be set by an external resistor. The muting operation will be on in following two cases; 1) the APC is out of locked 2) the video output becomes small enough in a low input level.
Vcc
The maximum outflow current : 0.2 mA The maximum inflow current : 0.2 mA
18
Tuner
Vcc
[V18]
( in open-loop condition )
Vcc 2 0 [fo]
Rev.2.0, Mar.12.2004, page 15 of 19
M61110FP/GP
*PIN 19 (GND)
19
This is GND other than SIF part.
*PIN 20, PIN 21 (VIF IN)
20 21 Bias 1.2K 1.2K
SAW
It should be designed carefully for impedance matching with the SAW filter.
*PIN 22 (RF AGC DELAY)
Vreg.
22
The applied voltage to the pin22 is for changing RF AGC delay point .
*PIN 24 (EQ F/B)
Both the external coil and capacitor determine the frequency response of EQ output . The series connected resistor is for damping.
500 24
5.3K
Bias
5K 5K
Rev.2.0, Mar.12.2004, page 16 of 19
M61110FP/GP
Application Example 1
2200 P
27
560
51
IF IN
1.2 K
2.2 K
0.01
0.01
1
Vcc
SAW
0.01
0.01 39K
150K
0.01 7.5 K
RF AGC OUT
1K
1K 0.01 33K 22K 0.01
Vcc AFT OUT
Vcc
20K 0.1
AF OUT
0.1
0.01
24
23 IF AGC
22
21
20
19
150K
18
17
16
15
14
AF AMP
13
VIF AMP
RF AGC
QIF AMP
EQ AMP
AFT REG
FM DET
APC
VIDEO DET
QIF AGC LIM AMP
QIF DET VCO
1 +
0.01 33
2
0.47
3
4
5
6
7
8
0.22
9
10
11
12
33
TP2
0.01
100
EQ OUT
1K
+
VCO COIL
1K
15
Vcc 330 4.5 MHz B.P.F. TP9
4.5 MHz Trap
special components
SAW : SAFW45MCC80Z(MURATA) TRAP : TPSRA4M50B00(MURATA) B.P.F. : SFSRA4M50EF00(MURATA) VCO : 292GCS- 5540Z(TOKO)
Rev.2.0, Mar.12.2004, page 17 of 19
M61110FP/GP
Application Example 2
2200 P
27
560
51
IF IN
1.2 K
2.2 K
0.01
0.01
1
Vcc
SAW
0.01
0.01 39K
150K
0.01 7.5 K
RF AGC OUT
1K
1K 0.01 33K 22 K 0.01
Vcc AFT OUT
Vcc
20K 0.1
AF OUT
0.1
0.01
24
23
IF AGC
22
21
20
19
150K
18
17
16
15
14
AF AMP
13
VIF AMP
RF AGC
QIF AMP
EQ AMP
AFT REG
FM DET
APC
VIDEO DET
QIF AGC
LIM AMP
QIF DET VCO
1 +
0.01 33
2
0.47
3
4
5
1p
6
7
8
0.22
9
10
11
12
0.01
1000 p
1K
51
1M
TP2
+
33
EQ OUT
22 56 p VCO COIL 4.5 MHz B.P.F. TP9
Vcc 15 330
4.5 MHz Trap
special components
SAW : SAFW45MCC80Z(MURATA) TRAP : TPSRA4M50B00(MURATA) B.P.F. : SFSRA4M50EF00(MURATA) VCO : 292GCS - 5540Z(TOKO)
Rev.2.0, Mar.12.2004, page 18 of 19
24P2Q-A
JEDEC Code -- e b2
13
MMP
Weight(g) 0.2 Lead Material Cu Alloy
Plastic 24pin 300mil SSOP
M61110FP/GP
EIAJ Package Code SSOP24-P-300-0.80
24
HE
E
L1
L
Rev.2.0, Mar.12.2004, page 19 of 19
Detailed Diagram Of Package Outline
F Recommended Mount Pad Symbol
12
1
A D
G
A2
b
A1
e y
c z Detail G Detail F
Z1
e1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
Dimension in Millimeters Min Nom Max -- -- 2.1 0 0.1 0.2 -- 1.8 -- 0.3 0.35 0.45 0.18 0.2 0.25 10.0 10.1 10.2 5.2 5.3 5.4 -- 0.8 -- 7.5 7.8 8.1 0.4 0.6 0.8 -- 1.25 -- -- -- 0.65 -- -- 0.8 -- -- 0.1 0 -- 8 -- 0.5 -- -- 7.62 -- -- 1.27 --
I2
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0

▲Up To Search▲

Price & Availability of M61110GPNBSP

	To Download M61110GPNBSP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .