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RFD10P03L, RFD10P03LSM, RFP10P03L
Data Sheet July 1999 File Number
3515.2
10A, 30V, 0.200 Ohm, Logic Level, P-Channel Power MOSFET
These products are P-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49205.
Features
* 10A, 30V * rDS(ON) = 0.200 * Temperature Compensating PSPICE(R) Model * PSPICE Thermal Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature
Symbol
D
Ordering Information
PART NUMBER RFD10P03L RFD10P03LSM RFP10P03L PACKAGE TO-251AA TO-252AA TO-220AB BRAND 10P03L 10P03L F10P03L
G
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Packaging
JEDEC TO-251AA JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE DRAIN GATE GATE SOURCE
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
7-3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD10P03L, RFD10P03LSM, RFP10P03L
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specifie RFD10P03L, RFD10P03LSM, RFP10P03L -30 -30 10 10 See Figure 5 Refer to UIS Curve 65 0.43 -55 to 175 300 UNITS V V V A
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current RMS Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL (0.063in (1.6mm) from case for 10s)
W W/oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-5) Qg(TH) CISS COSS CRSS RJC RJA RFD10P03L, RFD10P03LSM RFP10P03L VGS = 0 to -10V VGS = 0 to -5V VGS = 0 to -1V VDD = -24V, ID 10A, RL = 2.4 Ig(REF) = -0.25mA (Figure 14) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 11) VGS = VDS, ID = 250A (Figure 12) VDS = -30V, VGS = 0V VGS = 10V ID = 10A, VGS = -5V (Figures 9, 10) ID = 10A, VGS = -4.5V (Figures 9, 10) VDD = 15V, ID 10A, RL = 1.5, RGS = 5, VGS = -5V (Figure 13) 15 50 35 20 25 13 1.2 1035 340 35 TC = 25oC TC = 150oC MIN -30 -1 TYP MAX -2 -1 -50 100 0.200 0.220 100 80 30 16 1.5 2.30 100 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 1) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient
VDS = -25V, VGS = 0V, f = 1MHz (Figure 15)
Source to Drain Diode Specifications
PARAMETER Source to Drain Forward Voltage Reverse Recovery Time NOTE: 2. Pulse Test: Pulse width 300s, Duty Cycle 2%. SYMBOL VSD trr ISD = -10A ISD = -10A, dISD/dt = -100A/s TEST CONDITIONS MIN TYP MAX -1.5 75 UNITS V ns
7-4
RFD10P03L, RFD10P03LSM, RFP10P03L Typical Performance Curves Unless Otherwise Specified
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 -12 -10 ID, DRAIN CURRENT (A) -8 -6 -4 -2 0 25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
ZJC, NORMALIZED THERMAL IMPEDANCE 2.0 1.0 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
PDM
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC+ TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100 IDM , PEAK CURRENT CAPABILITY (A) TJ = MAX RATED TC = 25oC 100s
-100
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: VGS = -10V VGS = -5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 175 - T C I = I 25 ----------------------- 150
ID , DRAIN CURRENT (A)
-10
1ms
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -1 -1
10ms 100ms DC -100
-10
VDSS MAX = -30V
-10 VDS , DRAIN TO SOURCE VOLTAGE (V)
-5 10-5
10-4
10-3 10-2 10-1 t, PULSE WIDTH (s)
100
101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
7-5
RFD10P03L, RFD10P03LSM, RFP10P03L Typical Performance Curves Unless Otherwise Specified
-50 IAS , AVALANCHE CURRENT (A) STARTING TJ = 25oC -25 PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX TC = 25oC
(Continued)
VGS = -5V
ID, DRAIN CURRENT (A)
-20
-10 STARTING TJ = 150oC
VGS = -10V
-15
VGS = -4V VGS = -3.5V
-10 VGS = -3V -5
If R = 0 tAV = (L) (IAS)/(1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R)/(1.3 RATED BVDSS - VDD) + 1] -1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10
0
0
-1
-2
-3
-4
-5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
-25 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX VDD = -15V
FIGURE 7. SATURATION CHARACTERISTICS
400 -55oC rDS(ON), DRAIN TO SOURCE 25oC 175oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC ON RESISTANCE (m) 300 ID = -20A ID = -10A 200 ID = -5A ID = -2.5A 100
-20
-15
-10
-5
0 0 -1.5 -3.0 -4.5 -6.0 VGS, GATE TO SOURCE VOLTAGE (V)
0 -2
-4
-6
-8
-10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
1.5
NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -10A
1.2 ID =- 250uA
1.1
1.0
1.0
0.5
0.9
0 -80
-40
0
40
80
120
160
200
0.8 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
7-6
RFD10P03L, RFD10P03LSM, RFP10P03L Typical Performance Curves Unless Otherwise Specified
1.2 VGS = VDS, ID = -250A 125 NORMALIZED GATE THRESHOLD VOLTAGE SWITCHING TIME (ns) 1.0 tr 100 td(OFF) 75 tf 50 25 0.4 -80 0 td(ON)
(Continued)
150 VDD = -15V, ID = -10A, RL= 1.50
0.8
0.6
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
0
10 20 30 40 RGS, GATE TO SOURCE RESISTANCE ()
50
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
-30 VDS , DRAIN TO SOURCE VOLTAGE (V) VDD =BVDSS -22.5 VDD = BVDSS -3.75 -5.00 VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
1200 CISS 1000 C, CAPACITANCE (pF) 800 600 COSS 400 200 CRSS 0 0 -5 -10 -15 -20 VDS , DRAIN TO SOURCE VOLTAGE (V) -25 VGS = 0V, f = 0.1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
-15
RL = 3.0 IG(REF) = -0.25mA 0.75 BVDSS 0.50 BVDSS 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS
-2.50
-7.5
0.25 BVDSS
-1.25
VGS = -5V 0 20 IG(REF) IG(ACT) t, TIME ( s) 80 IG(REF) IG(ACT) 0.00
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0
+
VDD VDD
0V VGS
DUT tP IAS 0.01
IAS tP BVDSS VDS
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
7-7
RFD10P03L, RFD10P03LSM, RFP10P03L Test Circuits and Waveforms
(Continued)
tON td(ON) tr RL 0 10%
tOFF td(OFF) tf 10%
DUT VGS RG
VDD
+
VDS VGS 0
90%
90%
10% 50% PULSE WIDTH 90% 50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL 0 VGS= -1V VGS VDD
+
Qg(TH)
VDS
-VGS Qg(-5) VDD Qg(TOT) 0 Ig(REF)
VGS= -5V
DUT IG(REF)
VGS= -10V
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
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RFD10P03L, RFD10P03LSM, RFP10P03L PSpice Electrical Model
.SUBCKT RFD10P03L 2 1 3
CA 12 8 1.29e-9 CB 15 14 9.90e-10 CIN 6 8 1.01e-9 ESG DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -36.49 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.40e-9 LSOURCE 3 7 3.22e-9 LGATE GATE 1 RLGATE MMED 16 6 8 8 MmedMOD MSTRO 16 6 8 8 MstroMOD MWEAK 16 21 8 8 MweakMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 68.25e-3 RGATE 9 20 2.54 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSourceMOD 25.00e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 CIN RGATE 9 EVTEMP
REV 22 Aug 96
LDRAIN + 5 RLDRAIN + 17 18 DRAIN 2 RSLC1 51 ESLC 50 DBODY EBREAK
10
8 6
RSLC2
5 51 DPLCAP EVTHRES + 19 8 6
-
20
18 + 22
-
-
ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))} .MODEL DBODYMOD D (IS=9.15e-13 RS=3.25e-2 IKF=0.05 N=0.97 TRS1=4.11e-5 TRS2=2.03e-6 CJO=1.13e-9 M=0.40 TT=3.72e-8) .MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6) .MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50) .MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54) .MODEL MWEAKMOD PMOS (VTO=-1.43 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=25.4 RS=0.1) .MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7) .MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RSCLMOD RES (TC1=2e-3 TC2=0) .MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6) .MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40) ENDS For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley.
7-9
+
-
-
RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11
LSOURCE 7 RLSOURCE RBREAK 18 RVTEMP 19 SOURCE 3
VBAT +
8 22 RVTHRES
RFD10P03L, RFD10P03LSM, RFP10P03L PSpice Thermal Model
7 JUNCTION
REV 29 Aug 96
RFP10P03L CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.45 RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
RFD10P03L, RFD10P03LSM CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.11 RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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