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INTEGRATED CIRCUITS
DATA SHEET
PCF8801 LCD driver for 140 x 2 segments
Product specification File under Integrated Circuits, IC12 2000 Feb 04
Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
FEATURES * Single-chip LCD controller/driver * Fixed backplane multiplexing at a rate of 1 : 2 * Internal LCD bias generation (0.5VDD) * 140 segment outputs configured to drive seven 40-segment characters * On-chip oscillator with one external resistor * Wide power supply range (2.7 V up to 5.5 V) * Low power consumption * Compatible with most microprocessors/microcontrollers * 1 MHz serial bus interface (280-bit shift register) * Easily cascaded for large LCD applications (two cascade directions possible) * Compatible with chip-on-glass technology * Manufactured by silicon gate CMOS process. GENERAL DESCRIPTION The PCF8801 is a peripheral device which interfaces a multiplexed Liquid Crystal Display (LCD) having two backplanes and up to 140 segments. It generates drive signals at a multiplex rate of 1 : 2 allowing seven 40-segment (5 x 8) characters to be driven. ORDERING INFORMATION TYPE NUMBER PCF8801U PACKAGE NAME - chip with bumps in tray DESCRIPTION
PCF8801
The chip can easily be cascaded for larger LCD applications, and the direction of the information flow in the cascade can be selected. The PCF8801 is compatible with most microprocessors/microcontrollers and communicates via a serial bus interface comprising a 280-bit shift register. The outputs are multiplexed by a clock signal generated by the internal oscillator which needs only one external resistor. Cascade applications only require the clock signal to be generated by the first device with the internal oscillators in the other devices disabled. The PCF8801 is designed for chip-on-glass applications. It has a narrow package with raised points (bumps) for easy assembly on to LCD glass.
VERSION -
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
BLOCK DIAGRAM
PCF8801
handbook, full pagewidth
LDPI LDNI DI1 DO1 DIR CLKI CLKO DO2 DI2 LCD BIAS GENERATOR IO1_1 OM1 SH1_1 280-BIT IO140_2 OM140 SH140_2 BI280-BIT ROUTING OUTPUT DIRECTIONAL OUTPUT BLOCK MULTIPLEXER SHIFT REGISTER REGISTER
LDPO LDNO
OUTPUT DRIVERS
S1 S140
/2
OSCI OSCO INT_OSCO INTERNAL OSCILLATOR REXT FRAME GENERATOR
COMMON M
VMID COM1 BACKPLANE DRIVERS COM2
/4
PCF8801
POWER-ON-RESET
RESET
MGL915
T1 T2 T3
VSS1 VSS3 VSS5 VSS2 VSS4
VDD1 VDD3 VDD5 VDD2 VDD4
Fig.1 Block diagram.
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PINNING SYMBOL VDD1 to VDD4 VSS1 to VSS4 VDD5 VSS5 REXT RESET T1 to T3 COM1_1, COM1_2 COM2_1, COM2_2 DIR S1 to S140 DI1, DI2 DO1, DO2 LDP1, LDP2 PAD SIMPLIFIED SYMBOL(1) DESCRIPTION
PCF8801
28, 27, 3, 4 VDD 30, 29, 1, 2 VSS 16 15 10 14 13, 17, 18 31, 173 32, 174 19 33 to 172 24, 7 23, 8 26, 5 DI DO LDPI, LDPO COM1 COM2 VDD VSS
Power supply for output drivers, backplane drivers and LCD bias generator; 4 pads connected internally Ground for output drivers, backplane drivers and LCD bias generator; 4 pads connected internally Power supply for remaining circuitry; connect externally to VDD1 to VDD4 Ground for remaining circuitry; connect externally to VSS1 to VSS4 Enable internal oscillator input; connected via an external resistor Reset input; active HIGH Test pads; must remain unconnected First pair of identical 3-level LCD backplane outputs; each pad is located on opposite sides of the die Second pair of identical 3-level LCD backplane outputs; each pad is located on opposite sides of the die Data direction control input; its voltage level determines the direction in which data is shifted LCD driver outputs Data input; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die Data outputs; both identical; both always valid; for cascade use; each pad is located on opposite sides of the die Data load control input (LDPI) and output (LDPO) on rising edge; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die Data load control input (LDNI) and output (LDNO) on falling edge; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die Data shift clock input (CLKI) and output (CLKO); the status of DIR determines which pad is valid; for cascade use; each pad is located on opposite sides of the die
LDN1, LDN2
25, 6
LDNI, LDNO
CLK1, CLK2
22, 9
CLKI, CLKO
OSC1, OSC2
21, 11
OSCI, OSCO LCD multiplexing clock input (OSCI) and output (OSCO); the status of DIR determines which pad is valid; each pad is located on opposite sides of the die INT_OSCO Internal oscillator outputs; both identical; each pad is located on opposite sides of the die
INT_OSCO1, INT_OSCO2 20, 12 Note
1. These symbols simplify descriptions in this data sheet where several pads have the same function and also indicate the direction of data on pads which can be selected to be either an input or an output.
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
FUNCTIONAL DESCRIPTION Refer to block diagram Fig.1. The PCF8801 comprises a bi-directional 280-bit input shift register, 280-bit output register, output multiplexer providing 140-segment outputs via a routing block and output drivers, two 3-level backplane outputs, internal oscillator and internal power-on reset circuit. To reduce the length of routing required between cascaded chips in multiple chip-on-glass applications, all inputs/outputs for control lines, clock signals and data are provided at both sides of the narrow package. Shift register The 280-bit bi-directional shift register shifts data on the rising edge of clock signal CLKI. The shift register output bits are called SH1_1, SH1_2 to SH140_1, SH140_2. The direction in which data is shifted and the pads that are valid for inputs DI, CLKI and output CLKO, is determined by the voltage level on pad DIR. The voltage on pad DIR must be tied to either VDD or VSS and must not be switched when the PCF8801 is operating. The relationship between the status of pad DIR and the other pads connected to the shift register is shown in Table 1. Table 1 280-bit bi-directional shift register pads VALID PAD SHIFT DIRECTION DIR = 1 Data input DI(1) DI1 DO1 and DO2 CLK1 CLK2 SH140_2 SH1_1 DI2 DO1 and DO2 CLK2 CLK1 SH1_1 SH140_2 Data output DO(2) Clock input CLKI Clock output Last bit Notes 1. The invalid DI pad must be connected to either VDD or VSS. 2. Pads DO and CLKO are used when PCF8801 devices are connected in cascade. 3. The last bit is loaded into a flip-flop whose output is connected to pad DO. The value of the last bit appears at pad DO delayed by a 12 CLKI period. CLKO(2) First bit shifted shifted(3) DIR = 0 Output register
PCF8801
The 280-data bits (SH1_1, SH1_2 to SH140_1, SH140_2) from the output of the shift register are transferred to the input of the 280 bit output register. Data is transferred when either pad LDPI goes HIGH or when pad LDNI goes LOW. The output register bits are called IO1_1, IO1_2 to IO140_1, IO140_2. The pads that are valid for inputs LDPI, LDNI, OSCI, and outputs LDPO, LDNO, OSCO are determined by the voltage level on pad DIR. During a positive pulse on pad LDPI, pad LDNI must stay HIGH, or during a negative pulse on pad LDNI, pad LDPI must stay LOW. The voltage on pad DIR must be tied to either VDD or VSS and must not be switched when the PCF8801 is operating. The relationship between the status of pad DIR and the other pads connected to the output register is shown in Table 2. Table 2 280-bit output register pads VALID PAD SHIFT DIRECTION DIR = 1 Data load input LDPI Data load output LDPO Data load input LDNI Data load output LDNO Multiplexing clock input OSCI Multiplexing clock output OSCO LDP1 LDP2 LDN1 LDN2 OSC1 OSC2 DIR = 0 LDP2 LDP1 LDN2 LDN1 OSC2 OSC1
Output multiplexer, frame generator and backplane drivers The 280 data bits (IO1_1, IO1_2 to IO140_1, IO140_2) from the output register are transferred to the input of the output multiplexer which multiplexes the data at the rate of 1 : 2. The 140 output bits from the output multiplexer are called OM1 to OM140. The frame generator outputs two control signals derived from the LCD multiplex clock (OSCI) called COMMON (12 fOSC) and M (14 fOSC) which control the output multiplexer and the backplane drivers. The operation of the output multiplexer is defined in Table 3.
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
Table 3 Output multiplexer truth table n = 1 to 140; X = don't care. CONTROL INPUT COMMON 0 0 1 1 0 0 1 1 M 0 0 0 0 1 1 1 1 DATA INPUT IOn_1 0 1 X X 0 1 X X IOn_2 X X 0 1 X X 0 1 DATA OUTPUT OMn 0 1 0 1 1 0 1 0 Routing block and output drivers
PCF8801
The layout of the LCD interconnection requires each of the 140 outputs (OM1 to OM140) from the output multiplexer to be mapped to the corresponding pixel in each LCD character by the routing block. The outputs of the routing block are fed to output drivers whose outputs are pads S1 to S140. Table 4 shows which pixel is driven by which data bit output by the shift register for the first LCD character. There are 7 characters in total, each character has 40 data points, so routing is performed on a point-by-point basis. A pixel has 2 segments which are activated by backplane drive signals COM1 and COM2 respectively. If DIR = 0, the first data bit of the data stream to be loaded into the shift register is routed to the first pixel. Data bit SH1_1 is routed to pixel 1, activated by COM1, and data bit SH1_2 is routed to pixel 1, activated by COM2.
The backplane drivers generate two output signals called COM1 and COM2 which connect directly to LCD backplane 1 and to backplane 2 respectively. These signals have 3 voltage levels called VDD, VMID and VSS, where VSS = 0 V and VMID = 12VDD. VMID is the LCD bias voltage generated by the LCD bias generator. Figure 2 is a timing diagram for the output multiplexer, frame generator and backplane drivers.
handbook, full pagewidth
RESET
OSC
COMMON
M
COM1
COM2
OMn (n = 1 to 140)
IOn_1 IOn_2 IOn_1 IOn_2 IOn_1 IOn_2 IOn_1 IOn_2 IOn_1 t
MGL916
Fig.2 Timing diagram for output multiplexer, frame generator and backplane drivers.
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
Table 4 Routing of data to LCD pixels (First 20 bits, DIR = 0). SHIFT REGISTER DATA OUTPUT SH1_1 SH1_2 SH2_1 SH2_2 SH3_1 SH3_2 SH4_1 SH4_2 SH5_1 SH5_2 SH6_1 SH6_2 SH7_1 SH7_2 SH8_1 SH8_2 SH9_1 SH9_2 SH10_1 SH10_2 SH11_1 SH11_2 8 10 11 2 4 6 9 1 3 5 LCD PIXEL 7
PCF8801
SHIFT REGISTER DATA OUTPUT SH12_1 SH12_2 SH13_1 SH13_2 SH14_1 SH14_2 SH15_1 SH15_2 SH16_1 SH16_2 SH17_1 SH17_2 SH18_1 SH18_2 SH19_1 SH19_2 SH20_1 SH20_2
LCD PIXEL 12 13 14 17 19 15 16 18 20
The PCF8801 supports a 5 x 8 LCD character structure as shown in Fig.3. Because the bottom line of pixels are not often used in most applications, their data could be used instead to control LCD icons.
handbook, full pagewidth
top of LCD 1 1 3 3 5 5 7 7 2 2 4 4 6 6 9 9 12 12 8 8 10 10 11 11 19 19 17 17 14 14 13 13 20 20 18 18 16 16 15 15 7 1 3
top of LCD
2 4
12 8
19 17
6 6
10 10
14 14
16 16
9
11
13
15
pixel locations
pixels used to display digit 2
MGL917
Fig.3 LCD character pixel locations (looking from front).
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
Internal oscillator The internal oscillator generates two identical LCD multiplexing clock signals (INT_OSCO) having a minimum frequency of 240 Hz at pads INT_OSCO1 and INT_OSCO2. The internal oscillator is enabled by connecting an external resistor between pad REXT and VDD, and disabled (INT_OSCO = 0) by connecting pad REXT to VSS. An external resistor value of 330 k will typically generate a frequency of 500 Hz. For cascade applications, the first chip in the cascade should have pad INT_OSCO connected to pad OSCI. Each OSCI pad of all subsequent chips should be connected to the OSCO pad of the previous chip (see Fig.4). The signal applied to the OSCI pad must always be a clock signal; applying a DC signal could damage the LCD. Power-on reset and external reset At power-on, the PCF8801 resets to the following conditions: * The shift register and the output register sets all bits to 0 * The frame generator outputs (COMMON and M) are 0 * The multiplexed outputs (S1 to S140) to the LCD pixels are 0 * The backplane driver outputs (COM1 and COM2) are 0 until the first falling edge of OSCI (see Fig.2).
PCF8801
A positive pulse on pad RESET (active HIGH) has the same effect as the power-on reset. A HIGH-level on pad RESET disables all clock inputs, the bias generator, and the internal oscillator (INT_OSCO = 0). If the RESET input is not used, it is advisable to connect its pad directly to the adjacent pad VSS5. However, if the RESET input is to be used in a chip-on-glass application, it is strongly advised that the RESET input is connected in series with an on-glass resistance to reduce its sensitivity to ESD/EMC disturbances. The minimum value of resistance recommended by the ITO is 8 k. Cascading To reduce the length of routing required between cascaded chips on-glass, all inputs/outputs for control lines, clock signals and data are provided at both sides of the narrow package. An example of cascading is shown in Fig.4.
handbook, full pagewidth
VSS DIR
VSS DIR
DATA IN CLOCK LOAD VDD
DI CLKI LDPI LDNI OSCI
DO CLKO LDPO LDNO OSCO VDD
DI CLKI LDPI LDNI OSCI
DO CLKO LDPO LDNO OSCO
INT_OSCO VDD Rext 330 k REXT VSS
INT_OSCO REXT
PCF8801
RESET VSS chip 1
PCF8801
RESET VSS chip 2
MGL918
Fig.4 Example of cascading.
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); stresses greater than the values shown may cause permanent damage to the device; parameters are valid over the ambient temperature range; all voltages are with respect to VSS. SYMBOL VDD VI VO II IO IDD ISS Ptot P/out Tamb Tstg HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). DC CHARACTERISTICS VDD = 2.7 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDD Iq IDD3 supply voltage quiescent supply current normal mode supply current RESET = 1; note 1 CLKI = 0; OSCI = INT_OSCO; note 1 2.7 - - 3 or 5 2.5 32 5.5 10 100 V A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT supply voltage input voltage output voltage DC input current DC output current VDD current VSS current total power dissipation power dissipation per output ambient temperature storage temperature PARAMETER MIN. -0.5 VSS - 0.5 VSS - 0.5 -10 -10 -50 -50 - - -40 -65 MAX. +6.5 VDD + 0.5 VDD + 0.5 +10 +10 +50 +50 500 10 +85 +150 V V V mA mA mA mA mW mW C C UNIT
Logic VIL VIH IOL IOH ILI VPOR Ci Co LOW-level input voltage HIGH-level input voltage LOW-level output current input leakage current Power-on reset voltage input capacitance output capacitance note 2 VSS 0.7VDD VOL = 0.4 V; VDD = 5 V 1 VI = VDD or VSS VDD < VPOR -1 0.8 - - 0.33VDD 0.37VDD 3 -3 0 1.2 - - 0.2VDD VDD - -1 +1 1.6 15 15 V V mA mA A V pF pF
HIGH-level output current VOH = 4.6 V; VDD = 5 V -
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
SYMBOL Outputs to LCD VCOM(tol)
PARAMETER
CONDITIONS
MIN. -135
TYP.
MAX.
UNIT
output voltage tolerance on pad COM1 and pad COM2 output resistance on pad COM1 and pad COM2 output resistance on pads S0 to S140 VDD = 5 V; note 3
-10 to +10 +135
mV
Ro(COM)
-
5
30
k
Ro(S) Notes
-
7
30
k
1. Outputs to LCD are unloaded (open-circuit); inputs are at VSS or VDD; Rext = 330 k. 2. All Schmitt trigger inputs. 3. Measured one at a time; load current 30 A. AC CHARACTERISTICS VDD = 2.7 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified; all timing parameter values are valid within VDD and Tamb range, and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. The serial interface timing parameters are defined in Fig.5. SYMBOL Rext fosc PARAMETER external resistor oscillator frequency at pad INT_OSCO and pad OSCI HIGH time on pad OSCI LOW time on pad OSCI data shift clock frequency on pad CLKI HIGH time on pads CLKI, LDPI and LDNI LOW time on pads CLKI, LDPI and LDNI set-up time DI to CLKI data input hold time separation time between active edges of CLKI, LDPI and LDNI DI stable after CLKI rise note 1 CONDITIONS MIN. 264 240 TYP. 330 500 MAX. 396 1000 UNIT k Hz
tH(OSC) tL(OSC) fclk(CLK) tH(CLK)(LD) tL(CLK)(LD) tsu(DI-CLK) th(D) tsep
400 400 - 400 400 50 500 800
- - - - - - - -
- - 1000 - - - - -
ns ns kHz ns ns ns ns ns
Note 1. Frequency accuracy is valid within VDD, Tamb and Rext. Typical output duty cycle is 50 : 50.
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
handbook, full pagewidth
tsu(DI-CLK) th(D)
DI
CLK tH(CLK)(LD) LDN tL(CLK)(LD)
LDP tsep tsep 1 fclk(CLK) tsep tsep
MGL919
Fig.5 Serial interface timing.
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
BONDING PAD INFORMATION The PCF8801 is manufactured using n-well CMOS technology. S1 Table 5 Bonding pad locations All x/y coordinates represent the position of the centre of each pad (in m) with respect to the centre (x/y = 0) of the chip (see Fig.6). COORDINATES SYMBOL VSS3 VSS4 VDD3 VDD4 LDP2 LDN2 DI2 DO2 CLK2 REXT OSC2 INT_OSCO2 T1 RESET VSS5 VDD5 T2 T3 DIR INT_OSCO1 OSC1 CLK1 DO1 DI1 LDN1 LDP1 VDD2 VDD1 VSS2 VSS1 COM1_1 COM2_1 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -5644.4 -5644.4 -5644.4 -5644.4 -5644.4 -5644.4 -5644.4 -5644.4 -5644.4 -5238.3 -5138.3 -5038.3 -4913.3 -134.6 -47.1 53.4 4791.2 4916.2 5041.2 5141.2 5241.2 5644.4 5644.4 5644.4 5644.4 5644.4 5644.4 5644.4 5644.4 5644.4 5401.7 5326.7 382.4 307.4 232.4 157.4 82.4 -15.0 -115.0 -215.0 -315.0 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -314.9 -214.9 -114.9 -14.9 83.4 158.4 233.4 308.4 383.4 440.0 440.0 y S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 SYMBOL PAD x 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 5251.7 5176.7 5101.7 5026.7 4951.7 4876.7 4801.7 4726.7 4651.7 4576.7 4501.7 4426.7 4351.7 4276.7 4201.7 4126.7 4051.7 3976.7 3901.7 3826.7 3751.7 3676.7 3601.7 3526.7 3451.7 3376.7 3301.7 3226.7 3151.7 3076.7 3001.7 2926.7 2851.7 2776.7 2701.7 2626.7 2551.7 2476.7 2401.7
PCF8801
COORDINATES y 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
COORDINATES SYMBOL S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 PAD x 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 2326.7 2251.7 2176.7 2101.7 2026.7 1951.7 1876.7 1801.7 1726.7 1651.7 1576.7 1501.7 1426.7 1351.7 1276.7 1201.7 1126.7 1051.7 976.7 901.7 826.7 751.7 676.7 601.7 526.7 451.7 376.7 301.7 226.7 151.7 76.7 -73.3 -148.3 -223.3 -298.3 -373.3 -448.3 -523.3 -598.3 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 y S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 SYMBOL PAD -673.3 -748.3 -823.3 -898.3 -973.3
COORDINATES x 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 y
-1048.3 -1123.3 -1198.3 -1273.3 -1348.3 -1423.3 -1498.3 -1573.3 -1648.3 -1723.3 -1798.3 -1873.3 -1948.3 -2023.3 -2098.3 -2173.3 -2248.3 -2323.3 -2398.3 -2473.3 -2548.3 -2623.3 -2698.3 -2773.3 -2848.3 -2923.3 -2998.3 -3073.3 -3148.3 -3223.3 -3298.3 -3373.3 -3448.3 -3523.3
2000 Feb 04
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Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
COORDINATES SYMBOL S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 COM1_2 COM2_2 Alignment marks TARGET1 TARGET2 Dummy pads Dummy1 Dummy2 Dummy3 Dummy4 Dummy5 Dummy6 Dummy7 Dummy8 Dummy9 Dummy10 2000 Feb 04 - - - - - - - - - - -5644.4 5644.4 -4102.7 -4027.7 -3952.7 -3877.7 -3802.7 -3727.7 -3652.7 -3577.7 458.4 458.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 14 - - -5645.0 5645.0 -440.0 -440.0 PAD x 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 -3598.3 -3673.3 -3748.3 -3823.3 -3898.3 -3973.3 -4048.3 -4123.3 -4198.3 -4273.3 -4348.3 -4423.3 -4498.3 -4573.3 -4648.3 -4723.3 -4798.3 -4873.3 -4948.3 -5023.3 -5098.3 -5173.3 -5248.3 -5323.3 -5398.3 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 440.0 y Dummy11 Dummy12 Dummy13 Dummy14 Dummy15 Dummy16 Dummy17 Dummy18 Dummy19 Dummy20 Dummy21 Dummy22 Dummy23 Dummy24 Dummy25 Dummy26 Dummy27 Dummy28 Dummy29 Dummy30 Dummy31 Dummy32 Dummy33 Dummy34 Dummy35 Dummy36 Dummy37 Dummy38 Dummy39 Dummy40 Dummy41 Dummy42 Dummy43 Dummy44 Dummy45 Dummy46 Dummy47 Dummy48 Dummy49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SYMBOL PAD
COORDINATES x -3502.7 -3427.7 -3352.7 -3277.7 -3202.7 -3127.7 -3052.7 -2977.7 -2902.7 -2827.7 -2752.7 -2677.7 -2602.7 -2527.7 -2452.7 -2377.7 -2302.7 -2227.7 -2152.7 -2077.7 -2002.7 -1927.7 -1852.7 -1777.7 -1702.7 -1627.7 -1552.7 -327.4 140.9 215.9 290.9 1231.0 1306.0 1381.0 1456.0 1531.0 1606.0 1681.0 1756.0 y -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4
Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
COORDINATES SYMBOL Dummy50 Dummy51 Dummy52 Dummy53 Dummy54 Dummy55 Dummy56 Dummy57 Dummy58 Dummy59 Dummy60 Dummy61 Dummy62 Dummy63 Dummy64 Dummy65 Dummy66 Dummy67 Dummy68 Dummy69 Dummy70 Dummy71 PAD x - - - - - - - - - - - - - - - - - - - - - - 1831.0 1906.0 1981.0 2056.0 2131.0 2206.0 2281.0 2356.0 2431.0 2506.0 2581.0 2656.0 2731.0 2806.0 2881.0 2956.0 3031.0 3106.0 3181.0 3256.0 3331.0 3406.0 y -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 Dummy72 Dummy73 Dummy74 Dummy75 Dummy76 Dummy77 Dummy78 Dummy79 Dummy80 Dummy81 Dummy82 Dummy83 Dummy84 Dummy85 Dummy86 Dummy87 Dummy88 - - - - - - - - - - - - - - - - - - - SYMBOL PAD
COORDINATES x 3481.0 3556.0 3631.0 3706.0 3781.0 3856.0 3931.0 4006.0 4081.0 4156.0 4231.0 4306.0 4381.0 4456.0 4531.0 4606.0 4681.0 -5780.0 5780.0 y -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -439.4 -600.0 600.0
Chip corners (unsawn wafer) BOTLEFT TOPRIGHT
2000 Feb 04
15
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pitch y x 0.88 mm
COM2_2 COM1_2 S140
Philips Semiconductors
S1 COM2_1 COM1_1
S71 S70
handbook, full pagewidth
TOPRIGHT
LCD driver for 140 x 2 segments
. . .
. . .
. . .
. . .
1.2
mm
VSS3 VSS4 VDD3 VDD4 LDP2 LDN2 DI2 DO2 CLK2
y x 0 0
VSS1 VSS2 VDD1 VDD2 LDP1 LDN1 DI1 DO1 CLK1
RESET VSS5 VDD5
BOTLEFT
TARGET2 (1)
REXT OSC2 INT_OSCO2 T1
11.56 mm
T2 T3 DIR INT_OSCO1 OSC1
16
PCF8801
TARGET2 (1)
MGL921
Product specification
PCF8801
(1) Pattern recognition mark is metal circle of diameter 100 m.
Fig.6 Bonding pad locations.
Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
PCF8801
handbook, full pagewidth
VDDn(1)
VDD1
VDD5
VDD5 SUBSTRATE
VSS5(3)
VSSn(2)
VSS1
VSS5
VSS5
VSS1(3)
VDD1
VDD5
note 4
note 5
VSS1
VSS5
VDD5
note 6
VSS5
MGL922
(1) (2) (3) (4) (5) (6)
Pads VDD1 to VDD4; internally linked by metal connections. Pads VSS1 to VSS4; internally linked by metal connections. VSS1 and VSS5 are internally linked by the substrate resistance. Pads COM1, COM2, S1 to S140. Pads CLKI, OSCI, LDPI, LDNI, INT_OSCO, CLKO, OSCO, LDPO, LDNO, DO, T2. Pads REXT, DIR, RESET, DI, T1, T3.
Fig.7 Device protection diagram.
2000 Feb 04
17
Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
TRAY INFORMATION
PCF8801
x
handbook, full pagewidth
A
C D
y
B
F
E
MGL928
For the dimensions of x, y and A to F, see Table 7.
Fig.8 Tray details.
Table 6
Bonding pad dimensions min. 75 m 62 x 100 m 50 x 90 x 17.5 (5) m approx. 380 m
Pad pitch
handbook, halfpage
Pad size, aluminium Bump dimensions
PCF8801
Wafer thickness Table 7 DIM. Tray dimensions
DESCRIPTION pocket pitch, in the x direction pocket pitch, in the y direction
VALUE 13.97 mm 3.20 mm
MGL929
A B C D
pocket width, in the x direction 11.66 mm pocket width, in the y direction 1.30 mm tray width, in the x direction tray width, in the y direction no. pockets in the x direction no. pockets in the y direction 50.80 mm 50.80 mm 3 14
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to Fig.6 for the orientation and position of the type name on the die surface.
E F x y
Fig.9 Tray alignment.
2000 Feb 04
18
Philips Semiconductors
Product specification
LCD driver for 140 x 2 segments
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8801
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
2000 Feb 04
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/01/pp20
Date of release: 2000
Feb 04
Document order number:
9397 750 06536

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