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| HM5264165 Series HM5264805 Series HM5264405 Series 1,048,576-word x 16-bit x 4-bank Synchronous Dynamic RAM 2,097,152-word x 8-bit x 4-bank Synchronous Dynamic RAM 4,194,304-word x 4-bit x 4-bank Synchronous Dynamic RAM ADE-203-497(Z) Preliminary Rev. 0.2 Dec. 17, 1996 Description All inputs and outputs are reffered to the rising edge of the clock input. The HM5264165 Series, HM5264805 Series, HM5264405 Series are offered in 4 banks for improved performance. Features * 3.3 V power supply * Clock frequency: 100 MHz/83 MHz/66 MHz * LVTTL interface * Single pulsed RAS * 4 banks can operate simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8/full page * Programmable burst sequence Sequential/interleave * Full page burst length capability Sequential burst Burst stop capability * Programmable CAS latency: 2/3 * 4096 refresh cycles: 64 ms Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM5264165, HM5264805, HM5264405 Series * 2 variations of refresh Auto refresh Self refresh Ordering Information Type No. HM5264165TT-10 HM5264165TT-12 HM5264165TT-15 HM5264805TT-10 HM5264805TT-12 HM5264805TT-15 HM5264405TT-10 HM5264405TT-12 HM5264405TT-15 Frequency 100 MHz 83 MHz 66 MHz 100 MHz 83 MHz 66 MHz 100 MHz 83 MHz 66 MHz Package 400-mill 54-pin plastic TSOP II (TTP-54D) 2 HM5264165, HM5264805, HM5264405 Series Pin Arrangement HM5264165TT Series VCC DQ0 VCC Q DQ1 DQ2 V SS Q DQ3 DQ4 V CC Q DQ5 DQ6 V SSQ DQ7 VCC DQML WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SS Q DQ14 DQ13 V CC Q DQ12 DQ11 V SS Q DQ10 DQ9 V CC Q DQ8 V SS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 3 HM5264165, HM5264805, HM5264405 Series Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ15 Data-input/output CS RAS CAS WE Chip select Row address strobe command Column address strobe command Write enable A0 to A11 A0 to A7 Bank select address A12/A13 DQMU/DQML Input/output mask CLK CKE VCC VSS VCCQ VSS Q NC WE Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection Write enable 4 HM5264165, HM5264805, HM5264405 Series Pin Arrangement HM5264805TT Series VCC DQ0 V CC Q NC DQ1 V SS Q NC DQ2 V CC Q NC DQ3 V SSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ7 V SS Q NC DQ6 VCC Q NC DQ5 V SS Q NC DQ4 V CC Q NC V SS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 5 HM5264165, HM5264805, HM5264405 Series Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ7 CS RAS CAS WE DQM CLK CKE VCC VSS VCCQ VSS Q NC Data-input/output Chip select Row address strobe command Column address strobe command Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A11 A0 to A8 Bank select address A12/A13 6 HM5264165, HM5264805, HM5264405 Series Pin Arrangement HM5264405TT Series VCC NC VCC Q NC DQ0 V SS Q NC NC V CC Q NC DQ1 V SSQ NC V CC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS NC V SS Q NC DQ3 VCC Q NC NC V SS Q NC DQ2 V CC Q NC V SS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 7 HM5264165, HM5264805, HM5264405 Series Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ3 CS RAS CAS WE DQM CLK CKE VCC VSS VCCQ VSS Q NC Data-input/output Chip select Row address strobe command Column address strobe command Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A11 A0 to A9 Bank select address A12/A13 8 HM5264165, HM5264805, HM5264405 Series Block Diagram (HM5264165 Series) A0 to A13 A0 to A7 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Memory array Memory array Sense amplifier & I/O bus Memory array Column decoder Column decoder Column decoder Bank 0 Bank 1 Bank 2 Column decoder Bank 3 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ15 DQMU /DQML CKE RAS CAS CLK WE CS 9 HM5264165, HM5264805, HM5264405 Series Block Diagram (HM5264805 Series) A0 to A13 A0 to A8 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Column decoder Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Memory array Bank 3 Column decoder Bank 0 Bank 1 Bank 2 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ7 DQM CKE RAS CAS CLK WE CS 10 HM5264165, HM5264805, HM5264405 Series Block Diagram (HM5264405 Series) A0 to A13 A0 to A9 A0 to A13 Column address counter Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Column decoder Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Memory array Column decoder Bank 0 Bank 1 Bank 2 Bank 3 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit Input buffer Output buffer Control logic & timing generator DQ0 to DQ3 DQM CKE RAS CAS CLK WE CS 11 HM5264165, HM5264805, HM5264405 Series Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) is determined by A0 to A7, A8 or A9 (A7; HM5264165 Series, A8; HM5264805 Series, A9; HM5264405 Series) level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. A12/A13 (input pin): A12/A13 are bank select signal (BS). The memory array of the HM5264165 Series, HM5264805 Series, the HM5264405 Series is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165 Series contain 4096-row x 256-column x 16-bit. HM5264805 Series contain 4096-row x 512-column x 8-bit. HM5264405 Series contain 4096-row x 1024-column x 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers. Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during reading is 2.) Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0.) DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165 Series, DQ0 to DQ7; HM5264805 Series, DQ0 to DQ3; HM5264405 Series). These pins are the same as those of a conventional DRAM. VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) 12 HM5264165, HM5264805, HM5264405 Series VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Function Ignore command No operation Burst stop in full page Symbol DESL NOP BST CKE n-1 n H H H H H H H H H H x x x x x x x x x x V x CS H L L L L L L L L L L L A0 RAS CAS WE A12/A13 A10 to A11 x H H H H H H L L L L L x H H L L L L H H H L L x H L H H L L H L L H L x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V Column address and read command READ Read with auto-precharge READ A Column address and write command WRIT Write with auto-precharge WRIT A Row address strobe and bank active ACTV Precharge select bank Precharge all bank Refresh Mode register set PRE PALL REF/SELF H MRS H Note: H: VIH. L: V IL. x: VIH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256; HM5264165 Series, 512; HM5264805 Series, 1024; HM5264405 Series)), and is illegal otherwise. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. 13 HM5264165, HM5264805, HM5264405 Series Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (A12/A13). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low amd A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. 14 HM5264165, HM5264805, HM5264405 Series DQM Truth Table (HM5264165 Series) CKE n-1 H H H H Function Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. Symbol ENBU ENBL MASKU MASKL n x x x x DQMU L x H x DQML x L x H The HM5264165 series can mask input/output data by means of DQMU/DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQMU/DQML control section of the HM5264165 Series operating instructions. DQM Truth Table (HM5264805 Series, HM5264405 Series) Function Write enable/output enable Write inhibit/output disable Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. Symbol ENB MASK n-1 H H n x x DQM L H The HM5264805 series, HM5264405 Series can mask input/output data by means of DQM. During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other hand, when DQM is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQM. For details, refer to the DQM control section of the HM5264805 Series, HM5264405 Series operating instructions. 15 HM5264165, HM5264805, HM5264405 Series CKE Truth Table CKE n-1 H L L H H H H Self refresh Self refresh exit (SELFX) L L Power down Power down exit L L Note: H: VIH. L: V IL. x: VIH or VIL. CS H x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE x x x H H H x H x H x Current state Active Any Clock suspend Idle Idle Idle Function Clock suspend mode entry Clock suspend Clock suspend mode exit Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry n L L H H L L L H H H H Address x x x x x x x x x x x Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. 16 HM5264165, HM5264805, HM5264405 Series Self-refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self-refresh exit: When this command is executed during self-refresh mode, the synchronous DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the synchronous DRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state Precharge CS H L L L L L L L L Idle H L L L L L L L L RAS x H H H H L L L L x H H H H L L L L CAS x H H L L H H L L x H H L L H H L L WE x H L H L H L H L x H L H L H L H L Address x x x Command DESL NOP BST Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL ILLEGAL Bank and row active NOP Refresh Mode register set BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE ACTV PRE, PALL REF, SELF MRS 17 HM5264165, HM5264805, HM5264405 Series Current state Row active CS H L L L L L L L L Read H L L L RAS x H H H H L L L L x H H H CAS x H H L L H H L L x H H L WE x H L H L H L H L x H L H Address x x x Command DESL NOP BST Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CAS latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst r ead a nd Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST BA, CA, A10 READ/READ A L L L L L Read with auto-precharge H L L L L L L L L H L L L L x H H H H L L L L L H H L L x H H L L H H L L L H L H L x H L H L H L H L BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE ACTV PRE, PALL REF, SELF MRS 18 HM5264165, HM5264805, HM5264405 Series Current state Write CS H L L L L L L L L Write with auto-precharge H L L L L L L L L Refresh (auto-refresh) H L L L L L L L L RAS x H H H H L L L L x H H H H L L L L x H H H H L L L L CAS x H H L L H H L L x H H L L H H L L x H H L L H H L L WE x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burs t write a nd Prec harge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE ACTV PRE, PALL REF, SELF MRS Notes: 1. H: VIH. L: V IL. x: VIH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 19 HM5264165, HM5264805, HM5264405 Series From [PRECHARGE] To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of t RAS is required.) From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. 20 HM5264165, HM5264805, HM5264405 Series From [READ with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank activ. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the synchronous DRAM automatically enters the IDLE state. 21 HM5264165, HM5264805, HM5264405 Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MODE REGISTER SET MRS IDLE REFRESH *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE CLOCK SUSPEND ACTIVE CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE CKE WRITE WITH AP CKE_ WRITEA SUSPEND WRITEA CKE PRECHARGE READ WITH AP WRITE WITH AP READ READ WITH AP WRITE READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE PRECHARGE READA SUSPEND READ SUSPEND WRITE WITH AP PRECHARGE POWER APPLIED POWER ON PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 22 HM5264165, HM5264805, HM5264405 Series Mode Register Configuration The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9 A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. A13 A12 A11 A10 A9 A8 A7 0 A6 A5 LMODE A4 A3 BT A2 A1 BL A0 OPCODE A6 A5 A4 CAS Latency 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X R R 2 3 R A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Burst Length BT=0 1 2 4 8 R R R F.P. BT=1 1 2 4 8 R R R R A13 A12 A11 A10 0 X X X 0 X X X 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1 Write mode Burst read and burst write R Burst read and SINGLE WRITE F.P. = Full Page (256: HM5264165) (512: HM5264805) R (1024: HM5264405) R is Reserved (inhibit) X: 0 or 1 23 HM5264165, HM5264805, HM5264405 Series Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, 24 HM5264165, HM5264805, HM5264405 Series Operation of HM5264165 Series, HM5264805 Series, HM5264405 Series Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. HM5264165 Series, HM5264805 series, HM5264405 Series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page(256; HM5264165 Series, 512; HM5264805 Series, 1024; HM5264405 Series). The start address for a burst read is specified by the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, 8, or full-page (256; HM5264165 Series, 512; HM5264805 Series, 1024; HM5264405 Series), the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register. CAS Latency CLK t RCD Command ACTV READ Address Row Column Dout CL = 2 CL = 3 out 0 out 1 out 0 out 2 out 1 out 3 out 2 out 3 25 HM5264165, HM5264805, HM5264405 Series Burst Length CLK t RCD Command Address ACTV READ Row Column BL = 1 BL = 2 out 0 out 0 out 1 Dout out 0 out 1 out 2 out 3 BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 0-1 BL = full page BL : Burst Length CAS Latency = 2 Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (A12/A13) at the write command set cycle. CLK t RCD Command Address ACTV WRIT Row Column BL = 1 BL = 2 Din in 0 in 0 in 0 in 1 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 6 in 7 in 7 in 8 in 0-1 BL = 4 in 0 BL = 8 in 0 BL = full page CAS Latency = 2, 3 26 HM5264165, HM5264805, HM5264405 Series 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7; HM5264165 Series, AY0 to AY8; HM5264805 Series, AY0 to AY9; HM5264405 Series) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). CLK t RCD Command ACTV WRIT Address Din Row Column in 0 Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. CAS latency 3 2 Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output CLK CL=2 Command READ ACTV out0 out1 out2 out3 lAPR Dout CL=3 Command READ ACTV out0 out1 out2 out3 lAPR Dout Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 50 MHz (I APR changes depending on the operating frequency.) 27 HM5264165, HM5264805, HM5264405 Series Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after active (ACTV) command. In addition, an interval of l APW is required between the final valid data input and input of next command. Burst Write (Burst Length = 4) CLK Command WRIT ACTV DQ (input) in0 in1 in2 in3 lAPW Single Write CLK Command WRIT ACTV DQ (input) in lAPW 28 HM5264165, HM5264805, HM5264405 Series Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. CAS latency 2 3 BST to valid data 1 2 BST to high impedance 2 3 CAS Latency = 2, Burst Length = full page CLK Command DQ (output) out out out out BST out out l BSH = 2 cycle l BSR = 1 cycle CAS Latency = 3, Burst Length = full page CLK Command BST DQ (output) out out out out out out out l BSR = 2 cycle l BSH = 3 cycle 29 HM5264165, HM5264805, HM5264405 Series Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command, and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page CLK Command DQ (input) in in t DPL I BSW = 0 cycle BST PRE/PALL 30 HM5264165, HM5264805, HM5264405 Series Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) CLK Command Address (A0 to A11) BS(A12/A13) READ ACTV READ Row Column A Column B Dout Bank0 Active out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout CAS Latency = 3 Burst Length = 4 Bank 0 2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. 31 HM5264165, HM5264805, HM5264405 Series READ to READ Command Interval (different bank) CLK Command Address (A0 to A11) BS(A12/A13) ACTV ACTV READ READ Row 0 Row 1 Column A Column B Dout Bank0 Active Bank3 Bank0 Bank3 Active Read Read out A0 out B0 out B1 out B2 out B3 Bank0 Bank3 Dout Dout CAS Latency = 3 Burst Length = 4 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) CLK Command Address (A0 to A11) BS(A12/A13) Din Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV WRIT WRIT Row Column A Column B Column =A Column =B Write Write Burst Write Mode Burst Length = 4 Bank 0 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. 32 HM5264165, HM5264805, HM5264405 Series WRITE to WRITE Command Interval (different bank) CLK Command Address (A0 to A11) BS(A12/A13) Din Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV ACTV WRIT WRIT Row 0 Row 1 Column A Column B Bank3 Bank0 Bank3 Active Write Write Burst Write Mode Burst Length = 4 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. 33 HM5264165, HM5264805, HM5264405 Series READ to WRITE Command Interval (1) CLK Command DQM, CL=2 DQMU /DQML READ WRIT CL=3 Din in B0 High-Z in B1 in B2 in B3 Dout Burst Length = 4 Burst write READ to WRITE Command Interval (2) CLK Command READ WRIT DQM, DQMU/DQML CL=2 2 clock High-Z High-Z Dout CL=3 Din 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. 34 HM5264165, HM5264805, HM5264405 Series Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the write command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) CLK Command WRIT READ DQM, DQMU/DQML Din Dout in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 CAS Latency Column = B Dout WRITE to READ Command Interval (2) CLK Command WRIT READ DQM, DQMU/DQML Din Dout in A0 in A1 out B0 out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 Column = A Write Column = B Read CAS Latency Column = B Dout 35 HM5264165, HM5264805, HM5264405 Series 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4 CLK Command READ PRE/PALL Dout CL=2 out A0 out A1 out A2 out A3 l EP = -1 cycle CAS Latency = 3, Burst Length = 4 CLK Command READ PRE/PALL Dout CL=3 out A0 out A1 out A2 l EP = -2 cycle out A3 36 HM5264165, HM5264805, HM5264405 Series READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL Dout out A0 l HZP =2 High-Z CAS Latency = 3, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL Dout l HZP =3 out A0 High-Z 37 HM5264165, HM5264805, HM5264405 Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. However, if the burst write operation is unfinished, the input data must be masked by means of DQM, DQMU/DQML for assurance of the cycle defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command WRIT PRE/PALL DQM, DQMU/DQML Din tDPL CLK Command DQM, DQMU/DQML Din in A0 in A1 WRIT PRE/PALL tDPL Burst Length = 4 (To write all data) CLK Command DQM, DQMU/DQML WRIT PRE/PALL Din in A0 in A1 in A2 in A3 tDPL 38 HM5264165, HM5264805, HM5264405 Series Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than tRC. 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Same Bank CLK Command Address (A0 to A11) BS (A12/A13) ACTV ACTV ROW ROW t RC Bank 0 Active Bank 0 Active Bank Active to Bank Active for Different Bank CLK ACTV ACTV Command Address (A0 to A11) ROW:0 ROW:1 BS (A12/A13) t RRD Bank 0 Active Bank 3 Active 39 HM5264165, HM5264805, HM5264405 Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA . CLK Command MRS ACTV Address (A0 to A13) CODE BS & ROW t RSA Mode Register Set Bank Active DQM Control (HM5264165 Series) The DQMU and DQML mask the lower and upper bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2. Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0. DQM Control (HM5264805 Series, HM5264405 Series) The DQM mask the lower and upper bytes of the DQ data, respectively. The timing of DQM is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2. Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0. 40 HM5264165, HM5264805, HM5264405 Series Reading CLK DQM, DQMU/DQML DQ (output) High-Z out 0 out 1 out 3 lDOD = 2 Latency Writing CLK DQM, DQMU/DQML DQ (input) , in 0 in 1 in 3 l DID = 0 Latency 41 HM5264165, HM5264805, HM5264405 Series Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". Power-up sequence: During power-up sequence, the DQM and the CKE must be set to High. When 200 s has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. 42 HM5264165, HM5264805, HM5264405 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1 Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC, VCCQ VSS , VSS Q Input high voltage Input low voltage Notes: 1. 2. 3. 4. VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V 1, 2, 3 1, 4 Notes 1 All voltage referred to VSS VIH (max) = VCC + 0.5 V for pulse width 5 ns at VCC. (DQ pins). VIH (max) = 4.6 V for pulse width 5 ns at VCC. (Others). VIL (min) = -1.0 V for pulse width 5 ns at VSS. 43 HM5264165, HM5264805, HM5264405 Series DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264165/HM5264805 -10 Parameter Operating current Standby current (Bank Disable) Symbol Min I CC1 I CC2 -- -- -- -- -12 Max Min 130 3 2 50 -- -- -- -- -15 Max Min 105 3 2 45 -- -- -- -- Max Unit Test conditions 85 3 2 35 mA mA mA mA Burst length = 1 t RC = min CKE = VIL, t CK = min Notes 1, 2, 4 5 CLK = VIL or VIH Fixed 6 CKE = VIH, NOP command t CK = min CKE = VIL, t CK = min DQ = High-Z CKE = VIH, NOP command t CK = min, DQ = High-Z 3 Active standby current I CC3 (Bank active) -- -- 12 55 -- -- 12 50 -- -- 12 40 mA mA 1, 2 1, 2, 9 Burst operating current (CAS Latency = 2) (CAS Latency = 3) Refresh current Self refresh current Input leakage current I CC4 I CC4 I CC5 I CC6 I LI -- -- -- -- -10 -10 2.4 -- 150 200 150 3 10 10 -- 0.4 -- -- -- -- -10 -10 2.4 -- 130 180 125 3 10 10 -- 0.4 -- -- -- -- -10 -10 2.4 -- 100 140 100 3 10 10 -- 0.4 mA mA mA mA A A V V t RC = min, Address = VIL or VIH Fixed VIH VCC - 0.2 VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -2 mA I OL = 2 mA 7 t CK = min, BL = 8 1, 2, 8 Output leakage current I LO Output high voltage Output low voltage VOH VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. Input signal transition is once per CLK eight cycles. 9. Input signal transition is once per CLK four cycles. 44 HM5264165, HM5264805, HM5264405 Series DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264405 -10 Parameter Operating current Standby current (Bank Disable) Symbol Min I CC1 I CC2 -- -- -- -- -12 Max Min 110 3 2 40 -- -- -- -- -15 Max Min 95 3 2 35 -- -- -- -- Max Unit Test conditions 75 3 2 30 mA mA mA mA Burst length = 1 t RC = min CKE = VIL, t CK = min Notes 1, 2, 4 5 CLK = VIL or VIH Fixed 6 CKE = VIH, NOP command t CK = min CKE = VIL, t CK = min DQ = High-Z CKE = VIH, NOP command t CK = min, DQ = High-Z 3 Active standby current I CC3 (Bank active) -- -- 12 45 -- -- 12 40 -- -- 12 35 mA mA 1, 2 1, 2, 9 Burst operating current (CAS Latency = 2) (CAS Latency = 3) Refresh current Self refresh current Input leakage current I CC4 I CC4 I CC5 I CC6 I LI -- -- -- -- -10 -10 2.4 -- 140 190 150 3 10 10 -- 0.4 -- -- -- -- -10 -10 2.4 -- 120 170 125 3 10 10 -- 0.4 -- -- -- -- -10 -10 2.4 -- 95 135 100 3 10 10 -- 0.4 mA mA mA mA A A V V t RC = min, Address = VIL or VIH Fixed VIH VCC - 0.2 VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -2 mA I OL = 2 mA 7 t CK = min, BL = 8 1, 2, 8 Output leakage current I LO Output high voltage Output low voltage VOH VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. 8. Input signal transition is once per eight CLK cycles. 9. Input signal transition is once per four CLK cycles. 45 HM5264165, HM5264805, HM5264405 Series Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V) Parameter Input capacitance (Address) Input capacitance (Signals) Output capacitance (DQ) Symbol CI1 CI2 CO Typ -- -- -- Max 5 5 7 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM, DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264165/HM5264805/HM5264405 -10 Parameter System clock cycle time (CAS Latency = 2) (CAS Latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS Latency = 2) (CAS Latency = 3) Data-out hold time t AC t AC t OH -- -- 3 2 9 8 -- -- -- -- 3 2 13 10 -- -- -- -- 3 2 15 12 -- -- ns ns ns ns 1, 2 1, 2, 3 1, 2 t CK t CK t CKH t CKL 15 10 3 3 -- -- -- -- 18 12 4 4 -- -- -- -- 22.5 15 5 5 -- -- -- -- ns ns ns ns 1 1 1 Symbol Min Max -12 Min Max -15 Min Max Unit Notes CLK to Data-out low impedance t LZ CLK to Data-out high impedance (CAS Latency = 2, 3) Data-in setup time Data in hold time Address setup time Address hold time CKE setup time t HZ t DS t DH t AS t AH t CES -- 2 1 2 1 2 7 -- -- -- -- -- -- 3 1 3 1 3 9 -- -- -- -- -- -- 3 1 3 1 3 11 -- -- -- -- -- ns ns ns ns ns ns 1, 4 1 1 1 1 1, 5 46 HM5264165, HM5264805, HM5264405 Series AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264165/HM5264805/HM5264405 -10 Parameter Symbol Min 2 1 2 1 90 Max -- -- -- -- -- -12 Min 3 1 3 1 108 Max -- -- -- -- -- -15 Min 3 1 3 1 135 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 1 1 1 1 1 CKE setup time for power down t CESP exit CKE hold time t CEH Command (CS, RAS, CAS, WE, t CS DQM) setup time Command (CS, RAS, CAS, WE, t CH DQM) hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time t RC t RAS t RCD t RP t DPL 60 30 30 15 120000 72 -- -- -- 36 36 18 120000 90 -- -- -- 45 45 22.5 120000 ns -- -- -- ns ns ns 1 1 1 1 Active (a) to Active (b) command t RRD period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. tT t REF 20 1 -- -- 5 64 24 1 -- -- 5 64 30 1 -- -- 5 64 ns ns ms 1 AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CKE rising edge except power down exit command. 47 HM5264165, HM5264805, HM5264405 Series Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures 2.8 V 50 +1.4 V CL t input V SS 80% 20% I/O T tT Relationship Between Frequency and Minimum Latency HM5264165/HM5264805/HM5264405 Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input -10 100 66 Symbol 10 lRCD lRC lRAS lRP lDPL lRRD lSREX lAPW lSEC 3 9 6 3 2 2 2 5 9 15 2 6 4 2 1 2 2 3 6 33 30 1 3 2 1 1 1 2 2 3 -12 83 12 3 9 6 3 2 2 2 5 9 55 18 2 6 4 2 1 2 2 3 6 28 36 1 3 2 1 1 1 2 2 3 -15 66 15 3 9 6 3 2 2 2 5 9 44 22 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 22.5 45 2 6 4 2 1 2 2 3 6 1 3 2 1 1 1 2 2 3 48 HM5264165, HM5264805, HM5264405 Series HM5264165/HM5264805/HM5264405 Parameter Frequency (MHz) tCK (ns) Precharge c ommand t o hgh impedance i (CAS latency = 2) (CAS latency = 3) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 2) (CAS latency = 3) lEP lEP -- -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 -- -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 -- -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 -1 -2 1 0 0 2 1 1 0 1 lHZP lHZP lAPR -- 3 1 2 3 1 2 3 1 -- 3 1 2 3 1 2 3 1 -- 3 1 2 3 1 2 3 1 -10 100 66 Symbol 10 15 33 30 -12 83 12 55 18 28 36 -15 66 15 44 22 Notes 22.5 45 Column c ommand to column command lCCD Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command CS to command disable lWCD lDID lDOD lCLE lRSA lCDD Power down exit to command input lPEC Burst stop to output valid data hold (CAS latency = 2) (CAS latency = 3) Burst stop to output high impedance (CAS latency = 2) (CAS latency = 3) Burst stop to write data ignore lBSH lBSH lBSW lBSR lBSR -- 2 1 2 1 2 -- 2 1 2 1 2 -- 2 1 2 1 2 -- 3 0 2 3 0 2 3 0 -- 3 0 2 3 0 2 3 0 -- 3 0 2 3 0 2 3 0 Notes: 1. lRCD to l RRD are recommended value. 2. 2 clock is required between self refresh exit time and next refresh or active command. 49 HM5264165, HM5264805, HM5264405 Series Timing Waveforms Read Cycle t CK t CKH t CKL , , , , , , CLK t RC VIH CKE t RCD t RAS t RP , , ,, , , , , , CS t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH RAS t CS t CH t CS t CH t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t CS t CH WE t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A12/A13 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQM, DQMU/DQML DQ (input) t AC t AC t AC t HZ DQ (output) t AC Bank 0 Active Bank 0 Read t LZ t OH t OH t OH t OH Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL 50 HM5264165, HM5264805, HM5264405 Series Write Cycle , , , t CK t CKH t CKL CLK t RC VIH CKE t RCD t RAS t RP , , , CS t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH RAS t CS t CH t CS t CH t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH t CS t CH WE t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A12/A13 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQM, DQMU/DQML t DS t DH tDS t DH t DS t DH t DS t DH DQ (input) t RWL DQ (output) Bank 0 Active Bank 0 Write Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL 51 0+ *, " $ " ! , 0 , ' & . HM5264165, HM5264805, HM5264405 Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 , , , ,, , , ,,, , , , , , CLK CKE CS VIH RAS CAS WE A12/A13 (BS) Address valid code R: b C: b C: b' DQM, DQMU/DQML DQ (output) DQ (input) b b+3 b' b'+1 b'+2 b'+3 High-Z l RP l RSA l RCD Output mask Precharge If needed Mode Bank 3 register Active Set Bank 3 Read l RCD = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 52 , "! ! , " HM5264165, HM5264805, HM5264405 Series Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE VIH , , ,, , , , , , RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML R:a C:a R:b C:b C:b' C:b" DQ (output) a a+1 a+2 a+3 b b+1 b+2 b+3 b' Bank 3 Read Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL b'+1 b" b"+1 b"+2 b"+3 DQ (input) High-Z Bank 0 Active Bank 0 Read Bank 3 Active Bank 3 Bank 0 Read Precharge Bank 3 Read Bank 3 Precharge CKE CS VIH RAS CAS Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b C:b' C:b" High-Z a a+1 a+2 a+3 Bank 3 Active b b+1 b+2 b+3 b' Bank 0 Precharge b'+1 b" b"+1 b"+2 b"+3 Bank 0 Active Bank 0 Write Bank 3 Write Bank 3 Write Bank 3 Write Bank 3 Precharge 53 , * "+ !$ 0 , 0 . & 0 0 . , & . ! * $ + , & HM5264165, HM5264805, HM5264405 Series Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE VIH RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (input) R:a C:a R:b C:a' C:a a DQ (output) a a+1 a+2 a+3 a a+1 a+2 a+3 Bank 0 Precharge Bank 0 Active Bank 0 Read Bank 3 Active Bank 0 Bank 0 Write Read Bank 3 Precharge CKE CS VIH RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (input) R:a C:a R:b C:a a C:b C:c b c DQ (output) a a+1 a+3 Bank 0 Active Bank 0 Read Bank 3 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 54 " 0 $ , 0- , ". , + * . + $ ' ! & * HM5264165, HM5264805, HM5264405 Series Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (input) R:a C:a R:b C:a' a a+1 a+2 a+3 DQ (output) a a+1 a+2 a+3 Clock suspend Bank 0 Active Bank 0 Read Bank 3 Active Bank 0 Write Bank 0 Precharge Bank 3 Precharge , , , CKE CS VIH RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (input) R:a C:a R:b C:a a a+1 a+2 a+3 DQ (output) a a+1 a+3 Bank 0 Active Bank 0 Read Bank 3 Active Bank 0 Write Bank 0 Precharge Read/Burst write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 55 " , " ! ! , , " HM5264165, HM5264805, HM5264405 Series Full Page Read/Write Cycle CLK CS CKE VIH RAS CAS Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b a a+1 a+2 a+3 High-Z Bank 0 Active Bank 0 Read Bank 3 Active Burst stop Bank 3 Precharge CKE CS VIH RAS CAS Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b High-Z a a+1 a+2 a+3 a+4 a+5 a+6 Bank 0 Active Bank 0 Write Bank 3 Active Burst stop Bank 3 Precharge 56 , , , ! " ! , ! , " ! " ! , HM5264165, HM5264805, HM5264405 Series Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 , , , ,, ,, , , ,, , ,, , , , , , , , , , , , ,,, , , , , , ,, , , , CLK CKE CS VIH RAS CAS WE A12/A13 (BS) Address DQM, DQMU/DQML A10=1 R:a C:a DQ (input) DQ (output) High-Z a a+1 t RP t RC tRC Precharge If needed Auto Refresh Auto Refresh Active Bank 0 Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL Self Refresh Cycle CLK l SREX CKE CS CKE Low RAS CAS WE A12/A13 (BS) Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output) High-Z tRP tRC tRC Precharge command If needed Self refresh entry command Self refresh exit ignore command or No operation Next clock enable Self refresh entry command Auto Next clock refresh enable Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL 57 , " , ! " , ! " HM5264165, HM5264805, HM5264405 Series Clock Suspend Mode t CES t CEH t CES ,, , ,, , , , , , , , ,,,,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CS CKE RAS CAS Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b a a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank3 Active Read suspend start Read suspend end Bank3 Read Bank0 Precharge Earliest Bank3 Precharge CKE CS RAS CAS Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL WE A12/A13 (BS) Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b High-Z a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Active Active clock suspend start Active clock Bank0 Bank3 supend end Write Active Write suspend start Write suspend end Bank3 Bank0 Write Precharge Earliest Bank3 Precharge 58 5* 6: .9 ' 2, ?8 =,1 7 ! " 0 !; : 3+ 2 HM5264165, HM5264805, HM5264405 Series Power Down Mode CLK CKE CS CKE Low ,, , , ,, , ,, , , , CKE CS VIH , , , , , , ,, ,, , , ,, , , RAS CAS WE A12/A13 (BS) Address A10=1 R: a DQM, DQMU/DQML DQ (input) DQ (output) High-Z tRP Precharge command If needed Power down entry Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL Power Up Sequence 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 CLK RAS CAS WE Address valid code Valid DQM, DQMU/DQML DQ VIH High-Z t RP t RC tRC t RSA All banks Precharge Auto Refresh Auto Refresh Mode register Set Bank active If needed 59 HM5264165, HM5264805, HM5264405 Series Package Dimensions HM5264165TT/HM5264805TT/HM5264405TT Series (TTP-54D) Unit: mm 22.22 22.72 Max 54 28 1 0.30 + 0.10 - 0.05 0.91 Max 1.20 Max 0.80 0.13 M 27 10.16 11.76 0.20 0 - 5 + 0.055 - 0.025 0.08 Min 0.18 Max 0.145 0.50 0.10 60 0.68 0.10 HM5264165, HM5264805, HM5264405 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 61 HM5264165, HM5264805, HM5264405 Series Revision Record Rev. Date 0.0 0.1 Contents of Modification Drawn by Approved by May. 30, 1996 Initial issue Nov. 29, 1996 H. Miyashita K. Sato K. Sato A. Kumata Correct errors Operation of HM5264165/5264805/5264405 Series Change of description for Read/Write operaion and Full-page burst stop DC Characteristics (HM5264165) ICC3 max: 7/7/7 mA to 12/12/12 mA ICC4 (CL = 2) max: 100/85/65 mA to 150/130/100 mA I C C4 ( = 3) max : 150/ 125/ 100 m to 200/ 180/140 mA CL A I CC4 test conditions: BL = 4 to BL = 8 ICC6 max: 2/2/2 mA to 3/3/3 mA Addition of ICC5 test conditions: Address = VIL or VIH Fixed Addition of notes8 and 9 DC Characteristics (HM5264805) ICC2 max: 40/35/30 mA to 50/45/35 mA ICC3 max: 7/7/7 mA to 12/12/12 mA ICC3 max: 45/40/35 mA to 55/50/40 mA ICC4 (CL = 2) max: 100/85/65 mA to 150/130/100 mA I C C4 ( = 3) max : 150/ 125/ 100 m to 200/ 180/140 mA CL A I CC4 test conditions: BL = 4 to BL = 8 ICC6 max: 2/2/2 mA to 3/3/3 mA Addition of ICC5 test conditions: Address = VIL or VIH Fixed Addition of notes8 and 9 DC Characteristics (HM5264405) ICC3 max: 7/7/7 mA to 12/12/12 mA ICC4 (CL = 2) max: 100/85/65 mA to 140/120/95 mA I C C4 ( = 3) max : 150/ 125/ 100 m to 190/ 170/135 mA CL A ICC4 test conditions: BL = 4 to BL = 8 ICC5 max: 130/110/85 mA to 150/125/100 mA ICC6 max: 2/2/2 mA to 3/3/3 mA Addition of ICC5 test conditions: Address = VIL or VIH Fixed Addition of notes8 and 9 AC Characteristics tAC (CL = 2) max: 12/15/17 ns 9/13/15 ns Correct errors Change of description for Command Truth Table Change of figures for Operation of HM5264165, HM5264805, HM5264405 Series Change of description for Self-refresh Recommended DC Operating Conditions Change of notes2 AC Characteristics Change of symbol: t DPL to tDPL Timing Waveforms Change of Full Page Read/Write cycle 0.2 Dec. 17, 1996 62 |
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