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AS8202NF TTP-C2NF Communication Controller
Data Sheet Rev.1.4, July 2005
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the prior permission in writing by the copyright holder. To the best of its knowledge, austriamicrosystems AG asserts that the information contained in this publication is accurate and correct. TTP is a registered trademark of FTS Computertechnik GmbH. All other trademarks are the property of their respective holders.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
2
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Table of Contents
1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ................................................................................................ 4 BENEFITS......................................................................................................................... 5 KEY FEATURES ............................................................................................................... 5 PIN ASSIGNMENT ............................................................................................................ 6 PIN DESCRIPTION ........................................................................................................... 6 5.1. 6.1. 6.2. 6.3. 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 9. 10. 11. PIN DIRECTIONS .........................................................................................................................7 ABSOLUTE MAXIMUM RATINGS (NON OPERATING) ..................................................................7 RECOMMENDED OPERATING CONDITIONS................................................................................7 DC ELECTRICAL CHARACTERISTICS .........................................................................................8 HOST CPU INTERFACE ..............................................................................................................9 RESET AND OSCILLATOR .........................................................................................................12 TTP BUS INTERFACE ...............................................................................................................14 TTP ASYNCHRONOUS BUS INTERFACE ..................................................................................14 TTP SYNCHRONOUS BUS INTERFACE ....................................................................................14 TEST INTERFACE ......................................................................................................................15 LED SIGNALS ...........................................................................................................................16 ELECTRICAL SPECIFICATIONS...................................................................................... 7
APPLICATION INFORMATION......................................................................................... 9
PACKAGE....................................................................................................................... 17 ORDERING INFORMATION AND SUPPORT ............................................................. 19 RELATED PRODUCTS ............................................................................................... 19
APPENDIX ............................................................................................................................. 20 FEATURE COMPARISON .......................................................................................................................20 LIST OF APPLICATION NOTES ..............................................................................................................21 LIST OF KNOWN BUGS .........................................................................................................................21 DOCUMENT REVISION HISTORY...........................................................................................................21
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
3
TTP-C2NF Communication Controller - Data Sheet AS8202NF
1. General Description
The AS8202NF communication controller is an integrated device supporting serial (R) communication according to the TTP specification version 1.1. It performs all communication tasks such as reception and transmission of messages in a TTP cluster without interaction of the host CPU. TTP provides mechanisms that allow the deployment in high-dependability distributed real-time systems. It provides the following services: * * * * Predictable transmission of messages with minimal jitter Fault-tolerant distributed clock synchronization Consistent membership service with small delay Masking of single faults
The CNI (communication network interface) forms a temporal firewall. It decouples the controller network from the host subsystem by use of a dual ported RAM (CNI). This prevents the propagation of control errors. The interface to the host CPU is implemented as a 16-bit wide non-multiplexed asynchronous bus interface. TTP follows a conflict-free media access strategy called time division multiple access (TDMA). This means, TTP deploys a time slot technique based on a global time that is permanently synchronized. Each node is assigned a time slot in which it is allowed to perform transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds forms a cluster cycle. The operation of the network is repeated after one cluster cycle. The sequence of interactions forming the cluster cycle is defined in a static time schedule, called message descriptor list (MEDL). The definition of the MEDL in conjunction with the global time determines the response time for a service request. The membership of all nodes in the network is evaluated by the communications controller. This information is presented to all correct cluster members in a consistent fashion. During operation, the status of all other nodes is propagated within one TDMA round. Please read more about TTP and request the TTP specification at www.tttech.com.
D[15:0] A[11:0] CEB OEB WEB READYB INTB LED[2:0] RAM_CLK_TESTSE USE_RAM_CLK
Host Processor Interface
Communication network interface (CNI) --------------------Network configuration memory (MEDL)
Receiver TTP protocol processor core
RXD[1:0] RXCLK[1:0] RXDV[1:0] RXER[1:0] XIN1 XOUT1
Bus guardian
TTP Bus Media Drivers
Transmitter
TXD[1:0] CTS[1:0] TXCLK[1:0]
Quartz or Oscillator
XIN0 XOUT0 PLLOFF RESETB
Reset & time base
Instruction memory RAM & ROM
Test Interface
RAM_CLK _TESTSE FTEST STEST FIDIS TTEST
Test Interface
Figure 1. AS8202NF Block Diagram
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
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TTP-C2NF Communication Controller - Data Sheet AS8202NF
2 . B e n e f i ts
The AS8202NF provides support for fault-tolerant, high-speed bus systems in a single device. The communication controller is qualified for the full temperature range required for automotive applications and is certifiable according to RTCA standards. It offers superior reliability and supports data transfer rates of 25 Mbit/s with MII and up to 5 Mbit/s with MFM/Manchester. The AS8202NF is the first TTP controller to support both MFM and Manchester coding. Manchester coding is important for DC-free data transmission, which allows the use of transformers in the data stream. The AS8202NF is pin-compatible with its predecessor, the AS8202.
3. Key Features
* * * * * * * * * * * * * * * * * * Dedicated controller supporting TTP (time-triggered protocol class C) Suited for dependable distributed real-time systems with guaranteed response time Application fields: automotive (by-wire braking, steering, vehicle dynamics control, drive train control), aerospace (aircraft electronic systems), industrial systems, railway systems Asynchronous data rate up to 5 Mbit/s (MFM / Manchester) Synchronous data rate 5 to 25 Mbit/s Bus interface (speed, encoding) for each channel selectable independently 40 MHz main clock with support for 10 MHz crystal, 10 MHz oscillator or 40 MHz oscillator 16 MHz bus guardian clock with support for 16 MHz crystal or 16 MHz oscillator Single power supply 3.3V, 0.35m CMOS process Full automotive temperature range (-40 to 125 C C) 16k x 16 SRAM for message, status, control area (communication network interface) and for scheduling information (MEDL) 4k x 16 (plus parity) instruction code RAM for protocol execution code Data sheet conforms to protocol revision 2.03 16k x 16 instruction code ROM containing startup execution code and deprecated protocol code revision 1.00 16 Bit non-multiplexed asynchronous host CPU interface 16 Bit RISC architecture Software tools, design support, development boards available (www.tttech.com) 80 pin LQFP80 Package
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
5
TTP-C2NF Communication Controller - Data Sheet AS8202NF
4 . P i n As s i g n m e n t
60 61 TTEST D8 D9 D10 D11 D12 D13 D14 D15 VDDBG XOUT1 XIN1 VSSBG VDD VSS CEB OEB WEB READYB VSSPLL 80 1
VSS VDD D7 D6 D5 D4 D3 D2 D1 D0 VSS VDD A11 A10 A9 A8 A7 A6 A5 VSS
41 40 nc A4 A3 A2 A1 A0 USE_RAM_CLK LED2 LED1 LED0 VSS VDD INTB nc RESETB FIDIS FTEST PLLOFF STEST RAM_CLK_TESTSE 21 20
AS8202NF TTP Communications Controller
(TOP VIEW)
Figure 2. LQFP 80 Pin Package and Pin Assignment
5. Pin Description
Pin
12,29,49,59,74 13,30,41,50,60,75 70 73 4 80 21 22 24 25 61 34 2 3 23 72 71 26 5 6 11 7 8
Name
VDD VSS VDDBG VSSBG VDDPLL VSSPLL RAM_CLK_TESTSE STEST FTEST FIDIS TTEST USE_RAM_CLK XIN0 XOUT0 PLLOFF XIN1 XOUT1 RESETB TXD0 CTS0 RXD0 TXCLK0 RXER0
nc XIN0 XOUT0 VDDPLL TXD0 CTS0 TXCLK0 RXER0 RXCLK0 RXDV0 RXD0 VDD VSS TXD1 CTS1 TXCLK1 RXER1 RXCLK1 RXDV1 RXD1
Dir
P P P P P P IPD IPD IPD IPD IPU IPD A A IPD A A IPU OPU OPD IPU IPD IPU Positive Power Supply Negative Power Supply
Function
Positive Power Supply for Bus Guardian (connect to VDD) Negative Power Supply for Bus Guardian (connect to VSS) Positive Power Supply for Main Clock PLL (connect to VDD) Negative Power Supply for Main Clock PLL (connect to VSS) RAM_CLK when STEST='0' and USE_RAM_CLK='1', else Test Input, connect to VSS if not used Test Input, connect to VSS Test Input, connect to VSS Test Input, connect to VSS Test Input, connect to VDD RAM_CLK Pin Enable, connect to VSS if not used Main Clock: Analog CMOS Oscillator Input, use as input when providing external clock Main Clock: Analog CMOS Oscillator Ouptut, leave open when providing external clock Main Clock PLL Disable Pin, connect to VSS when providing 10 MHz crystal for enabling the internal PLL Bus Guardian Clock: Analog CMOS Oscillator Input, use as input when providing external clock Bus Guardian Clock: Analog CMOS Oscillator Output, leave open when providing external clock Main Reset Input, active low TTP Bus Channel 0: Transmit Data TTP Bus Channel 0: Transmit Enable TTP Bus Channel 0: Receive Data TTP Bus Channel 0: Transmit Clock (MII mode) TTP Bus Channel 0: Receive Error (MII mode)
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
6
TTP-C2NF Communication Controller - Data Sheet AS8202NF Pin
9 10 14 15 20 16 17 18 19 35-39, 42-48 51-58, 62-69 76 77 78 79 28 31-33 1, 27, 40
Name
RXCLK0 RXDV0 TXD1 CTS1 RXD1 TXCLK1 RXER1 RXCLK1 RXDV1 A[11:0] D[15:0] CEB OEB WEB READYB INTB LED[2:0] nc
Dir
IPD IPU OPU OPD IPU IPD IPU IPD IPU I I/O IPU IPU IPU OPU OPU OPD TTP Bus Channel 1: Transmit Data
Function
TTP Bus Channel 0: Receive Clock (MII mode) TTP Bus Channel 0: Receive Data Valid (MII mode) TTP Bus Channel 1: Transmit Enable TTP Bus Channel 1: Receive Data TTP Bus Channel 1: Transmit Clock (MII mode) TTP Bus Channel 1: Receive Error (MII mode) TTP Bus Channel 1: Receive Clock (MII mode) TTP Bus Channel 1: Receive Data Valid (MII mode) Host Interface (CNI) Address Bus Host Interface (CNI) Data Bus, tristate Host Interface (CNI) Chip Enable, active low Host interface (CNI) output enable, active low Host interface (CNI) write enable, active low Host interface (CNI) transfer finish signal, active low, open drain1 Host interface (CNI) time signal (interrupt), active low, open drain Configurable generic output port Not connected, leave open
Note 1: At de-assertion READYB is driven to the inactive value (high) for a configurable time.
5.1.
Dir
I IPU IPD I/O OPU OPD A P
Pin Directions
Function
TTL Input TTL Input with Internal Weak Pull-Up TTL Input with Internal Weak Pull-Down TTL Input/Output with Tristate TTL Output with Internal Weak Pull-Up at Tristate TTL Output with Internal Weak Pull-Down at Tristate Analog CMOS Pin Power Pin
6. Electrical Specifications
6.1. Absolute Maximum Ratings (Non Operating)
Parameter
DC Supply Voltage Input Voltage Input Current Storage Temperature Soldering Temperature Humidity Electrostatic Discharge Note:
Symbol
VDD Vin Iin Tstrg Tsold H ESD any pin
Conditions
Min
-0.3 -0.3 -100 -55
Typ
Max
5.0 VDD+0.3 100 150 235
Unit
V V mA C C % V
any pin, TA=25 C
t=10 sec, Reflow and Wave 5 HBM: 1KV Mil.std.883, Method 3015.7 1000
85
Stresses higher than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device under these or any other conditions higher than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (e.g. hot carrier degradation).
6.2.
Recommended Operating Conditions
Parameter Symbol
VDD
1
Conditions
VSS=0V
Min
3.0 -40
Typ
3.3
Max
3.6 125 900
Unit
V C A
DC Supply Voltage1 Ambient Temperature Static Supply Current
TA IDDs all inputs tied to VDD/VSS, clocks stopped, exclusive of I/O drive requirements, VDD=3.6V
5
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
7
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Operating Supply Current
2
IDD
2
VDD=3.3V, PLL active, exclusive of I/O drive requirements PLL active3 PLL inactive 100 25 62.5
100
4
mA ns ns ns
Clock Period of Main Clock (external) Clock Period of Bus Guardian Clock
2
CLK0_ext_PLL CLK0_ext CLK1
Note 1: The input and output parameter values in this table are directly related to ambient temperature and DC supply voltage. A temperature range other than Tamin to Tamax or a supply voltage range other than VDDmin to VDDmax will affect these values and must be evaluated on its own. Note 2: Typical values: CLK0=40 MHz, CLK1=16 MHz Note 3: Using the internal PLL multiplies the main clock frequency by 4. Note 4: To be defined
6.3.
DC Electrical Characteristics
TTL Input Pins and TTL Bidirectional Pins in Input/Tristate Mode
Parameter
Input Low Voltage Input High Voltage Input Leakage Current
Symbol
Vil Vih Iin
Conditions
Min
2.0
1
Typ
Max
0.8
1
Unit
V V
Pins without pad resistors, VDD=3.6V Pins with pulldown resistors VDD=3.0V Pins with pull-up resistors Pins with pulldown resistors Vin=0.4V Vin=0.8V VDD=3.6V Vin=0V VDD=3.6V Vin=3.6V Vin=2.0V Vin=2.5V 4.9
3
1
A
Input Low Current
Iil
8.83 -15 15 -10.73 -63 4.52 -75 75
A
Input High Current
Iih
Pins with pull-up resistors VDD=3.0V
A
Input Capacitance
Cin
pF
CMOS Inputs (XIN), drive from external clock generator Drive at XIN (XOUT = open)
Parameter
Input Capacitance Input Current Input Low Voltage Input High Voltage
Symbol
C_xin Iin_xin Vil_xin Vih_xin
Conditions
Input slope 2ns, Vil=0V, Vih=3.3V, VDD=3.3V
Min
1
Typ
1.9
Max
2.5 12
1
Unit
pF A V V
0 0.7*VDD
0.3*VDD VDD
Outputs and TTL Bidirectional Pins in Output Mode
Parameter
Output Low Current Output High Current Output Tristate Current
Symbol
Iol Ioh Ioz Tr
Conditions
VDD=3.0V, Vo = 0.4V VDD=3.0V, Vo = 2.5V VDD=3.6V T = 125 C, Slow Process, VDD=3.0V, Cload=35pF T = 125 C, Slow Process, VDD=3.0V, Cload=35pF TXD[1,0], CTS[1,0], LED[2:0], INTB D[15:0], READYB TXD[1,0], CTS[1,0], LED[2:0], INTB D[15:0], READYB
Min
1
Typ
Max
-4 4 10 8.1
2
1
Unit
mA mA A
3
Transition Time - Rise
T(Vout=0.1*VDD) to T(Vout=0.9*VDD)
ns 8.9 6
3 3
Tf Transition Time - Fall
T(Vout=0.9*VDD) to T(Vout=0.1*VDD)
ns 7
3
Note 1: If Min/Max values are both negative, they are ordered according to their absolute value.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
8
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Note 2: Typical value, not tested during production. Note 3: Implicitly tested.
8 . Ap p l i c a t i o n I n f o r m a t i o n
8.1. Host CPU Interface
The host CPU interface, also referred to as CNI (Communication Network Interface), connects the application circuitry to the AS8202NF TTP controller. All related signal pins provide an asynchronous read/write access to a dual ported RAM located in the AS8202NF. There are no setup/hold constraints referring to the microtick (main clock "CLK0"). The host interface features an interrupt or time signal INTB to notify the application circuitry of programmed and protocol-specific, synchronous and asynchronous events. The host CPU interface allows access to the internal instruction code memory. This is required for proper loading of the protocol execution code into the internal instruction code RAM, for extensive testing of the instruction code RAM and for verifying the instruction code ROM contents. INTB is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull-up resistors or transistors may be necessary depending on the application. READYB is also an open-drain output, but with a possibility to be driven to `1' for a defined time (selectable by register) before weak-pull-up at any other time. The LED port is software-configurable to automatically show some protocol-related states and events, see below for the LED port configuration. Host Interface Ports
Pin Name
A[11:0] D[15:0] CEB WEB OEB READYB INTB RAM_CLK_TESTSE USE_RAM_CLK
Mode
in inout (tri) in in In out (open drain) out (open drain) in in
Width
12 16 1 1 1 1 1 1 1
Comment
CNI address bus, 12 bit (A0 is LSB) CNI data bus, 16 bit (D0 is LSB) CNI chip enable, active low CNI write enable, active low CNI output enable, active low CNI ready, active low CNI interrupt, time signal, active low HOST clock HOST clock pin enable
Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the application. Connect USE_RAM_CLK to VSS to enable this mode of operation. Synchronous READYB uses an external clock (usually the host processor's bus clock) for synchronization of the signal eliminating external synchronization logic. Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of operation.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
9
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Asynchronous DPRAM interface
PARAMETER
Controller Cycle Time Input Valid to CEB, WEB (Setup Time)
SYMBOL
Tc 1a 2a 1b 2b 3 4 5 6 7a 7b 8 9 10 11a 11b 11c 12 13 14 A[11:0] A[11:0] A[11:0] D[15:0] A[11:0] D[15:0]
CONDITIONS
MIN
TYP
25
MAX
UNIT
ns ns
5 3 4 5 5
1,2 1,2
CEB, WEB to Input Invalid (Hold Time) Input Rising to CEB, WEB Falling CEB, WEB Rising to Input Falling Write Access Time (CEB, WEB to READYB) CEB, WEB de-asserted to READYB deasserted Input Valid to CEB, OEB (Setup Time) CEB, OEB to Input Invalid (Hold Time) Input Rising to CEB, OEB Falling CEB, OEB Rising to Input Falling Read Access Time (CEB, OEB to READYB) CEB, OEB asserted to signal asserted CEB, OEB de-asserted to signal deasserted READYB, D skew RAM_CLK_TESTSE Rising to READYB Falling RAM_CLK_TESTSE Rising to READYB Rising
ns ns ns 100 9.4 ns ns ns ns ns ns 150 8.4 8 8.8 2 ns ns ns ns ns ns
CEB, WEB, OEB CEB, WEB, OEB min = 1 Tc, max = 4 Tc
25
5 2 5 5
1 1
CEB, WEB, OEB CEB, WEB, OEB min = 1.5 Tc, max = 6 Tc D[15:0] D[15:0] READYB
37.5 4.0 3.8
USE_RAM_CLK='1' USE_RAM_CLK='1' Ready delay='00'
3.7 3 3.6 4.5 5.4 6.4 37.5 5 5
1 1
13.5 9.7 12.9 15.4 18.8 22.2
RAM_CLK_TESTSE Rising to READYB Deactivated 1->Z
15
USE_RAM_CLK ='1'
Ready delay='01' Ready delay='10' Ready delay='11'
ns
Read to Read Access Inactivity Time (CEB, OEB low to CEB, OEB low) Read to Write Access Inactivity Time (CEB, OEB low to CEB, WEB low) Write to Write Access Inactivity Time (CEB, WEB low to CEB, WEB low) Write to Read Access Inactivity Time (CEB, WEB low to CEB, OEB low)
16 17 18 19
min = 1.5 Tc
ns ns ns ns
1,2
min = 2.5 Tc
62.5
1,2
Note 1: Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). In addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. See Figure 3 for more information on the inactivity times. Note 2: To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal CONTROLLER_ON register, CEB OEB and WEB have to be stable high within 200 ns ( min = 8 Tc). Note: All values not tested during production, guaranteed by design.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
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TTP-C2NF Communication Controller - Data Sheet AS8202NF
Read
16
Read
17
Write
18
Write
19
Read
CEB OEB WEB
Figure 3. Read/Write Access Inactivity Time
Write Access Timing (CEB Controlled)
1a 1b
Write Access Timing (WEB Controlled)
1a 1b
A
Valid
A
Valid
CEB
CEB
WEB
2a 2b
WEB
2a 2b
D
Valid
D
Valid
OEB READYB
3 5 6
4
OEB READYB
3 5 6
4
Read Access Timing (CEB Controlled)
7a 7b
Read Access Timing (OEB Controlled)
7a 7b
A
Valid
A
Valid
CEB
CEB
WEB
11a
WEB
12
11b
11a
12
11b
D
8
Invalid
Valid
9
D
8
Invalid
Valid
9
OEB
10
11c
OEB
10
11c
READYB
READYB
Figure 4. Host Read/Write Access Timing
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
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TTP-C2NF Communication Controller - Data Sheet AS8202NF
Synchronous READYB Generation
asynchronous READYB RAM_CLK_TESTSE
15
synchronous READYB
13 14
Figure 5. Synchronous READYB Timing
Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host timing constraints for input setup and input hold time to/after host clock rising edge.
Note: Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of operation.
8.2.
XIN0 XOUT0 XIN1 XOUT1 PLLOFF RESETB
Reset and Oscillator
Mode
analog analog analog analog in in main oscillator output bus guardian oscillator input (external clock input) bus guardian oscillator output PLL disable external reset
Pin Name
Comment
main oscillator input (external clock input)
External Reset Signal To issue a reset of the chip the RESETB port has to be driven low for at least 1 us. Pulses under 50 ns duration are discarded. At power-up the reset must overlap the build-up time of the power supply. Integrated Power-On Reset The Device has an internal Power-On Reset generator. When supply voltage ramps up, the internal reset signal is kept active (low) for 33 s typical.
Parameter
supply voltage slope power on reset active time after VDD > 1,0V
Symbol
dV/dt tpores
Min
551 25
Typ
33
Max
49
Unit
V/ms s
Note 1: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid and oscillator inputs active.
Oscillator Circuitry The internal oscillators for main and bus guardian clock require external quartzes or external oscillators. The main clock features a PLL multiplying a 10 MHz XIN0/XOUT0 oscillation to an internal frequency of 40 MHz when enabled.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
12
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Cext 10 MHz
Cext
10 MHz square wave
VSS
40 MHz square wave
VDD
Rf XOUT0 XIN0
Rd
VSS
XOUT0
XIN0
Enabled PLL, external quartz
PLLOFF
Enabled PLL, external oscillator
PLLOFF
Disabled PLL, external oscillator
Figure 6. Main clock setup
Rf will normally not be soldered, it is only provided to get maximum flexibility. Cext, typ = 15/18 pF. Rd has to be calculated, if the measured drive level will be too high; if drive level is ok, Rd = 0. If using an external oscillator at 10 MHz with enabled internal PLL, the oscillator must have a period of 100 ns with low jitter. Note that a crystal-based clock is recommended over a derived clock (i.e., PLL-based) to allow best internal PLL performance.
Parameter
R_osc10 R_osc16 R_osc20
Conditions
Oscillation margin @ 10 MHz, Cload = 18 pF Oscillation margin @ 16 MHz, Cload = 18 pF Oscillation margin @ 20 MHz, Cload = 18 pF
Min
0.95 0.37 0.24
1 1 1
Typ
1.62 0.64 0.41
1 1 1
Max
PLLOFF
XOUT0
XIN0
Unit
kOhm kOhm kOhm
Note 1: Not tested during production. Cload is the value of the external load capacitors towards ground. The total load capacitance seen by the quartz will be Cload_tot = (Cload + Cpar)/2. Cpar is the equivalent parasitic capacitance of the oscillator cell inputs and the PCB and is derived from measurements to be about 3.5 ... 4.0 pF.
The bus guardian clock has no internal PLL and must be connected to either a 16 MHz Quartz or an external 16 MHz oscillator:
Cext 16 MHz Cext
16 MHz square wave
Rf XIN1 XOUT1
Rd
external quartz
external oscillator
Figure 7. Bus Guardian clock setup
Both the XIN0/XOUT0 (main clock) and the XIN1/XOUT1 (bus guardian clock) cells support driving a quartz crystal oscillation as well as clock input by an external oscillator. Build-up Characteristics
Parameter
Oscillator startup time (Main clock) Oscillator startup time (Bus Guardian clock)
Symbol
Tosc_startup0
Pin
XIN0/XOUT0
Min
XOUT1
XIN1
Typ
Max
20 ms
Note
Quartz frequency: 10 MHz
Tosc_startup1
XIN1/XOUT1
20 ms
Quartz frequency: 16 MHz
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
13
TTP-C2NF Communication Controller - Data Sheet AS8202NF Parameter
PLL startup time (Main clock)
Symbol
Tpll_startup0
Pin
XIN0/XOUT0
Min
Typ
Max
20 ms
Note
Quartz frequency: 10 MHz
8.3.
TTP Bus Interface
The AS8202NF contains two TTP bus units, one for each TTP channel, building the TTP bus interface. Each TTP bus channel contains a transmitter and a receiver and can be configured to be either in the asynchronous or synchronous mode of operation. Note that the two channels (channel 0 and channel 1) can be configured independently for either of these modes. The drivers of the TXD and CTS pins are actively driven only during a transmission window, all the other time the drivers are switched off and the weak pull resistors are active. External pull resistors must be used to define the signal levels during idle phases. Note that the transmission window may be different for each channel.
Pin Name
TXD[0] CTS[0] TXD[1] CTS[1]
TX inactive
weak pull-up weak pull-down weak pull-up weak pull-down
8.4.
TTP Asynchronous Bus Interface
When in asynchronous mode of operation the channel's bus unit uses a self-clocking transmission encoding which can be either MFM or Manchester at a maximum data rate of 5 Mbit/s on a shared media (physical bus). The pins can either be connected to drivers using recessive/dominant states on the wire as well as drivers using active push/pull functionality. The RXD signal uses '1' as the inactivity level. In the so-called RS485 compatible mode longer periods of '0' are treated as inactivity, too. If the RS485 compatible mode is not used, the application must care to drive RXD to '1' during inactivity on the bus.
Pin Name
TXD[0] CTS[0] TXCLK[0] RXER[0] RXCLK[0] RXDV[0] RXD[0] TXD[1] CTS[1] TXCLK[1] RXER[1] RXCLK[1] RXDV[1] RXD[1]
Mode
out out in in in in in out out in in in in in
Connect to PHY
TXD CTS
Comment
Transmit data channel 0 Transmit enable channel 0 No function (do not connect) No function (do not connect) No function (do not connect) No function (do not connect)
RXD TXD CTS
Receive data channel 0 Transmit data channel 1 Transmit enable channel 1 No function (do not connect) No function (do not connect) No function (do not connect) No function (do not connect)
RXD
Receive data channel 1
8.5.
TTP Synchronous Bus Interface
When in synchronous mode of operation, the bus unit uses a synchronous transfer method to transfer data at a rate between 5 and 25 Mbit/s. The interface is designed to run at 25 Mbit/s
Rev.1.4, Copyright 2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved. 14
TTP-C2NF Communication Controller - Data Sheet AS8202NF
and to be gluelessly compatible with the commercial 100 Mbit/s Ethernet MII (Media Independent Interface) according to IEEE standard 802.3 (Ethernet CSMA/CD). Connecting the synchronous TTP bus unit to a 100 Mbit/s Ethernet PHY is done by connecting TXD, CTS, TXCLK, RXER, RXCLK, RXDV and RXD of any channel to TXD0, TXEN, TXCLK, RXER, RXCLK, RXDV and RXD0 of the PHY's MII. The pins TXD1, TXD2 and TXD3 of the PHY's MII should be linked to VSS. The signals RXD1, RXD2, RXD3, COL and CRS as well as the MMII (Management Interface) should be left open or can be used for diagnostic purposes by the application. Note that the frames sent by the AS8202NF are not Ethernet compatible and that an Ethernet Hub (not a Switch) can be used as a 'star coupler' for proper operation. Also note that the Ethernet PHY must be configured for Full Duplex operation (even though the Hub does not support full duplex), because TTP has its own collision management that should not interfere with the PHY's Half-Duplex collision management. In general, the PHY must not be configured for automatic configuration ('Auto negotiation') but be hard-configured for 100 Mbit/s, Full Duplex operation. Note that to run the interface at a rate other than 25 Mbit/s other transceiver PHY components have to be used.
Pin Name
TXD[0] CTS[0] TXCLK[0] RXER[0] RXCLK[0] RXDV[0] RXD[0] TXD[1] CTS[1] TXCLK[1] RXER[1] RXCLK[1] RXDV[1] RXD[1]
Mode
out out in in in in in out out in in in in in
Connect to PHY
TXD0 TXEN TXCLK RXER RXCLK RXDV RXD0 TXD0 TXEN TXCLK RXER RXCLK RXDV RXD0
Transmit data channel 0
Comment
Transmit enable channel 0 Transmit clock channel 0 Receive error channel 0 Receive clock channel 0 Receive data valid channel 0 Receive data channel 0 Transmit data channel 1 Transmit enable channel 1 Transmit clock channel 1 Receive error channel 1 Receive clock channel 1 Receive data valid channel 1 Receive data channel 1
8.6.
Test Interface
The Test Interface supports the manufacturing test and characterization of the chip. In the application environment test pins have to be connected as following: STEST, FTEST, FIDIS: connect to VSS TTEST: connect to VDD Warning: Any other connection of these pins may cause permanent damage to the device and to additional devices of the application.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
15
TTP-C2NF Communication Controller - Data Sheet AS8202NF
8.7.
LED Signals
The LED port consists of three pins. Via the MEDL each of these pins can be independently configured for any of the three modes of operation. At Power-Up and after Reset the LED port is inactive and only weak pull-down resistors are connected. After the controller is switched on by the host and when it is processing its initialization, the LED port is initialized to the selected mode of operation.
Pin Name
LED2 LED1 LED0
Protocol Mode
RPV1 or Protocol activity7 Sync Valid
8 6
Timing Mode
Time Overflow2 Time Tick
2
Bus Guardian Mode
Action Time4 BDE1
5
Protocol activity or 7 RPV
Microtick3
BDE05
Note 1: RPV is Remote Pin Voting. RPV is a network-wide agreed signal used typically for agreed power-up or power-down of the application's external drivers. Note 2: Time Overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. Time Tick is active for one clock cycle when the internal time is counted up. Time Overflow and Time Tick can be used to externally clone the internal time control unit (TCU). With this information the application can precisely sample and trigger events, for example. Note 3: Microtick is the internal main clock signal. Note 4: Action Time signals the start of a bus access cycle. Note 5: BDE0 and BDE1 show the Bus Guardian's activity, '1' signals an activated transmitter gate on the respective channel. Note 6: Protocol activity is typically connected to an optical LED. The flashing frequency and rhythm give a simple view to the internal TTP protocol state. Note 7: LED2's RPV mode and LED0's Protocol activity mode can be swapped with a MEDL parameter. Note 8: The controller sets this output when cluster synchronization is achieved (after integration from the LISTEN state, after acknowledge in the COLDSTART state).
Each LED pin can be configured to be either a push/pull driver (drives both LOW and HIGH) or to be only an open-drain output (drives only LOW).
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
16
TTP-C2NF Communication Controller - Data Sheet AS8202NF
9. Package
Type: LQFP80
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
J a la n S . P a rm an Kav. 201 Ba ta m ind o Ind us tria l P a rk, Muka Kuning Ba ta m Is la nd 29433, Indonesia
17
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
J a lan S . P a rm an Kav. 201 Ba ta m ind o Indus trial P ark, Muka Kuning Ba ta m Is land 29433, Indonesia
18
TTP-C2NF Communication Controller - Data Sheet AS8202NF
10. Ordering Information and Support
Part Number: Part Name: Package: AS8202NF TTP-C2NF Communication Controller LQFP80
Please contact one of the following austriamicrosystems sales offices for further assistance:
Headquarters austriamicrosystems AG A-8141 Schloss Premstatten Austria Tel.: +43 3136 500-0 Fax: +43 3136 525-01 E-mail: info@austriamicrosystems.com Web: www.austriamicrosystems.com Sales Offices Europe austriamicrosystems Germany GmbH Tegernseer Landstrasse 85 D-81539 Munchen Germany Tel.: +49 89 693643-0 Fax: +49 89 693643-66 austriamicrosystems Italy S.r.l. Piazzale Marengo 8, I 20121 Milano Italy Tel.: +39 02 4565 910 Fax: +39 02 4892 0265 austriamicrosystems UK 88, Barkham Ride, Finchampstead, Wokingham Berks. RG40 4ET, UK. Tel.: +44 118 973-1797 Fax: +44 118 973-5117 austriamicrosystems Switzerland AG Rietstrasse 4 CH-8640 Rapperswil Switzerland Tel.: +41 55 220 9000 Fax: +41 55 220 9001 austriamicrosystems France S.a.r.l. 124, Avenue de Paris F-94300 Vincennes France Tel.: +33 1 43 74 00 90 Fax: +33 1 43 74 20 98 Sales Offices North America austriamicrosystems USA, Inc. Suite 400, 8601 Six Forks Road Raleigh, NC 27615 USA Tel.: +1 919 676 5292 Fax: +1 509 696 2713 austriamicrosystems USA, Inc. Suite 116, 4030 Moorpark Ave, San Jose, CA 95117 USA Tel.: +1 408 345 1790 Fax: +1 509 696 2713 Sales Offices Asia austriamicrosystems AG Suite 811, Tsimshatsui Centre, East Wing, 66 Mody Road, Tsim Sha Tsui East, Kowloon Hong Kong Tel.: +852 2268 6899 Fax: +852 2268 6799 austriamicrosystems AG Singapore Representative Office 83 Clemenceau Avenue #02-01 UE Square, Singapore 239920 Tel.: +65 68 30 83 05 Fax: +65 62 34 31 20 austriamicrosystems AG AIOS Gotanda Annex 5th Fl., 1-7-11, Higashi-Gotanda, Shinagawa-ku Tokyo 141-0022 Japan Tel.: +81 3 5792 4975 Fax: +81 3 5792 4976 austriamicrosystems AG #805, Dong Kyung Bldg., 824-19, Yeok Sam Dong, Kang Nam Gu, Seoul Korea 135-080 Tel.: +82 2 557 8776 Fax: +82 2 569 9823
1 1 . R e l a t e d P r o d u c ts
Software tools, hardware development boards, evaluation systems and extensive support on TTP system integration as well as consulting are provided by:
TTChip Entwicklungsgesellschaft mbH Schoenbrunner Strasse 7 A-1040 Vienna, Austria Tel.: +43 1 5853434-0 Fax: +43 1 5853434-90 E-mail: office@ttchip.com Web: www.ttchip.com
Rev.1.4, Copyright
TTTech Computertechnik AG Schoenbrunner Strasse 7 A-1040 Vienna, Austria Tel.: +43 1 5853434-0 Fax: +43 1 5853434-90 E-mail: support@tttech.com Web: www.tttech.com
19
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Ap p e n d i x
Feature Comparison
Feature
Conformance with TTP Specification Version 1.0. TTP controller
C2 AS8202
yes RISC CPU (PCU) yes (Flash) no (MEDL in Flash)
C2NF AS8202NF
yes RISC CPU (PCU) no
1
Firmware on Chip
Data load phase at power-on
yes (MEDL in RAM) - asynch. - synch.(MII) MFM Manchester 23s 16 Bit Intel <150ns (Intel) yes (access time <100ns) configurable
Interface to TTP Physical Layer TTP Bus data coding (asynchronous interface) IFG (Inter Frame Gap) Interface to Host CPU Supported Host CPU Bus Type Host CPU access speed (without "read ahead") Read ahead / Posted write
- asynch.
- synch.(MII) MFM 45s 16 Bit Intel <250ns
no
CNI-RAM configuration
fixed
(4kB to 28kB in 4kB steps) block" CRC (firmware) Parity Bit (+firmware) yes
MEDL check method Instruction RAM (I-RAM) check Method Support for X-Frames Baudrate on TTP Bus asynchronous mode synchronous mode Process SRAM ROM Flash Power supply Temperature range ( C) Package
one CRC (firmware) once (firmware) yes
up to 5MBd 25MBd 0,35 CMOS+Flash 12kByte 8kByte 32kByte 3,3V 0 to +70 LQFP80
up to 5MBd up to 25MBd 0,35 CMOS 40kByte 32kByte 3,3V -40 to +125 LQFP80
1
Note 1: The chip is designed to allow inclusion of a stable protocol code (or customized protocol code) into the ROM by changing the ROM mask in the production process. This would eliminate the need of loading the protocol firmware code into the instruction code RAM.
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
20
TTP-C2NF Communication Controller - Data Sheet AS8202NF
List of Application Notes
The following is a list of the public application notes of the AS8202NF: * AN123 Host Read Access Speedup in AS8202NF * AN134 Reception scheme changed for ignoring IFG traffic during synchronized operation * AN136 Changed Transformer Noise Tolerance in Manchester Mode in AS8202NF * AN145 TTP Protocol Binary Release 2.04 for the AS8202NF Controller The following application notes are obsolete for this data sheet: * AN133 TTP Protocol Binary Release 1.02 for the AS8202NF Controller * AN139 TTP Protocol Binary Release 2.02 for the AS8202NF Controller * AN140 TTP Protocol Binary Release 2.03 for the AS8202NF Controller
List of Known Bugs
The following is a list of the known bugs of the AS8202NF.
1. AS8202NF RX001 Receiver Bug
TTP requires a maximum level of error detection on the physical layer as well as on the semantic layer for a received message. Among others the AS8202NF has a built-in ability to detect frames that are shorter or longer than expected. This feature does not correctly work for all situations with MFM and Manchester encoding. Frames that are too short or too long can appear to have the correct size. In this case the CRC check invalidates the frame. This bug is reported as bug report AN120. The following bug reports apply to firmware versions prior to 2.02 and are obsolete for this data sheet: * AN130 Manchester Decoding Bug * AN132 AS8202/AS8202NF MFM/MII Async Reception Bug
Document Revision History
Revision 0.1 0.2 Date Dec. 17, 2002 Dec. 18, 2002 Initial release Modification Author Matthias Wachter, Rastislav Hindak Matthias Wachter
0.3
Jan. 9, 2003
0.4 0.4.5
Jan. 20, 2003 Feb. 3, 2003
0.5 0.6
Feb. 5, 2003 Feb. 10, 2003
a) Updated austriamicrosystems' logo (front page and header on each page). b) The expected maximum current is now 95 mA instead of 65 mA. The actual tested limits will be given by austriamicrosystems after the first test runs. a) "HBM: R=1.5KOhm, C=100pF" changed to "HBM: 1KV Mil.std.883, Method 3015.7" b) Operating Supply Current changed to: Imin=- , Imax=~90mA (TBD) c) Soldering Temperature changed from 260C to 235C d) Updated austriamicrosystems' logo (front page and header on each page). e) Updated input current values Feature Comparison AS8202 <-> AS8202NF added CEB, OEB to READYB (Read Access Time) - min. = 1 Tc changed to 1.5 Tc (37.5 ns) Asynchronous and synchronous definition of READYB signal changed. Renamed TXPADSOFF pin with TTEST, removed all TXPADSOFF feature description. Synchronous READYB generation added. Added timing for synchronous READYB Figure 3. & 4. updated
Rastislav Hindak
Rastislav Hindak Rastislav Hindak
Matthias Wachter Rastislav Hindak Matthias Wachter Rastislav Hindak
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
21
TTP-C2NF Communication Controller - Data Sheet AS8202NF
Revision
Date
0.7 0.8
Mar. 13, 2003 Mar. 14, 2003
Apr. 3, 2003 0.9 Apr. 8, 2003
1.0
Apr. 16, 2003
Apr. 24, 2003
May 23, 2003 Aug. 6, 2003
Aug. 21, 2003 1.1 Aug. 25, 2003 Oct. 01, 2003
Oct. 23, 2003
1.2 1.3 1.4
Nov. 05, 2003 May 07, 2004 Jul. 15, 2005
Modification Added max. current for weak-pull input/bidir pads Redraw tables, removed typos Updated Host Access inactivity time Input currents at XIN and XOUT updated Note 2 on page 7 changed from "Values not tested, guaranteed by design" to "Typical value, not tested during production". Supply voltage slope updated. Appendix - Bug List added Updated protocol code handling Removed oscillator driving at XOUT DC Electrical Characteristics: TTL Input Pins and TTL Bidirectional Pins in Input/Tristate Mode & Outputs and TTL Bidirectional Pins in Output Mode updated, Transition times added, Note 3 added. Integrated Power-On Reset - supply voltage slope: Note 1 added. Host Read Access Inactivity drawing added. DC Electrical Characteristics: Outputs and TTL Bidirectional Pins in Output Mode: Cload changed from 40 pF to 35 pF. Oscillator circuitry: oscillation margins added. DC Electrical Characteristics: Outputs and TTL Bidirectional Pins in Output Mode: Parameter Output Low/High Voltage removed. Asynchronous DPRAM interface: common note added. Added note for clock requirement when using external oscillator and internal PLL Updated for Protocol V1.02 functionality, updated LED functionality according to protocol, added references to all existing public application notes and bug reports Substitute "TTP " for "TTP/C", add contact page, minor changes in wording and formatting Minor changes in wording and formatting Figure 4.: Read Access Timing (CEB & OEB Controlled) updated. Timing of Asynchronous DPRAM interface updated (Symbol: 1b, 2b, 6, 11 (changed to 11a, 11b, 11c) and 15. Added Input Capacitance Cin for Input pins Updated values for 11a, 11b Updated data sheet, app notes, for protocol version 2.02 Updated data sheet, app notes for protocol version 2.03 Updated app notes for protocol version 2.04 Updated access inactivity times
Author
Rastislav Hindak Rastislav Hindak
Rastislav Hindak Matthias Wachter Rastislav Hindak
Rastislav Hindak
Rastislav Hindak
Matthias Wachter Matthias Wachter
Bernhard Wenzl Matthias Wachter Rastislav Hindak
Matthias Wachter
Matthias Wachter Matthias Wachter Matthias Wachter
Rev.1.4, Copyright
2000-2005, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
22

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