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Integrated Circuit Systems, Inc.
Product Data Sheet
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
PIN ASSIGNMENT (9 x 9 mm SMT)
VCCA GND REF_SEL REF_CLK0 REF_CLK1 DS_CLK_SEL nUS_CLK US_CLK VCC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2006-03 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for frequency translation and jitter attenuation of a master reference clock in a cable modem termination system (CMTS). External loop filter components allow tailoring of the PLL loop response. The M2006-03 includes a phase-slope limiting feature to prevent disruptive output clock phase changes upon input reference reselection.
FEATURES
Integrated SAW (surface acoustic wave) delay line VCSO center frequency of 491.52MHz Jitter 9ps rms, typical, over 100Hz to 12kHz Jitter 3ps rms, typical, over 12kHz to 1GHz PLL phase slope limiter circuit Single-ended reference inputs support LVCMOS, LVTTL All output clocks are differential LVPECL compatible Two downstream clocks, frequency-selectable One upstream clock, frequency-selectable REF_OUT always provides a 10.24MHz reference clock All output rising edges aligned to within 1nsec of selected input reference rising edge (unless M2_SEL= 1) Output duty cycle 47-53% worse case Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
VCC nREF_OUT REF_OUT M1_SEL M2_SEL VCC DNC DNC DNC
28 29 30 31 32 33 34 35 36
M2006-03
(Top View)
18 17 16 15 14 13 12 11 10
US_CLK_SEL1 US_CLK_SEL0 nDS_CLK_1 DS_CLK_1 GND nDS_CLK_0 DS_CLK_0 VCC GND
Figure 1: Pin Assignment
Selectable Frequencies (MHz) for M2006-03-491.5200
Input Ref. Clock: 2.048, 4.096, 10.24, or 20.48 MHz VCSO Frequency: 491.52 MHz Downstream Clock: 245.76 or 491.52 MHz Upstream Clock: 40.96, 81.92, 163.84, or 491.52 MHz Output Ref. Clock: 10.24 MHz
Table 1: Selectable Frequencies (MHz) for M2006-03-491.5200
SIMPLIFIED BLOCK DIAGRAM
M2006-03-491.52
VSCO
Reference Clock Input (20.48, 10.24, 4.096, or 2.048MHz) DS_CLK Pairs (491.52 or 245.76MHz) US_CLK Pair (491.52, 163.84, 81.92, 40.96MHz) REF_CLK Pair (10.24MHz)
MUX
DS Divider
1 0
Frequency Multiplying PLL
US Divider REF Divider
External Loop Filter M2_SEL
M1_SEL DS_CLK_SEL
US_CLK_SEL1:0
Figure 2: Simplified Block Diagram
M2006-03 Datasheet Rev 1.3
M2006-03 CMTS Direct Conversion (Zero IF) Clock Source
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
Revised 14Jul2004
Integrated Circuit Systems, Inc.
Networking & Communications
w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Product Data Sheet
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC
External Loop Filter Components
M2006-03
MUX Phase Detector
OP_IN
nOP_IN
RIN
SAW Delay Line
REF_CLK1 REF_CLK0 REF_SEL
1 0
RIN Loop Filter Amplifier
Phase Locked Loop (PLL)
M1 Divider M1 = 24 or 48
Phase Shifter VCSO
DS CLOCK Divider
= 1 or 2
DS_CLK_0 nDS_CLK_0 DS_CLK_1 nDS_CLK_1 US_CLK nUS_CLK REF_OUT nREF_OUT
M2 Divider M2 = 1 or 5
US CLOCK Divider
= 1,3,6 or 12
REF Divider
= 2 or 1
M2_SEL
M1_SEL
DS_CLK_SEL
2 US_CLK_SEL1:0
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4, 9 5, 8 6, 7 11, 19, 28, 33 27 12, 13 15, 16 20, 21 29, 30 Name GND OP_IN, nOP_IN nOP_OUT, OP_OUT nVC, VC VCC VCCA DS_CLK_0, nDS_CLK_0 DS_CLK_1, nDS_CLK_1 US_CLK_0, nUS_CLK nREF_OUT, REF_OUT, US_CLK_SEL0, US_CLK_SEL1 I/O Configuration Description
Ground Input Output Input Power Analog Power Output No internal terminator
Power supply ground. Used for external loop filter. See Figure 4. Power supply connection, connect to +3.3V 1 Analog power connection, connect to +3.3V 2 Downstream clock output pairs. Differential LVPECL. Upstream clock output pair. Differential LVPECL. Reference clock output pair. Differential LVPECL. Upstream Divider controls. LVCMOS/LVTTL. For US_CLK_SEL1:0 : Logic 1 1 sets divider to 12 " 10 " ""6 " 01 " ""3 " 00 " ""1 Downstream Divider control. LVCMOS/LVTTL: Logic 1 sets divider to 2 Logic 0 sets divider to 1 Reference clock input 1. LVCMOS/LVTTL. Reference clock input 0. LVCMOS/LVTTL. Reference clock input select. LVCMOS/LVTTL: Logic 1 selects REF_CLK1 Logic 0 selects REF_CLK0 M1 Divider control. LVCMOS/LVTTL: Logic 1 sets divider to 48 and REF Divider to 2 Logic 0 sets divider to 24 and REF Divider to 1 M2 Divider control. LVCMOS/LVTTL: Logic 1 sets divider to 5 Logic 0 sets divider to 1 Do Not Connect.
Table 2: Pin Descriptions
17, 18
Input
Internal pull-down resistor3 Internal pull-down resistor3 Internal pull-down resistor3
22 23 24 25
DS_CLK_SEL REF_CLK1 REF_CLK0 REF_SEL
Input Input Input Input Input
31
M1_SEL
Internal pull-down resistor3
32 34, 35, 36
M2_SEL DNC
Note 1: Same potential as VCCA. Note 2: Same potential as VCC. Note 3: For typical values of internal pull-down resistors, see DC Characteristics, Pull-down on pg. 5.
M2006-03 Datasheet Rev 1.3 Integrated Circuit Systems, Inc.
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M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Product Data Sheet For the M2006-03-491.5200, which has a VCSO frequency of 491.52MHz, the four feedback divider values enable use with these corresponding input reference frequencies:
VSCO Frequency (MHz)
M2006-03-491.5200
FUNCTIONAL DESCRIPTION
The M2006-03 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). The VCSO center frequency is an integer multiple of the input reference frequency. The M2006-03 is available with a 491.52MHz VCSO frequency that is specifically designed to support DOCSIS modem applications. As such, the
M2006-03-491.520 (see "Ordering Information" on pg. 6) accepts input reference frequencies of: 2.048, 4.096, 10.24, and 20.48MHz.
/
491.52
M Feedback = Divider Value 240 120 48 24
Input Reference Frequency (MHz) 2.048 4.096 10.24 20.48
M2006-03-491.5200
Table 4: Feedback Divider Values and Input Reference Frequencies
Because both inputs to the phase detector have the same frequency, the PLL can control the VCSO to keep it locked to the input reference clock. Post-PLL Dividers The M2006-03 also features three post-PLL dividers: the downstream ("DS") divider, the upstream ("US") divider, and the output reference ("REF") divider.
The DS Divider: Divides the VCSO frequency to produce one of two downstream output frequencies (1/2 or 1/1 of the VCSO frequency). The DS_CLK_SEL pin determines the DS Divider value.
DS_CLK_SEL
Input Reference The selectable reference inputs are applied to the REF_CLK1 and REF_CLK0 input pins as necessary. The REF_SEL pin selects the reference input:
* *
REF_SEL = 1 selects REF_CLK1. REF_SEL = 0 selects REF_CLK0.
The selected reference clock is supplied directly to the phase detector of the PLL. The PLL The PLL (Phase Locked Loop) includes the phase detector, the VCSO, and two feedback dividers (labeled "M1 Divider" and "M2 Divider"). The product of the two feedback divider values equals the overall feedback divider value "M". M1 x M2 = M The M1_SEL and M2_SEL pins select the individual M1 and M2 divider values and, taken in combination, the overall feedback divider value ("M").
M2_SEL M1_SEL
1 0
DS Value Downstream Output Frequencies (MHz) 2 245.76 1 491.52
M2006-03-491.5200
Table 5: Downstream Divider Selector, Values, and Frequencies
The US Divider: Divides the VCSO frequency to produce
one of four upstream output frequencies (1/12, 1/6, 1/3 or 1/1 of the VCSO frequency). The US_CLK_SEL1 and US_CLK_SEL0 pins determine the US Divider value.
US_CLK_SEL1 US_CLK_SEL0 US Value
M2 M1 Overall Feedback x Value Value = Divider "M" Value 5 1 48 24 48 24 240 120 48 24
1 1 0 0
1 0 1 0
12 6 3 1
Upstream Output Frequencies (MHz) 40.96 81.92 163.84 491.52
M2006-03-491.5200
Table 6: Upstream Divider Selectors, Values, and Frequencies
1 1 0 0
1 0 1 0
The REF Divider: Used along with the M1 divider value to ensure that the output system reference clock always equals the VCSO frequency divided by 48. The M1_SEL pin determines the REF Divider value.
M2006-03-491.5200
Table 3: Combined Feedback Divider Selectors and Values
"M" is used to divide the VCSO frequency so that it matches the input reference frequency. The relationship between the VCSO frequency, the M Divider, and the input reference frequency is: Fvcso / M = Fref_in
M2006-03 Datasheet Rev 1.3 Integrated Circuit Systems, Inc.
REF M1_SEL Value 1 0 1 2
REF Output VCSO M1 REF x Frequency / = Frequency Value Value (MHz) (MHz) 491.52 48 24 1 2 10.24
M2006-03-491.5200
Table 7: M1 Selector and REF Divider Values and Frequencies
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Outputs The M2006-03 provides a total of four differential LVPECL output pairs:
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Product Data Sheet External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M2006-03 requires the use of an external loop filter. This is provided via the provided filter pins (see Figure 4). Due to the differential signal path design, the implementation requires two identical complementary RC filters as shown here.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
* * *
Downstream - The selected frequency is output from DS_CLK_0 and from DS_CLK_1. Upstream - The selected frequency is output from US_CLK. System reference - The 10.24MHz clock is output from REF_OUT.
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
nOP_IN
VC
Figure 4: External Loop Filter
External Loop Filter Component Values for M2006-03-491.520
Input Ref. Clock Freq. 20.48MHz 10.24MHz 4.096MHz 2.048MHz PLL Damping Bandwidth Factor 1.6 1kHz 1kHz 1kHz 1kHz 2.7 2.0 2.7 R loop 9.1k 20k 50k 100k C loop 0.22F 0.22F 0.047F 0.047F R post 20k 20k 20k 20k C post 250pF 250pF 250pF 250pF
Table 8: External Loop Filter Component Values for M2006-03-491.520
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
oC
-45 to +100
Table 9: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings ard stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 0 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature
V
o
+70
C
Table 10: Recommended Conditions of Operation
M2006-03 Datasheet Rev 1.3 Integrated Circuit Systems, Inc.
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M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Product Data Sheet
ELECTRICAL SPECIFICATIONS FOR M2006-03-491.520
DC Characteristics
Unless stated otherwise, VCC = 3.3 Volts + 5%1, TA = 0 oC to 70 oC, VCSO Frequency = 491.52MHz, Outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 162
Max 3.465
Unit Test Conditions
Power Supply VCC 1 ICC All Inputs VIH VIL IIH IIL Cin Pull-down Differential Outputs
Positive Supply Power Supply Current Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance
REF_SEL, M1_SEL, M2_SEL, US_CLK_SEL0, US_CLK_SEL1, DS_CLK_SEL, REF_CLK0, REF_CLK1 (All Inputs)
V mA V V A A pF k
VCC = VCCA = 3.3V
2
Vcc + 0.3 0.8 150
-0.3 -5
4 51 Vcc - 1.0 Vcc - 1.7 0.85
Rpulldown Internal Pull-down Resistor VOH Output High Voltage VOL VP-P Output Low Voltage Peak to Peak Output
US_CLK, nUS_CLK, Vcc - 1.4 DS_CLK_0, nDS_CLK_0, V - 2.0 DS_CLK_1, nDS_CLK_1, cc 0.6 REF_OUT, nREF_OUT
V V V
Table 11: DC Characteristics
Note 1: Vcc applies to both VCC and VCCA pins (i.e., VCC = VCCA = 3.3V)
AC Characteristics
Unless stated otherwise, VCC = 3.3 Volts + 5%1, TA = 0 oC to 70 oC, VCSO Frequency = 491.52MHz, Outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min REF_CLK0, REF_CLK1
Typ 20.48 10.24 4.096 2.048 491.52 245.76 491.52 163.84 81.92 40.96 10.24
Max
Unit Test Conditions
Input Frequency Range Output Frequency Range
FIN
Input Frequency
FDS_OUT Downstream Output Frequency Range FUS_OUT Upstream Output Frequency Range
DS_CLK_0, nDS_CLK_0, DS_CLK_1, nDS_CLK_1 US_CLK, nUS_CLK
FREF_OUT Reference Output APR n VCSO Pull-Range Single Side Band Phase Noise @491.52MHz Jitter (rms)
REF_OUT, nREF_OUT
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ppm dBc/Hz dBc/Hz dBc/Hz ps ps % ms ps ps ns
M2_SEL=0, M1_SEL=0 M2_SEL=0, M1_SEL=1 M2_SEL=1, M1_SEL=0 M2_SEL=1, M1_SEL=1 DS_CLK_SEL=0 DS_CLK_SEL=1 US_CLK_SEL1:0=00 US_CLK_SEL1:0=01 US_CLK_SEL1:0=10 US_CLK_SEL1:0=11
+100
1kHz Offset 10kHz Offset 100kHz Offset Non-deterministic 47
+150 -72 -94 -123
9 3 53 100
J(t) tPW tLOCK tR tF tS
100Hz to 12kHz 12kHz to 1GHz
Output Duty Cycle, High Time 2 PLL Lock Time Output Rise Time Output Fall Time
2
325 325
450 450
500 500 1
20% to 80% 20% to 80%
2
Input to Output Skew
Rising Edge
Note 1: Vcc applies to both VCC and VCCA pins (i.e., VCC = VCCA = 3.3V) Note 2: See Parameter Measurement Information on pg. 6
Table 12: AC Characteristics
M2006-03 Datasheet Rev 1.3 Integrated Circuit Systems, Inc.
5 of 6 Networking & Communications
Revised 14Jul2004 w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Product Data Sheet
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time Output Duty Cycle
nFOUT FOUT VP-P Clock Output 20% tR 20% tF odc = tPW tPERIOD tPW (Output Pulse Width) tPERIOD
80%
80%
Figure 5: Output Rise and Fall Time
Figure 6: Output Duty Cycle
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at www.icst.com/products/appnotes/SawPllAppNotes.htm for application notes, including recommended PCB footprint, solder mask, and furnace profile.
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
For VCSO Frequency (MHz) 491.52 Order Part Number
M2006-03-491.5200
Table 13: Ordering Information
Other frequencies available upon request.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
M2006-03 Datasheet Rev 1.3 Integrated Circuit Systems, Inc.
6 of 6 Networking & Communications
Revised 14Jul2004 w w w. i c s t . c o m
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