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19-2544; Rev 1; 12/02
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
General Description
The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a -2.375V to -3.8V supply. A VBB reference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs. The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over -40C to +85C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet. o 300mV Differential Output at 1.0GHz o 900ps Propagation Delay o Selectable Divide-by-1 or Divide-by-2 Frequency Outputs o Multiplexed 2:1 Input Function o LVECL Operation from VEE = -2.375V to -3.8V o LVPECL Operation from VCC = +2.375V to +3.8V o ESD Protection: > 2kV Human Body Model
Features
o 1.2ps (RMS) Maximum Random Jitter
MAX9322
Ordering Information
PART MAX9322ECY MAX9322ETK* TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 52 TQFP 68 QFN
Applications
Precision Clock Distribution Low-Jitter Data Repeaters Central-Office Backplane Clock Distribution DSLAM Backplane Base Stations ATE
*Future product--contact factory for availability.
Pin Configurations
TOP VIEW
VCCO VCCO VCCO
40 39 VCCO 2 38 QC0 3 37 QC0 4 36 QC1 5 35 QC1 6 7 8 32 QC3 9 31 QC3 30 VCCO 29 N.C. 34 QC2 33 QC2 28 N.C. 27 VCCO 26
QA0
QA0
QA1
QA1
QB0
QB0
QB1
QB1
QB2
42 24
52
51
50
49
48
47
46
45
44
43
41
VCC MR FSELA
1
Typical Operating Circuit
FSELB CLK0 CLK0 CLK_SEL CLK1
MAX9322
MAX9322
ZO = 50 Q_
RECEIVER
CLK1
VBB 10 FSELC 11 FSELD 12
ZO = 50 Q_
VEE 13
14
15
16
17
18
19
20
21
22
23
QD5
QD5
QD4
QD4
QD3
QD3
QD2
QD2
QD1
QD1
QD0
QB2
25
50
50
VCCO
TQFP
VTT = VCC - 2.0V
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
QD0
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
ABSOLUTE MAXIMUM RATINGS
VCC to VEE .............................................................................4.1V Inputs and Outputs to VEE..........................-0.3V to (VCC + 0.3V) Differential Input Magnitude............Lower of (VCC - VEE) and 3V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 52-Pin TQFP (derate 15.4mW/C above +70C).....1230.8mW 68-Lead QFN (derate 27.8mW/C above +70C) ...2222.2mW Multilayer PC Board 52-Pin TQFP (derate 19.1mW/C above +70C).....1529.6mW 68-Lead QFN (derate 38.5mW/C above +70C) ...3076.9mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 52-Pin TQFP...............................................................+65C/W 68-Lead QFN .............................................................+36C/W Multilayer PC Board 52-Pin TQFP............................................................+52.3C/W 68-Lead QFN .............................................................+26C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow Single-Layer PC Board 52-Pin TQFP...............................................................+50C/W 68-Lead QFN .............................................................+27C/W Multilayer PC Board 52-Pin TQFP...............................................................+40C/W 68-Lead QFN .............................................................+20C/W Junction-to-Case Thermal Resistance 52-Pin TQFP............................................................+12.9C/W 68-Lead QFN ...............................................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Q_ _, Q_ _, CLK_SEL, FSEL_, CLK_, CLK_, MR, VBB) ............................................2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
((VCC - VEE) = 2.375V to 3.8V, outputs loaded with 50 1% to VCC - 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (VCC - VEE ) and 3V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40C MIN VCC 1.155 VCC 1.81 -15 TYP MAX VCC 0.88 MIN VCC 1.155 +25C TYP MAX MIN +85C TYP MAX VCC 0.88 VCC 1.505 +150 UNITS
SINGLE-ENDED INPUT (MR, FSEL_, CLK_SEL) Input High Voltage Input Low Voltage Input Current VIH1 VIL1 IIN1 Figure 1 Figure 1 VCC - VCC 0.88 1.155 VCC - VCC 1.505 1.81 +150 -15 V V A
VCC - VCC 1.505 1.81 +150 -15
MR, FSEL_, CLK_SEL = VIL or VIH DIFFERENTIAL INPUT (CLK_, CLK_) Single-Ended Input High Voltage Single-Ended Input Low Voltage High Voltage of Differential Input Low Voltage of Differential Input VIH2 VIL2 VIHD VILD Figure 1 Figure 1
VCC 1.155 VCC 1.81 VEE + 1.2 VEE
VCC - VCC 0.88 1.155 VCC - VCC 1.505 1.81 VCC VCC 0.095 VEE + 1.2 VEE
VCC - VCC 0.88 1.155 VCC - VCC 1.505 1.81 VCC VCC 0.095 VEE + 1.2 VEE
VCC 0.88 VCC 1.505 VCC VCC 0.095
V V V V
2
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
DC ELECTRICAL CHARACTERISTICS (continued)
((VCC - VEE) = 2.375V to 3.8V, outputs loaded with 50 1% to VCC - 2V; CLK_SEL, FSEL_ = high or low; MR = low; |VID| = 0.095V to the lower of (VCC - VEE ) and 3V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS For VCC - VEE < 3.0V For VCC - VEE 3.0V CLK_, CLK_ = VIHD or VILD -40C MIN 0.095 0.095 -150 TYP MAX MIN VCC 0.095 VEE 3.0 +150 0.095 -150 +25C TYP MAX MIN VCC 0.095 VEE 3.0 +150 0.095 -150 +85C TYP MAX VCC VEE V 3.0 +150 A UNITS
MAX9322
Differential Input Voltage
VIHD VILD
Input Current OUTPUTS (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage REFERENCE Reference Voltage Output SUPPLY Supply Current
IIN2
VOH
Figure 1
VCC 1.085
VCC - VCC 0.880 1.025
VCC - VCC 0.880 1.025
VCC 0.880
V
VOL VOH VOL
Figure 1
VCC 1.810 500
VCC - VCC 1.52 1.810 600
VCC - VCC 1.620 1.810 600
VCC 1.620
V
Figure 1
mV
VBB
IBB = 0.5mA (Note 5) (Note 6)
VCC 1.41 50
VCC - VCC 1.25 1.41 85 66
VCC - VCC 1.25 1.41 115 80
VCC 1.25 130
V
IEE
mA
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3
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
AC ELECTRICAL CHARACTERISTICS
((VCC - VEE) = 2.375V to 3.8V; outputs loaded with 50 1% to VCC - 2V; input frequency 1000MHz; input transition time = 125ps (20% to 80%); CLK_SEL, FSEL_ = high or low, MR = low; VIHD = VEE + 1.2V to VCC; VILD = VEE to VCC - 0.4V; VIHD - VILD = 0.4V to 1V. Typical values are at (VCC - VEE) = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Note 7)
PARAMETER Differential Input-toOutput Delay Single-Ended CLK_/CLK_ to Output Delay MR to Output Delay Output-to-Output Skew Added Random Jitter SYMBOL tPLHD, tPHLD tPHLS, tPLHS tPD tSKOO CONDITION MIN Figure 2 700 -40C TYP 900 MAX 1150 MIN 725 +25C TYP 900 MAX 1180 MIN 750 +85C TYP 950 MAX 1225 UNITS ps
Figure 1
700
900
1170
700
900
1175
725
950
1250
ps
Figure 3 (Note 8) fIN = 1.0GHz clock pattern (Note 9) 1Gbps 223 - 1 PRBS pattern (Note 9) VOD > 300mV
450
930 85
450
930 56
450
930 50
ps ps ps (RMS)
tRJ
1.2
1.2
1.2
Added Deterministic Jitter Switching Frequency Differential Output Rise and Fall Time (20% to 80%)
tDJ
61
61
61
psP-P
fMAX
1.0
1.0
1.0
GHz
tR , t F
Figure 2
200
260
400
200
260
400
200
240
400
ps
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. Single-ended CLK_, CLK_ input operation is limited to VCC - VEE = 3.0V to 3.8V. DC parameters are production tested at TA = +25C and guaranteed by design over the full operating temperature range. Use VBB as a reference for inputs of the same device only. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at 6 sigma. Measured between outputs of the same parts at the signal crossing points under identical conditions for a same-edge transition. Device jitter added to a jitter-free input signal.
4
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, VID = 500mV, CLK_SEL = 0, FSEL_ = 0, fIN = 600MHz, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT, IEE vs. TEMPERATURE
MAX9322 toc01
OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY
MAX9322 toc02
TRANSITION TIME vs. TEMPERATURE
MAX9322 toc03
85
800 700 OUTPUT AMPLITUDE (V) 600 500 400 300 200 100
270 260 TRANSITION TIME (ps) 250 240 230 220 210 200 tF tR
75 SUPPLY CURRENT (mA)
65
55
45
35 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (C)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD
MAX9322 toc04
PROPAGATION DELAY vs. TEMPERATURE
MAX9322 toc05
PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
MAX9322 toc06
910 905 PROPAGATION DELAY (ps) 900 895 890 885 880 1.2 1.5 1.8 2.1 2.4 2.7 3.0
1020 1000 PROPAGATION DELAY (ps) 980 960 940 920 900 880 860 DIFFERENTIAL CLOCK SINGLE-ENDED CLOCK VIH2 = VCC = 1.15V VIL2 = VCC = 1.48V
950
PROPAGATION DELAY (ps) 35 60 85
910
870
830
790
750 -40 -15 10 0 0.5 1.0 1.5 2.0 2.5 3.0 TEMPERATURE (C) DIFFERENTIAL INPUT VOLTAGE (VIHD - VILD) (V)
3.3
VIHD - VEE (V)
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5
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
Pin Description
PIN TQFP 1 QFN 2, 3 NAME FUNCTION Positive Power Supply. Powers input circuitry. Bypass each VCC to VEE with a 0.01F and 0.1F capacitor. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Single-Ended Master Reset. A high on MR sets all outputs to differential zero. A low on MR enables all outputs. MR is pulled to VEE through a 75k resistor. Single-Ended Frequency Select A. Selects the output frequency for bank A. Bank A consists of two differential outputs. A low on FSELA selects divide-by-1. A high on FSELA selects divide-by-2. FSELA is pulled to VEE through a 75k resistor. Single-Ended Frequency Select B. Selects the output frequency for bank B. Bank B consists of three differential outputs. A low on FSELB selects divide-by-1. A high on FSELB selects divide-by-2. FSELB is pulled to VEE through a 75k resistor. Noninverting Clock 0 Input. CLK0 is pulled to VEE through 75k resistors. Inverting Clock 0 Input. CLK0 is pulled to VCC and to VEE through a 75k resistor. Single-Ended Clock Selector Input. A low on CLK_SEL selects CLK0. A high on CLK_SEL selects CLK1. CLK_SEL is pulled to VEE through a 75k resistor. Noninverting Clock 1 Input. CLK1 is pulled to VEE through a 75k resistor. Inverting Clock 1 Input. CLK1 is pulled to VCC and to VEE through 75k resistors. Reference Voltage Output. Connect VBB to CLK_ or CLK_ to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise leave open. Single-Ended Frequency Select C. Selects the output frequency for bank C. Bank C consists of four differential outputs. A low on FSELC selects divide-by-1. A high on FSELC selects divide-by-2. FSELC is pulled to VEE through a 75k resistor. Single-Ended Frequency Select D. Selects the output frequency for bank D. Bank D consists of six differential outputs. A low on FSELD selects divide-by-1. A high on FSELD selects divide-by-2. FSELD is pulled to VEE through a 75k resistor. Negative Power-Supply Input Output Driver Positive Power Supply. Powers device output drivers. Bypass each VCCO to VEE with a 0.01F and 0.1F capacitor. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Inverting QD5 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD5 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QD4 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD4 Output. Typically terminate with 50 resistor to VCC - 2V.
VCC
2
4
MR
3
5
FSELA
4 5 6 7 8 9 10
6 7 8 9 10 11 12
FSELB CLK0 CLK0 CLK_SEL CLK1 CLK1 VBB
11
13
FSELC
12 13 14, 27, 30, 39, 40, 47, 52 15 16 17 18
14 15, 16 19, 20, 33, 36, 37, 40, 49, 50, 53, 54, 61, 66, 67 21 22 23 24
FSELD VEE
VCCO
QD5 QD5 QD4 QD4
6
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Pin Description (continued)
PIN TQFP 19 20 21 22 23 24 25 26 28, 29 31 32 33 34 35 36 37 38 41 42 43 44 45 46 48 49 50 51 -- QFN 25 26 27 28 29 30 31 32 1, 17, 18, 34, 35, 38, 39, 51, 52, 68 41 42 43 44 45 46 47 48 55 56 57 58 59 60 62 63 64 65 EP NAME QD3 QD3 QD2 QD2 QD1 QD1 QD0 QD0 N.C. QC3 QC3 QC2 QC2 QC1 QC1 QC0 QC0 QB2 QB2 QB1 QB1 QB0 QB0 QA1 QA1 QA0 QA0 VEE FUNCTION Inverting QD3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QD2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QD1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QD0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QD0 Output. Typically terminate with 50 resistor to VCC - 2V. No Connection. Not internally connected. Inverting QC3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QC3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QC2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QC2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QC1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QC1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QC0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QC0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA0 Output. Typically terminate with 50 resistor to VCC - 2V. The exposed pad of the QFN package is internally connected to VEE. Refer to Application Note HFAN-08.1.
MAX9322
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7
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
MR, FSEL_, CLK_SEL VIH1 VBB VIL1
CLK_ CLK_ (CLK_ IS CONNECTED TO VBB)
VIH2 VBB VIL2
tPHLS Q_ VOH - VOL Q_
tPLHS VOH
VOL
Figure 1. Timing Diagram for Single-Ended Inputs
CLK_ VIHD - VILD CLK_
VIHD
VILD
tPLHD
tPHLD VOH VOH - VOL
Q_
Q_
VOL
80% 0V (DIFFERENTIAL) 20% Q_ - Q_ tR
80% 0V (DIFFERENTIAL) 20% tF VOH - VOL
Figure 2. Timing Diagram for Differential Inputs
8
_______________________________________________________________________________________
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
VIH VBB MR VIL
tPD VOH
Q_ Q_
VOL
Figure 3. Timing Diagram for MR
Detailed Description
The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input frequency operation in excess of 1.0GHz. The 15 outputs are arranged into four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function.
all outputs for normal operation. A high on MR resets all outputs to differential low condition. See Table 1.
Input Termination Resistors
Differential inputs CLK_ and CLK_ are biased to guarantee a known state (differential low) if the inputs are left open. CLK_ is internally pulled to VEE through a 75k resistor. CLK_ is internally pulled to VCC and to VEE through 75k resistors. Single-ended inputs FSEL_, MR, and CLK_SEL are internally pulled to VEE through a 75k resistor.
LVECL/LVPECL Operation
Output levels are referenced to VCC and are LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to ground, the outputs are LVPECL. The outputs are LVECL when VCC is connected to ground and VEE is connected to a negative supply. When interfacing to differential LVPECL signals, the VCC range is 2.375V to 3.8V (VEE = 0), allowing high-performance clock distribution in systems with nominal 2.5V and 3.3V supplies. When interfacing to differential LVECL, the VEE range is -2.375V to -3.8V (VCC = 0).
Differential Clock Input
The MAX9322 accepts two differential or single-ended clock inputs, CLK0/CLK0 and CLK1/CLK1. CLK_SEL selects between CLK0/CLK0 and CLK1/CLK1. A low on CLK_SEL selects CLK0/CLK0. A high on CLK_SEL selects CLK1/CLK1. See Table 1. Differential CLK_ inputs must be at least VBB 95mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. The maximum magnitude of the differential signal applied to the differential clock input is the lower of (VCC - VEE) and 3.0V. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously.
Control Inputs (FSEL_, CLK_SEL, MR)
The MAX9322 provides four output banks: A, B, C, and D. Bank A consists of two differential output pairs. Bank B consists of three differential output pairs. Bank C consists of four differential output pairs. Bank D consists of six differential output pairs. FSEL_ selects the output clock frequency for a bank. A low on FSEL_ selects divide-by-1 frequency operation while a high on FSEL_ selects divide-by-2 operation. CLK_SEL selects CLK0 or CLK1 as the input signal. A low on CLK_SEL selects CLK0 while a high selects CLK1. Master reset (MR) enables all outputs. CLK_SEL and FSEL_ are asynchronous. Changes to the control inputs (CLK_SEL, FSEL_) or on power-up cause indeterminate output states requiring a MR assertion to resynchronize any divide-by-2 outputs (Figure 4). A low on MR activates
Table 1. Function Table
PIN FSEL_ CLK_SEL MR* FUNCTION LOW OR OPEN Divide-by-1 CLK0 Active HIGH Divide-by-2 CLK1 Reset
*A master reset is required following power-up or changes to input functions to prevent indeterminant output states. 9
_______________________________________________________________________________________
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Single-Ended Inputs and VBB The differential clock input can be configured to accept a single-ended input when operating at VCC - VEE = 3.0V to 3.8V. Connect VBB to the inverting or noninverting input of the differential input as a reference for single-ended operation. The differential CLK_ input is converted to a noninverting, single-ended input by connecting VBB to CLK_ and connecting the single-ended input signal to CLK. Similarly, an inverting configuration is obtained by connecting VBB to CLK_ and connecting the single-ended input to CLK_. The single-ended inputs FSEL_, CLK_SEL, and MR are internally referenced to VBB. All single-ended inputs (FSEL_, CLK_SEL, MR, and any CLK_ in single-ended mode) can be driven to VCC and VEE or with a singleended LVPECL/LVECL signal. The single-ended input must be at least VBB 95mV to switch the outputs to the V OH and V OL levels specified in the DC Electrical Characteristics table. When using the VBB reference output, bypass VBB with a 0.01F ceramic capacitor to VCC. Leave VBB open when not used. The VBB reference can source or sink 0.5mA. Use VBB as a reference for the same device only.
MAX9322
Applications Information
Supply Bypassing
Bypass each VCC and VCCO to VEE with high-frequency surface-mount ceramic 0.01F and 0.1F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass VBB to VCC with a 0.01F ceramic capacitor.
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9322. Connect input and output signals with 50 characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces.
Output Termination
Terminate outputs with 50 to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if QA0 is used as a single-ended output, terminate both QA0 and QA0.
CLK_
MR
Q_(/1)
Q_(/2)
Figure 4. Timing Diagram for MR Resynchronization
10
______________________________________________________________________________________
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Functional Diagram
FSELA 75k
MAX9322
MAX9322
VEE CLK0 VCC 75k 75k VEE CLK0 75k /2 CLK1 75k 75k VEE CLK1 75k 1 VEE CLK_SEL 75k VEE MR 75k VEE FSELB BANK C 75k VEE FSELC 75k VEE QD0 QD0 QD1 QD1 QD2 QD2 1 FSELD 75k VEE VBB QD5 QD5 QD3 QD3 QD4 QD4 0 QC0 QC0 QC1 QC1 1 QC2 QC2 QC3 QC3 QB2 QB2 0 BANK B QB0 QB0 QB1 QB1 VEE VCC 1 QA1 QA1 BANK A /1 0 QA0 QA0
BANK D 0
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11
LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MAX9322
Pin Configurations (continued)
VCCO VCCO VCCO VCCO N.C. N.C.
51 N.C. 50 VCCO 49 VCCO 48 QC0 47 QC0 46 QC1 45 QC1 44 QC2 43 QC2 42 QC3 41 QC3 40 VCCO 39 N.C. 38 N.C. 37 VCCO 36 VCCO 35 N.C.
QA0
QA0
QA1
QA1
QB0
QB0
QB1
QB1
QB2
68
67 66 65 64
63 62 61 60 59 58 57 56 55 54 53 52
N.C. VCC VCC MR FSELA FSELB CLK0 CLK0 CLK_SEL
1 2 3 4 5 6 7 8 9
MAX9322
CLK1 10 CLK1 11 VBB 12 FSELC 13 FSELD 14 VEE 15 VEE 16 N.C. 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
VCCO
VCCO
QB2
TOP VIEW
VCCO VCCO
N.C.
QD5
QD5
QD4
QD4
QD3
QD3
QD2
QD2
QD1
QD1
QD0
QFN*
THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO VEE FOR PROPER THERMAL AND ELECTRICAL OPERATION OF THE MAX9322.
QD0
N.C.
Chip Information
TRANSISTOR COUNT: 2063 PROCESS: Bipolar
12
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
52L TQFP.EPS
MAX9322
D D1
e
D1 4 E1
SEE NOTE 2
E
E1 4
b
52
DIM A A1 A2 b c D D1 E E1 e L
NOM 0.10 1.00 0.32 12.00 10.00 BSC 12.00 11.80 10.00 BSC 0.65 BSC 0.60 0.45
MIN 0.05 0.95 0.22 0.09 11.80
MAX 1.20 0.15 1.05 0.38 0.20 12.20 12.20
0.75
1
TOP VIEW
0 MIN.
SEE DETAIL "A" A
A2
GAGE PLANE
SEATING PLANE
0.25
A1
1.00 REF
L 0-7
c
DETAIL A
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 52L TQFP, 10x10x1.0 MM
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0146
A
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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