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IC41C1665 IC41LV1665
Document Title
64K x16 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
October 17,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
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IC41C1665 IC41LV1665
64K x 16 (1-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
* * * * * *
DESCRIPTION
* *
The ICSI IC41C1665 and the IC41LV1665 are 65,536 x 16Fast access and cycle time bit high-performance CMOS Dynamic Random Access TTL compatible inputs and outputs Memory. Fast Page Mode allows 256 random accesses Refresh Interval: 256 cycles/4 ms within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower Refresh Mode: RAS-Only, CAS-before-RAS byte, makes these devices ideal for use in 16-, 32-bit wide (CBR), Hidden data bus systems. JEDEC standard pinout These features make the IC41C1665 and the IC41LV1665 Single power supply: ideally suited for high band-width graphics, digital signal -- 5V 10% (IC41C1665) processing, high-performance computing systems, and peripheral applications. -- 3.3V 10% (IC41LV1665) The IC41C1665 and the IC41LV1665 are packaged in a 40Byte Write and Byte Read operation via pin, 400mil SOJ and TSOP-2. two CAS Available in 40-pin SOJ and TSOP-2 KEY TIMING PARAMETERS
Parameter -25 -30 30 9 16 20 55 -35 35 10 18 23 65 -40 40 11 20 25 75 Unit ns ns ns ns ns
Max. RAS Access Time (tRAC) 25 Max. CAS Access Time (tCAC) 8 Max. Column Address Access Time (tAA) 12 Min. Fast Page Mode Cycle Time (tPC) 15
PIN CONFIGURATIONS 40-Pin TSOP-2
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
Min. Read/Write Cycle Time (tRC)
43
40-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A7 I/O0-I/O15 WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
NC NC WE RAS NC A0 A1 A2 A3 VCC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC LCAS UCAS OE NC A7 A6 A5 A4 GND
NC WE RAS NC A0 A1 A2 A3 VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
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IC41C1665 IC41LV1665
FUNCTIONAL BLOCK DIAGRAM
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 65,536 x 16
ADDRESS BUFFERS A0-A7
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IC41C1665 IC41LV1665
TRUTH TABLE
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh2) RAS-Only Refresh CBR Refresh(3) RAS H L L L L L L L Read LHL Write LHL L HL LCAS UCAS H H L L L H H L L H L L L H L L L H L L L L H L WE X H H H L L L HL H L X X OE X L L L X X X LH L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DIN High-Z High-Z
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS).
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IC41C1665 IC41LV1665
FUNCTIONAL DESCRIPTION
The IC41C1665 and the IC41LV1665 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered nine bits (A0-A7) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first eight bits and CAS is used to latch the latter eight bits. The IC41C1665 and the IC41LV1665 have two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generate a CAS signal functioning in an identical manner to the single CAS input on the other 64K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 - I/O7 and UCAS controls I/O8 - I/O15. The IC41C1665/IC41LV1665 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IC41C1665 both BYTE READ and BYTE WRITE cycle capabilities.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Refresh Cycle
To retain data, 256 refresh cycles are required in each 4 ms period. There are two ways to refresh the memory: 1. By clocking each of the 256 row addresses (A0 through A7) with RAS at least once every 4 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 8-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOE are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
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IC41C1665 IC41LV1665
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power DICSIpation Operation Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating -1.0 to +7.0 -0.5 to +4.6 -1.0 to +7.0 -0.5 to +4.6 50 1 0 to +70 -40 to +85 -55 to +125 Unit V V V V mA W o C o C o C
Com. Ind.
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol VCC VIH VIL TA Parameter Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature 5V 3.3V 5V 3.3V 5V 3.3V Com. Ind. Min. 4.5 3.0 2.4 2.0 -1.0 -0.3 0 -40 Typ. 5.0 3.3 -- -- -- -- -- -- Max. 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 Unit V V V V V V o C o C
CAPACITANCE(1,2)
Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A7 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. 5 7 7 Unit pF pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 5.0V + 10%, or VCC = 3.3V + 10%.
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ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter IIL IIO VOH VOL ICC1 ICC1 ICC2 ICC2 ICC3 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Stand-by Current: TTL Stand-by Current: TTL Stand-by Current: CMOS Stand-by Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR(2,3,5) Average Power Supply Current Test Condition Any input 0V VIN Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V VOUT Vcc IOH = -5 mA IOL = +4.2 mA RAS, LCAS, UCAS VIH RAS, LCAS, UCAS VIH RAS, LCAS, UCAS VCC - 0.2V RAS, LCAS, UCAS VCC - 0.2V RAS, LCAS, UCAS, Address Cycling, tRC = tRC (min.) 5V 3.3V 5V 3.3V -25 -30 -35 -40 -25 -30 -35 -40 -25 -30 -35 -40 -25 -30 -35 -40 Speed Min. -10 -10 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 10 10 -- 0.4 2 1 1 0.5 170 150 130 120 170 150 130 120 170 150 130 120 170 150 130 120 Unit A A V V mA mA mA mA mA mA mA
ICC4
RAS = VIL, LCAS, UCAS, Cycling tPC = tPC (min.)
mA
ICC5
RAS Cycling, LCAS, UCAS VIH tRC = tRC (min.)
mA
ICC6
RAS, LCAS, UCAS Cycling tRC = tRC (min.)
mA
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each fast page cycle. 5. Enables on-chip refresh and address counters.
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IC41C1665 IC41LV1665
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) -25 Min. Max. 43 -- -- -- 25 15 4 4 21 10 0 5 0 5 22 8 12 10 8 3 5 -- -- 5 0 0 0 5 22 5 7 5 0 22 -- 25 8 12 10k -- 10k -- -- 17 -- -- -- -- -- 13 -- -- -- -- -- 6 8 -- -- -- -- -- -- -- -- -- -- -- -30 Min. Max. 55 -- -- -- 30 20 9 5 30 10 0 5 0 5 26 8 16 10 9 3 5 -- -- 5 0 0 0 5 26 5 8 6 0 26 -- 30 9 16 10K -- 10K -- -- 21 -- -- -- -- -- 14 -- -- -- -- -- 8 9 -- -- -- -- -- -- -- -- -- -- -- -35 Min. Max. 65 -- -- -- 35 23 10 6 35 10 0 5 0 5 30 8 18 10 10 3 5 -- -- 5 0 0 0 5 30 5 9 7 0 30 -- 35 10 18 10K -- 10K -- -- 25 -- -- -- -- -- 17 -- -- -- -- -- 8 10 -- -- -- -- -- -- -- -- -- -- -- -40 Min. Max. 75 -- -- -- 40 25 11 7 40 10 0 5 0 5 34 8 20 10 11 3 5 -- -- 5 0 0 0 5 34 5 10 8 0 34 -- 40 11 20 10K -- 10K -- -- 29 -- -- -- -- -- 20 -- -- -- -- -- 8 11 -- -- -- -- -- -- -- -- -- -- --
Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOES tRCS tRRH tRCH tWCH tWCR tWP tRWL tCWL tWCS tDHR
Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS)
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Continued)
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IC41C1665 IC41LV1665
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) -25 Min. Max. 15 4 0 5 65 34 17 21 15 25 -- 37 3 4 5 7 0 -- 1 -- -- -- -- -- -- -- -- -- 10k 14 -- 15 -- -- -- -- 4 50 -30 Min. Max. 15 4 0 5 85 46 25 32 20 30 -- 42 3 9 10 10 0 -- 1 -- -- -- -- -- -- -- -- -- 10K 18 -- 15 -- -- -- -- 4 50 -35 Min. Max. 15 4 0 5 95 51 26 34 23 35 -- 49 3 10 10 10 0 -- 1 -- -- -- -- -- -- -- -- -- 10K 20 -- 15 -- -- -- -- 4 50 -40 Min. Max. 15 5 0 5 105 56 27 36 25 40 -- 52 3 11 10 10 0 -- 1 -- -- -- -- -- -- -- -- -- 10K 22 -- 15 -- -- -- -- 4 50
Symbol Parameter tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tOFF tCLCH tCSR tCHR tORD tREF tT Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITEcycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITECycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time(24) Fast Page Mode RAS Pulse Width Access Time from CAS Precharge(15) Fast Page Mode READ-WRITE Cycle Time(24) Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (256 Cycles) Transition Time (Rise or Fall)(2, 3)
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V 10%) One TTL Load and 50 pF (Vcc = 3.3V 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V 10%); VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V 10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V 10%, 3.3V 10%)
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IC41C1665 IC41LV1665
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first CAS edge to transition LOW. 21. The last CAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling CAS edge to first rising CAS edge. 24. Last rising CAS edge to next cycleOs last rising CAS edge. 25. Last rising CAS edge to first falling CAS edge. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters.
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IC41C1665 IC41LV1665
READ CYCLE
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
UCAS-LCAS
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLZ
tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Don't Care
Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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IC41C1665 IC41LV1665
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC tRAS
tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tAR tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
Row
tRCS
Column
tRWD tCWD tAWD
Row
tCWL tRWL tWP
WE
tAA tRAC tCAC tCLZ tDS tDH
I/O
Open
tOE
Valid DOUT
tOD
Valid DIN
Open
tOEH
OE
Don't Care
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IC41C1665 IC41LV1665
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
UCAS/LCAS
tAR tASR tRAD tRAH tASC tRAL tCAH tACH
ADDRESS
Row
Column
tCWL tRWL tWCR tWCS tWCH tWP
Row
WE
tDHR tDS tDH
I/O
Valid Data
Don't Care
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IC41C1665 IC41LV1665
FAST PAGE MODE READ CYCLE
tRASP
tRP
RAS
tCSH tCAS tCRP tRCD tCP tCAS tCP tPC tRSH tCAS tCRP
UCAS/LCAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCAH tASC tCAH
ADDRESS
Row
Column
Column
Column
tRCS
WE
tAA tCAC tOE tCPA tAA tCAC tOE tCPA tAA tCAC tOE
OE
tRAC tCLZ
tOD tCLZ
OUT OUT
tOD tCLZ
OUT
tOD
I/O
Don't Care
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IC41C1665 IC41LV1665
FAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRASP
tRP
RAS
tCSH tCAS tCRP tRCD tCP tPRWC tCAS tCP tRSH tCAS tCRP
UCAS/LCAS
tAR tRAH tASR tRAD tASC tCAH tCPWD tASC tAR tCWL tRWD tAWD tCWD tCAH tCPWD tRAL tCAH tASC
ADDRESS
Row
Column
Column
tCWL tAWD tCWD
Column
tCWL tRWL tWP tAWD tCWD
tRCS
tWP
tWP
WE
tAA tCAC tOE tCAC tOE tAA tCAC tOE tAA
OE
tOEZ tOED tDH tDS tCLZ
OUT IN OUT IN
tRAC tCLZ
tOEZ tOED tDH tDS tCLZ
OUT
tOEZ tOED tDH tDS
IN
I/O0-I/O15
Don't Care
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IC41C1665 IC41LV1665
FAST PAGE MODE EARLY WRITE CYCLE
tRASP
tRP tRHCP tRSH tCAS tCP tCRP
RAS
tCSH tCAS tCRP tRCD tCP tPC tCAS
UCAS/LCAS
tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tWCS tWP tWCH tWCS tWP tCAH tASC tCAH
ADDRESS
Row
Column
Column
tCWL tWCH tWCS
Column
tCWL tWCH tWP
WE
tWCR
OE
tDHR tDS tDH tDS tDH tDS tDH
I/O0-I/O15
Valid DIN
Valid DIN
Valid DIN
Don't Care
AC WAVEFORMS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) RAS
tRC tRAS tRP
RAS
tCRP tRPC
UCAS/LCAS
tASR tRAH
ADDRESS I/O
Row Open
Row
Don't Care
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IC41C1665 IC41LV1665
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC tCP tCHR tCSR tRPC tCSR tCHR
UCAS/LCAS I/O Open
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS tRP tRAS
RAS
tCRP tRCD tRSH tCHR
UCAS/LCAS
tAR tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Row
Column
tAA tRAC tCAC tCLZ tOFF(2)
I/O
Open
tOE tORD
Valid Data
Open
tOD
OE
Don't Care
Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
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IC41C1665 IC41LV1665
ORDERING INFORMATION IC41C1665 Commercial Range: 0C to 70C
Speed(ns) 25 30 35 40 OrderPartNo. IC41C1665-25K IC41C1665-25T IC41C1665-30K IC41C1665-30T IC41C1665-35K IC41C1665-35T IC41C1665-40K IC41C1665-40T Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
Industrial Range: -40C to 85C
Speed(ns) 25 30 35 40 OrderPartNo. IC41C1665-25KI IC41C1665-25TI IC41C1665-30KI IC41C1665-30TI IC41C1665-35KI IC41C1665-35TI IC41C1665-40KI IC41C1665-40TI Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
ORDERING INFORMATION IC41LV1665 Commercial Range: 0C to 70C
Speed(ns) 25 30 35 40 OrderPartNo. IC41LV1665-25K IC41LV1665-25T IC41LV1665-30K IC41LV1665-30T IC41LV1665-35K IC41LV1665-35T IS41LV1665-40K IC41LV1665-40T Package 400mil SOJ 400mil T SOP-2 400mil SOJ 400mil T SOP-2 400mil SOJ 400mil T SOP-2 400mil SOJ 400mil T SOP-2
Industrial Range: -40C to 85C
Speed(ns) 25 30 35 40 OrderPartNo. IC41LV1665-25KI IC41LV1665-25TI IC41LV1665-30KI IC41LV1665-30TI IC41LV1665-35KI IC41LV1665-35TI IC41LV1665-40KI IC41LV1665-40TI Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
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Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
IC41C1665 IC41LV1665
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
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