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AL875 Data Sheets
(Version 1.01)
AL875
Amendments (Since June 29, 1999)
99.06.29 99.07.19 99.08.24 99.08.31 01.01.18
99.06.29 Updated the document to reflect version A-1 change. 99.07.19 Output drive current provided Added section 6.6 Clamping. ADTEST1 & ADTEST2 description modified. Remove "6.6 Clamping"
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Contents
1.0 Features___________________________________________________________________ 4 2.0 Applications________________________________________________________________ 4 3.0 General Description _________________________________________________________ 5 4.0 Pinout Diagrams ____________________________________________________________ 6 5.0 Pin Definition and Description ________________________________________________ 6 5.0 Pin Definition and Description ________________________________________________ 7 6.0 Functional Description______________________________________________________ 14
6.1 ADC inputs and conversion _______________________________________________________ 14 6.2 ADC outputs ___________________________________________________________________ 15 6.3 Clock Distribution_______________________________________________________________ 15 6.4 Automatic Positioning Control_____________________________________________________ 16 6.5 Clock Phase Test (for Jitter-reduction)______________________________________________ 18 6.6 I2C Programming _______________________________________________________________ 19
7.0 Electrical Characteristics ____________________________________________________ 22
7.1 Recommended Operating Conditions _______________________________________________ 22 7.2 DC Characteristics ______________________________________________________________ 22 7.3 AC Characteristics ______________________________________________________________ 22
8.0 AL875 Register Definition ___________________________________________________ 24
8.1 Index of Control Registers ________________________________________________________ 24 8.2 Register Description _____________________________________________________________ 25
9.0 Board Design and Layout Considerations_______________________________________ 31
9.1 Grounding _____________________________________________________________________ 31 9.2 Power Planes and Power Supply Decoupling _________________________________________ 31 9.3 Digital Signal and Clock Interconnect_______________________________________________ 31 9.4 Analog Signal Interconnect _______________________________________________________ 31
10.0 Mechanical Drawing ______________________________________________________ 32 11.0 Power Consumption _______________________________________________________ 33
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AL875
AL875
Triple High Speed, 8-bit Analog-to-Digital Converter
1.0 Features
* * * * * * * * * * High speed 8-bit ADC up to 110MHz conversion rate Support display resolution up to 1280x1024 at 60Hz refresh rate Low power dissipation (0.9W typical at 3.3V, 110MHz) 0.6~2.0V p-p analog input range 10k~1MHz CKREF locking range Full programmability via I2C interface Automatic screen position support Programmable clock phase adjustment TTL compatible digital inputs and outputs High impedance tri-state output * * * Power-down mode Single 3.3 volt power with 5 volt tolerant I/O 100-pin 14x20 mm PQFP package
2.0 Applications
* * * * LCD/PDP Monitors LCD Projectors Other Flat Panel Displays High-end Video/Graphics Processing
ADDR1/2 SDA SCL
CKEXT IIC Interface & Control Logic HSYNC Digital Logic Circuits VSYNC CK REF CP
RIN VRT VN VRB
T/H
ADC/R
Output Logic
ROUT<7:0>
GIN VRT VN VRB
T/H
ADC/G
Output Logic
GOUT<7:0>
BIN VRT VN VRB
T/H
ADC/B
Output Logic
BOUT<7:0>
/OE
AL875-01a functional block diagram.vsd
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3.0 General Description
The AL875 is a high-speed triple 8-bit monolithic analog-to-digital converter (ADC) designed for digitizing RGB graphics/video signal or other applications. Its 110 MHz conversion rate can support display resolution of up to 1280x1024 at 60Hz refresh rate. The AL875 accepts 0.6~2.0V analog input range without using pre-amplifiers which may reduce the overall S/N ratio. Digitized data is piped at the full clock rate to the 24-bit output port. The AL875 uses 3.3V power with 5V tolerant I/O and low power dissipation. The sampling clock is provided by an external clock source, usually a PLL, which multiplies the frequency of the input reference clock (usually a HSYNC signal) to generate the sampling clock. The AL875 provides a programmable PLL divider up to 4096. In addition, the input active horizontal and vertical starting and ending positions can be detected to ensure that the whole picture fits into the displayable region of the screen. Through an I2C interface, the AL875 is fully programmable to support various graphic resolutions.
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4.0 Pinout Diagrams
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CKAO GNDPLL CKBO CKADCO VDDPLL GND /OE PWRDN HSFB HSYNC INV CKEXT VSYNC CKREF VDD GNDAPLL CP NC VDDAPLL GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TESTIN3 TESTIN2 TESTIN1 TESTIN0 VDD VRBR VNR VRTR NC NC VDDAR RIN GNDAR VRBG VNG VRTG NC NC VDDAG GIN GNDAG VRBB VNB VRTB NC NC VDDAB BIN GNDAB ADTEST3
AL875
CKREFO VDDR ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 GNDR VDDG GOUT7 GOUT6 GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 GNDG VDDB BOUT7 BOUT6 BOUT5 BOUT4 BOUT3 BOUT2 BOUT1 BCLAMP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
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GCLAMP BOUT0 GNDB BOF GOF ROF /RESET TESTIN4 SCL GND VDD SDA NC NC ADTEST2 ADTEST1 ADDR2 ADDR1 RCLAMP CKINTEN AL875-03 pinout diagram
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5.0 Pin Definition and Description
Following is the pin definition of the AL875 with the corresponding TDA8752 pin assignment attached.
AL875 TESTIN3 TESTIN2 TESTIN1 TESTIN0 VDD VRBR VNR VRTR NC NC VDDAR RIN GNDAR VRBG VNG VRTG NC NC VDDAG GIN GNDAG VRBB VNB VRTB NC NC VDDAB BIN GNDAB Type IN (CMOS) IN (CMOS) IN (CMOS) IN (CMOS) POWER IN IN IN --POWER IN GROUND IN IN IN --POWER IN GROUND IN IN IN --POWER IN GROUND PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 DESCRIPTION Test signal input 3, can be left open. Test signal input 2, can be left open. Test signal input 1, can be left open. Test signal input 0, can be left open. Digital power supply Red channel bottom voltage reference Red channel comparator voltage reference Red channel top voltage reference Not connected Not connected Red channel analog power supply Red channel analog input Red channel analog ground Green channel bottom voltage reference Green channel comparator voltage reference Green channel top voltage reference Not connected Not connected Green channel analog power supply Green channel analog input Green channel analog ground Blue channel bottom voltage reference Blue channel comparator voltage reference Blue channel top voltage reference Not connected Not connected Blue channel analog power supply Blue channel analog input Blue channel analog ground TDA8752 n.c. DEC2 Vref DEC1 n.c. RAGC RBOT RGAINC RCLP RDEC VCCAR RIN AGNDR GAGC GBOT GGAINC GCLP GDEC VCCAG GIN AGNDG BAGC BBOT BGAINC BCLP BDEC VCCAB BIN AGNDB
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ADTEST3 CKINTEN
IN (CMOSu) IN (CMOSd)
30 31
Internal ADC test pin 3, to be pulled up. Test pin, pulled down for normal operation. Reserved for AL876 internal clock enable (LO: external clock, HI: internal PLL clock)
n.c. n.c.
RCLAMP ADDR1 ADDR2 ADTEST1 ADTEST2 NC NC SDA VDD GND SCL TESTIN4 /RESET ROF GOF BOF GNDB BOUT0 GCLAMP BCLAMP BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7 VDDB GNDG
OUT (CMOSt) IN (CMOSd) IN (CMOSd) IN (CMOSd) IN (CMOSd) --INOUT (CMOSsu) POWER GROUND IN (CMOSs) IN (CMOSd) IN (CMOSu) OUT (CMOS) OUT (CMOS) OUT (CMOS) GROUND OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER GROUND
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 60
Red channel clamp control output (NC) I2C address control input 1 I2C address control input 2 Internal ADC test pin 1, to be pulled down. Internal ADC test pin 2, to be pulled down. Not connected Not connected I2C serial data input/output Logic digital power supply Logic digital ground I2C serial clock input Test signal input 4, to be pulled up Reset pin (active LOW) Red channel ADC output overflow Green channel ADC output overflow Blue channel ADC output overflow Blue channel ADC output ground Blue channel ADC output bit 0 Green channel clamp control output (NC) Blue channel clamp control output (NC) Blue channel ADC output bit 1 Blue channel ADC output bit 2 Blue channel ADC output bit 3 Blue channel ADC output bit 4 Blue channel ADC output bit 5 Blue channel ADC output bit 6 Blue channel ADC output bit 7 Blue channel ADC output power supply Green channel ADC output ground
I2C/3W ADD1 ADD2 TCK TDO DIS SEN SDA VDDD VSSD SCL n.c. n.c. ROR GOR BOR OGNDB B0 n.c. n.c. B1 B2 B3 B4 B5 B6 B7 VCCOB OGNDG
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GOUT0 GOUT1 GOUT2 GOUT3 GOUT4 GOUT5 GOUT6 GOUT7 VDDG GNDR ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 VDDR CKREFO
OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER GROUND OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER OUT (CMOS)
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Green channel ADC output bit 0 Green channel ADC output bit 1 Green channel ADC output bit 2 Green channel ADC output bit 3 Green channel ADC output bit 4 Green channel ADC output bit 5 Green channel ADC output bit 6 Green channel ADC output bit 7 Green channel ADC output power supply Red channel ADC output ground Red channel ADC output bit 0 Red channel ADC output bit 1 Red channel ADC output bit 2 Red channel ADC output bit 3 Red channel ADC output bit 4 Red channel ADC output bit 5 Red channel ADC output bit 6 Red channel ADC output bit 7 Red channel ADC output power supply PLL Reference clock output with phase adjustment from CKREF. Usually used for external PLL reference input.
G0 G1 G2 G3 G4 G5 G6 G7 VCCOG OGNDR R0 R1 R2 R3 R4 R5 R6 R7 VCCOR CKREFO
CKAO GNDPLL CKBO CKADCO VDDPLL
OUT (CMOS) GROUND OUT (CMOS) OUT (CMOS) POWER
81 82 83 84 85
Output clock A (in phase with the internal digital logic clock) Digital ground. Reserved for AL876 PLL digital ground. Output clock B (with phase adjustment) ADC sampling clock (in phase with the ADC sampling clock) Digital power supply. Reserved for AL876 PLL digital power supply. Suggested to be separated from the other VDD pins with a ferrite bead for AL876 compatibility
CKAO OGNDPLL CKBO CKADCO VCCO(PLL)
GND
GROUND
86
Digital ground
DGND
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/OE PWRDN HSFB HSYNC INV CKEXT VSYNC CKREF VDD GNDAPLL CP
IN (CMOS) IN (CMOSd) OUT (CMOS) IN (CMOS) IN (CMOSd) IN (CMOS) IN (CMOS) IN (CMOS) POWER GROUND IN
87 88 89 90 91 92 93 94 95 96 97
Output enable (when OE is HIGH, the outputs are OE in HI-Z) Power-Down control (Active HIGH) external PLL Horizontal sync input The invert control of the ADC sampling clock External clock input Vertical sync input PLL reference clock input Digital power supply ground. Internal compensation pin. Reserved for AL876 PLL filter input. Please follow the reference design for external RC filter circuitry. CP HSYNC INV CKEXT COAST CKREF VCCD PWOFF Clock feedback divider output. Used with optional CLP
Analog ground. Reserved for AL876 PLL analog AGNDPLL
NC VDDAPLL
-POWER
98 99
Not connected Analog power supply. Reserved for AL876 PLL analog power supply. Suggested to be separated from the other VDD pins with a ferrite bead for AL876 compatibility
CZ VCCAPLL
GND
GROUND
100
Digital ground
n.c.
Remarks: * CMOSd: * CMOSs: * CMOSsu: * CMOSt: * CMOSu:
CMOS with internal pull-down CMOS with Schmitt trigger input CMOS with Schmitt trigger input and internal pull-up CMOS with tri-state output CMOS with internal pull-up
Note: Clamping feature is not supported in the chip.
Pin list grouped by functionality
Symbol Analog Input RIN IN 12 Red channel analog input Type PIN# DESCRIPTION
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GIN BIN VRTR VRTG VRTB VNR VNG VNB VRBR VRBG VRBB Digital Output ROUT[7:0] GOUT[7:0] BOUT[7:0] ROF GOF BOF RCLAMP GCLAMP BCLAMP HSYNC VSYNC CKREF CKEXT CP
IN IN IN IN IN IN IN IN IN IN IN OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOS) OUT (CMOS) OUT (CMOS) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) IN (CMOS) IN (CMOS) IN (CMOS) IN (CMOS) IN
20 28 8 16 24 7 15 23 6 14 22 78-71 68-61 58-52, 49 45 46 47 32 50 51 90 93 94 92 97
Green channel analog input Blue channel analog input Red channel top voltage reference Green channel top voltage reference Blue channel top voltage reference Red channel comparator voltage reference Green channel comparator voltage reference Blue channel comparator voltage reference Red channel bottom voltage reference Green channel bottom voltage reference Blue channel bottom voltage reference Red channel ADC output Green channel ADC output Blue channel ADC output Red channel ADC output overflow Green channel ADC output overflow Blue channel ADC output overflow Red channel clamp control output(NC) Green channel clamp control output(NC) Blue channel clamp control output(NC) Horizontal sync input Vertical sync input PLL reference clock input, which is usually HSYNC External clock input Internal compensation pin. Reserved for AL876 PLL filter input. Please follow the reference design for external RC filter circuitry.
Clock Pins (and reserved PLL pins for the AL876)
CKREFO
OUT (CMOS)
80
PLL Reference clock output with phase adjustment from CKREF. Usually used for external PLL reference input.
CKAO
OUT (CMOS)
81
Output clock A (in phase with internal digital
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logic clock) CKBO CKADCO HSFB
2
OUT (CMOS) OUT (CMOS) OUT (CMOS) IN (CMOSu) IN (CMOSd) IN (CMOSs) INOUT (CMOSsu) IN (CMOSd) IN (CMOSd)
83 84 89 44 88 42 39 34, 33 31
Output clock B, with phase adjustment ACD sampling clock output (in phase with ADC sampling clock) Clock divided by N for external PLL circuits Reset pin (active LOW) Power-Down control (Active HIGH) I2C serial clock input I2C serial data input/output I2C address control input Test pin, pulled down for normal operation. Reserved for AL876 internal clock enable (LO: external clock, HI: internal PLL clock)
Reset, I C and Configuration Pins /RESET PWRDN SCL SDA ADDR[2:1] CKINTEN
/OE INV Test Pins ADTEST3 ADTEST[2:1] TESTIN4 TESTIN[3:0] VDD VDDR VDDG VDDB VDDPLL VDDAR VDDAG VDDAB VDDAPLL
IN (CMOS) IN (CMOSd) IN (CMOSu) IN (CMOSd) IN (CMOSd) IN (CMOS) POWER POWER POWER POWER POWER POWER POWER POWER POWER
87 91 30 36, 35 43 1, 2, 3, 4 5, 40, 95 79 69 59 85 11 19 27 99
Output enable (when OE is HIGH, the outputs are in HI-Z) The invert control of the ADC sampling clock Internal ADC test pins 3 Internal ADC test pins 2~1 Test signal input 4 Test signal input 3~0 Digital power supply Red channel ADC output power supply Green channel ADC output power supply Blue channel ADC output power supply Digital power supply; reserved for AL876 PLL power supply Red channel analog power supply Green channel analog power supply Blue channel analog power supply Analog power supply. Reserved for PLL analog
Power, Ground and No Connect
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power supply GND GNDR GNDG GNDB GNDPLL GNDAR GNDAG GNDAB GNDAPLL NC GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND -41, 86, 100 70 60 48 82 13 21 29 96 Digital ground Red channel ADC output ground Green channel ADC output ground Blue channel ADC output ground Digital ground. Reserved for AL876 PLL digital ground Red channel analog ground Green channel analog ground Blue channel analog ground Analog ground. Reserved for AL876 PLL analog ground 9, 10, 17, 18, Not connected 25, 26, 37, 38, 98
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6.0 Functional Description
6.1 ADC inputs and conversion
The AL875 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 110 MSPS encode rate capability supports display resolutions of up to 1280 x 1024 at 60 Hz refresh rate with sufficient input bandwidth to acquire and digitize each pixel accurately. Each of the three analog input signals is input to a track-and-hold (T/H) circuit. This T/H captures the value of the input at sampling and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the sampling clock input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MSB Coarse Comparator Array and MSB Fine Comparator Array. The residue signal is then encoded by the Least Significant Bits (LSB) Coarse Comparator Array and LSB Fine Comparator Array to generate the four bits of LSB data. The comparator outputs are decoded and combined into the 8-bit output. Following is the clock diagram of the ADC (take R channel as an example):
CLOCK CONTROL & ERROR CORRECTION UNIT
MSB COARSE COMPARATOR ARRAY
MSB ENCODER
MSB DATA LATCH
ROUT [7:4]
RIN
LSB FINE COMPARATOR ARRAY
LSB ENCODER
LSB DATA LATCH
ROUT [3:0]
LSB FINE COMPARATOR ARRAY
LSB ENCODER
/OE
VRT VRB
REFERENCE SUPPLY
AL875-02 Block Diagram R channel
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6.2 ADC outputs
The ADC outputs are straight binary. An output enable pin (/OE, active LOW) toggles the output status between active and high-impedance (/OE = HIGH). The timing should be checked carefully if the output capacitive load is more than 10 pF.
6.3 Clock Distribution
The ADCs' sampling clock is usually from an external PLL clock source. The AL875 provides a PLL reference clock CKREFO (with phase adjustment) for the external PLL to generate the pixel clock to CKEXT pin as the ADC sampling clock. If the PLL requires a feedback signal, it is provided by the AL875 HSFB pin which signal is obtained from CKEXT divided by N. The PLL programming can be either by the external PLL chip (if available) or by the AL875 registers. In order to adjust the phase of the reference clock for optimal PLL quality, the CKREFO has programmable delay from the CKREF input, which is usually a HSYNC signal. Each programmable increment is equivalent to approximately 1.6ns. The CKREF delay adjustment diagram is as follows:
CKREF DELAY 4 PHASE A #0Ch<7:4> CKREFO-INV #02h<4> INV
CKREFO Input/Output pin
1 delay = 1.6ns Max. 15 delays = 24ns
AL875-07a Clock Reference Delay
The PLL-generated pixel clock is input from the CKEXT pin, then distributed to different internal or output pins with different delay for different purposes. The internal logic clock is available at CKAO pin. The delay-adjustable clock is available at CKBO, which programmability is useful for the setup/hold time optimization for the LCD controller or any chip that captures the output of the AL875. The ADC sampling clock is also available at CKADCO pin. The HSFB divider can be up to 4096. The clock distribution circuitry is illustrated in the following diagram:
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Internal logic clock CKAO CLOCK BUFFER CKREF DELAY 4 PHASE B (#0Ch<3:0>) CKADCO Inverter ADC sampling clock INV /N COUNTER 12 DIVIDER #0Ah<3:0> & #0Bh<7:0> CKBO
HSFB
Input/Output pin
AL875-07b Clock Distribution Circuitry
6.4 Automatic Positioning Control
The input horizontal and vertical starting and ending positions are detected to ensure that the whole picture fits into the displayable region of the screen. Two modes of position detection are provided: 1line detection and whole-frame detection. The 1-line detection can be performed by choosing any horizontal line (reg.#10h) or vertical line (reg.#19h), to check in what range the luma data is larger than the threshold value defined by DATA_TH (reg.#11h). When the threshold for the vertical line is different from the horizontal line, an additional register VDATA_TH (reg.#0Fh) can be used for vertical threshold and it is enabled by reg.#06h<7>. Any luma data lower than the threshold value is considered blanking period. The following drawing shows the related registers:
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Selected line for vertical positioning detection VCOLUMN, #19h HS_WIDTH, #18h<7:0> HSYNC VSYNC VDE_ST, #1Ah<2:0> & 1Bh<7:0> Selected line for horizontal positioning detection HNUMBER, #10h
INPUT ACTIVE REGION
HCNT_TOT, #16h<2:0> & #17h<7:0>
HDE_ST, #12h<2:0> & #13h<7:0>
HDE_END, #14h<2:0> & #15h<7:0>
VDE_END, #1Ch<2:0> & #1Dh<7:0>
Threshold = DATA_TH, #11h When horizontal and vertical thresholds are different: Threshold horizontal = DATA_TH, #11h Threshold vertical = VDATA_TH, #0Fh, Enabled by #06h<7>
AL875-09 One-line position detection
The whole frame detection scans the whole input video/graphics to check in which range the luma data is larger than the threshold value defined by DATA_TH or VDATA_TH. Any luma data lower than the threshold value is considered blanking period. Whole frame detection may be more accurate than 1-line detection. The following drawing shows the related registers:
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HSYNC VSYNC WVDE_ST, #25h<2:0> & #26h<7:0>
INPUT ACTIVE REGION
WHDE_ST, #21h<2:0> & #22h<7:0>
WHDE_END, #23h<2:0> & #24h<7:0>
WVDE_END, #27h<2:0> & #28h<7:0>
Threshold = DATA_TH, #11h When horizontal and vertical thresholds are different: Threshold horizontal = DATA_TH, #11h Threshold vertical = VDATA_TH, #0Fh, Enabled by #06h<7>
AL875-10 Whole-frame position detection
Details about these registers can be found in the Register Definition section.
6.5 Clock Phase Test (for Jitter-reduction)
The AL875 provides a proprietary clock phase test mode for jitter-reduction. Jitters may be experienced when sampling clock frequency and/or phase is not accurate. The AL875 can sample twice (with slightly different clock phases) on each odd or even pixel and count the total output value difference of the two phases (delay controlled by register #07h). This information (stored in registers #08h and #09h) is then available for the micro-controller to adjust the sampling clock frequency and phase for optimization. Additional reference can be found in the Register Definition section.
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AL875
6.6 I2C Programming
The AL875 I2C bus controls and monitors the status of the 3 ADCs, PLL and related registers. Two pins (ADD1 and ADD2) are used to set the I2C address. Therefore, up to four AL875s can be used in the same system and can be programmed by the same I2C bus. For detailed description of the AL875 registers, please refer to the Register Definition Section. The AL875 I2C programming interface follows the Philips standard and consists of the SCL (clock) and SDA (data) signals. Data can be written to or read from the AL875. For both read and write, each byte is transferred MSB first, and the SDA data bit is valid when the SCL is pulled high. The read/write command format is as follows: Write:
Read:
Following are the details: : Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. : Write Slave Address: 98h, 9Ah, 9Ch, or 9Eh : Read Slave Address: 99h, 9Bh, 9Dh, or 9Fh : Value of the AL875 register index. : Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL875 (slave) to pull down the SDA line during the acknowledge clock pulse. : Not Acknowledge stage
AL250-15 I2C drawing
SDA Data bit [1] or NA SCL
SDA Data bit [0] or A SCL
SDA START bit [S] SCL
STOP bit [P] SCL
SDA Not significant SCL
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AL875
The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL875 does not pull it down during this stage. : Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL875.
: Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH.
Suppose data F0h is to be written to register 0Fh using write slave address 98h, the timing is as follows:
Start Slave addr = 98h Ack Index = 0Fh Ack Data = F0h Ack Stop
SDA SCL
AL875-04 I2C Write timing
Suppose data is to be read from register 55h using read slave address 99h, the timing is as follows:
Start
Slave addr = 98h
Ack
Index = 55h
Ack
Stop Read slave addr = 99h NAck Start Ack Data read cycle Stop
SDA SCL
AL875-05 I2C Read timing
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AL875
More information on the AL875 functionality can be found in the Register Definition section.
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AL875
7.0 Electrical Characteristics
7.1 Recommended Operating Conditions
Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min +3.0 0 Max +3.6 +70 Unit V C
7.2 DC Characteristics
Parameter IDD P VIH VIL VOH VOL IO Supply current Power consumption Hi-level input voltage Lo-level input voltage Hi-level output voltage Lo-level output voltage Output current, stand data -0.5V7.3 AC Characteristics
Parameter Ci CK2 tiS tiH tr tf Input pin capacitance Duty factor (tCK2H/tCK2) Input data set-up time Input data hold time Input rise time Input fall time Vi = 0.6 to 2.6V Vi = 2.6 to 0.6V Test Conditions Min 40 5 3 Typ. Max 8 60 5 5 Unit PF % ns ns ns ns
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AL875
CL toH tPD SNR FC
Digital output load cap. Output hold time Propagation delay Signal-to-noise ratio Conversion speed CL = 15pF CL = 40pF
15 3 -
-
50 5 48 110
PF ns ns dB MHz
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AL875
8.0 AL875 Register Definition
The AL875 is powered up to a default state depending on the hardware mode-setting pins. Hardware configuration is disabled by setting SoftConfig (bit 4 of register 0x03) as 1, then software configuration is determined by the values of register 0x02, which is programmable by software. I2C Sub-address: ADDR2, ADDR1 pins LOW, LOW LOW, HIGH HIGH, LOW HIGH, HIGH I2C write address 98h 9Ah 9Ch 9Eh I2C read address 99h 9Bh 9Dh 9Fh
8.1 Index of Control Registers
The following is the summary of AL875 control registers
Register COMPANYID REVISION HWCONFIG GENERAL FAMILY STATUS Addr 00h 01h 02h 03h 04h 05h R/W R only Company ID R only Revision number R/W R/W Hardware configuration General register 1000 0111 87h Description Default 0100 0110 0000 0000 46h 00h Note
R only Chip family R Status register
Jitter Test Registers PHITEST DELTA DIFFH DIFFL 06h 07h 08h 09h R/W R/W Clock phase test Main and delay clock select UUU0 0000 00h 0000 0000
R only Difference count in a horizontal line (high) R only Difference count in a horizontal line (low)
PLL-Related Registers DIVIDERH DIVIDERL PHASE 0Ah 0Bh 0Ch R/W R/W R/W PLL divider high-byte PLL divider low-byte PLL phase delay control 0101 0011 0100 1000 0000 0000 53h 46h
One-line Auto-Positioning Registers HNUMBER 10h R/W Horizontal line number for HDE_ST, 0000 0110 Unit: 8 lines
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HDE_END detection DATA_TH HDE_STH HDE_STL HDE_ENDH HDE_ENDL HCNT_TOTH HCNT_TOTL HS_WIDTH VCOLUMN 11h 12h 13h 14h 15h 16h 17h 18h 19h R/W Data threshold for 0001 0000
6 * 8 = 48 20h
R only Horizontal active data start (high-byte) R only Horizontal active data start (low-byte) R only Horizontal active data end (high-byte) R only Horizontal active data end (low-byte) R only Detected horizontal total value (high-byte) R only Detected horizontal total value (low-byte) R only Detected horizontal sync width R/W Vertical column number for VDE_ST, VDE_END detection 0011 0111 Unit: 8 lines 37h * 8=440
VDE_STH VDE_STL VDE_ENDH VDE_ENDL
1Ah 1Bh 1Ch 1Dh
R only Vertical active data start (high-byte) R only Vertical active data start (low-byte) R only Vertical active data end (high-byte) R only Vertical active data end (low-byte)
Whole-frame Auto Positioning Registers WHDE_STH 21h R only Detected horizontal active start pixel position (high-byte) WHDE_STL 22h R only Detected horizontal active start pixel position (low-byte) WHDE_ENDH 23h R only Detected horizontal active end pixel position (high-byte) WHDE_ENDL 23h R only Detected horizontal active end pixel position (low-byte) WVDE_STH WVDE_STL WVDE_ENDH WVDE_ENDL 25h 26h 27h 28h R only Detected vertical active start line (high byte) R only Detected vertical active start line (low-byte) R only Detected vertical active end line (high-byte) R only Detected vertical active end line (low-byte)
Note: U - unused
8.2 Register Description
00h: Company ID (R) [COMPANYID] CompanyId <7:0> Company ID (46h)
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01h:
Revision (R) [REVISION] Revision <7:0> Revision number (00h) Hardware/Software Configuration (R/W) [HWCONFIG] Ckrefo_inv <4> Invert the phase of CKREFO (reference clock output) Inv <1> Invert the phase of CKADCO (ADC sampling clock) PwrDn <0> Power-Down mode (active high) Please refer to the Clock Distribution Circuitry diagram in section 6.3 for additional reference. General (R/W) [GENERAL] If SoftCinfig (0x03<4>) = 0, the values of hardware configuration pins are set/read. If SoftCinfig (0x03<4>) = 1, the values of software configuration registers are set/read. SoftConfig <4> Enable configuration defined by software configuration registers 0x02.
02h:
03h:
04h:
Chip Family (R) [FAMILY] Family <7:0> 10000111, AL875 series Status Register (R) [STATUS] VsPol_Det <7> Detected input Vsync polarity 1: positive, 0: negative. HsPol_Det <6> Detected input Hsync polarity 1: positive, 0: negative. Vsync <4> Input Vsync signal (without any processing) Hsync <3> Input Hsync signal (without any processing) Hspeed <2> Chips speed version; 1: high speed; 0: low speed.
05h:
Clock Phase Test (Jitter Test) 06h: Clock Phase Test (R/W) [PHITEST] ENV_TH <7> Enable VDATA_TH When ENV_TH = 0, DATA_TH (reg.#11h) applies for both horizontal and vertical threshold. When ENV_TH = 1, DATA_TH (reg.#11h) defines horizontal threshold only; vertical threshold is defined by VDATA_TH (reg.#0Fh). ADCDIFF_TH <6:5> Bits 5 and 4 of ADCDIFF_TH, threshold of data difference in clock phase test mode for auto phase detection PhiTest <4> Clock phase test enable
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ADCDIFF_TH
<3:0>
Bits 0~3 of ADCDIFF_TH, threshold of data difference in clock phase test mode for auto phase detection. Any difference lower than the threshold is considered as noise and can be disregarded.
07h:
Delayed Clock value select (R/W) [DELTA] Delta <3:0> Delayed clock phase-delay select This register defines the delay of the two ADC sampling clocks in jitter detection mode 1. Each delay is equivalent to 1.6ns. The detected value is stored in registers #08h and 09h. Number of pixels with significant data difference in jitter detection mode (R) [DIFFH] DIFF (9:8) <1:0> Number of pixels with significant data difference in jitter detection mode (R) [DIFFL] DIFF (7:0) <7:0> In this jitter detection mode, all odd pixels in a designated line are sampled and digitized twice. The total number of data pairs with data value difference higher than the specified threshold value is stored in these two registers. The delay of the two sampling clocks can be programmed by register #07h. Change of HSYNC and clock phase may result in different DIFF values. The lowest DIFF value usually indicates the optimized HSYNC and clock phase setting. Difference of first and last pixel position (R) [DIFF2H] DIFF2 (10:8) <2:0> Bits 11~8 of the difference of first and last pixel position Difference of first and last pixel position (R) [DIFF2L] DIFF2 (7:0) <7:0> Bits 7~0 of the difference of first and last pixel position In this jitter detection mode, position of the first active pixel of each line is compared with that of the previous line. When there is difference, this value is incremented by 1. Similarly, position of the last active pixel of each line is also compared with that of the previous line; when there is difference, this register values is incremented by 1. The total number is stored in DIFF2Hand DIFF2L.
08h:
09h:
0Dh:
0Eh:
PLL-Related Registers 0Ah: Divider High-byte (R/W) [DIVIDERH] DIVIDERH(11:8) <3:0> Bits 8~11 of the PLL divider Divider Low-byte (R/W) [DIVIDERL] DIVIDERL(7:0) <7:0> Bits 7~0 of the PLL divider This is the PLL divider number when a non-programmable genlock PLL such as ICS9173 is used.
0Bh:
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0Ch:
PLL phase delay control (R/W) [PHASE] PhaseA <7:4> Hsync phase delay adjustment PhaseB <3:0> CKBO phase delay adjustment Refer to the Internal PLL Block Diagram and AL875 Clock Distribution Circuitry in section 6.3 for additional reference.
One-line Automatic positioning: 0Fh: Vertical Data Threshold (R/W) [VDATA_TH] VData_TH <7:0> Luma (brightness) threshold value. This value is used to determine non-blanking pixel for vertical direction. Any pixel luma value less than this value is considered as blanking. . Hardware default value is 32 (20h). Vertical column used to detect vertical active start and end is defined by register #19h. This register is enabled by register #06h<7>. Horizontal Line Number for HDE_ST & HDE_END detection (R/W) [HNUMBER] HNumber <7:0> Horizontal line number for horizontal active start and end detection; refer to register #11h for additional reference. (unit: 8 lines) Hardware default value is 06h, which means 6 X 8 = 48 lines Data Threshold (R/W) [DATA_TH] Data_TH <7:0> Luma (brightness) threshold value. This value is used to determine non-blanking pixel for horizontal direction. Any pixel luma value less than this value is considered as blanking. . Hardware default value is 32 (20h). Horizontal line used to detect horizontal active start and end is defined by register #10h. This register is enabled by register #06h<7>. Horizontal Active Start High (R only) [HDE_STH] HDE_stH <2:0> Bits <10:8> of detected horizontal active start pixel position. Horizontal Active Start Low (R only) [HDE_STL] HDE_stL <7:0> Bits <7:0> of detected horizontal active start pixel position. (Unit: 1 pixel) Horizontal Active End High (R only) [HDE_ENDH] HDE_EndH <2:0> Bits <10:8> of detected horizontal active end-pixel position. Horizontal Active End Low (R only) [HDE_ENDL] HDE_EndL <7:0> Bits <7:0> of detected horizontal active end-pixel position. (Unit: 1 pixel) Detected H Total Value (R only) [HCNT_TOTH] HCNT_TOTH <2:0> Bits <10:8> of the detected horizontal total pixel number.
10h:
11h:
12h:
13h:
14h:
15h:
16h:
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17h:
Detected H Total Value Low (R only) [HCNT_TOTL] HCNT_TOTL <7:0> Bits <7:0> of the detected horizontal total pixel number. Detected Hsync Width (R only) [HS_WIDTH] HS_WIDTH <7:0> Indicate the detected horizontal sync pulse width. Vertical Column for VDESTART & VDEEND Detection (R/W) [VCOLUMN] VColumn <7:0> Vertical column number for vertical active start and end detection; refer to register #11h for additional reference. Hardware default value: 37h = 55 X 8 = 440. (Unit: 8 pixels) Vertical Active Start High (R only) [VDE_STH] VDE_StH <2:0> Bits <10:8> of detected vertical active start line. Vertical Active Start Low (R only) [VDE_STL] VDE_StL <7:0> Bits <7:0> of detected vertical active start line. (Unit: 1 line) Vertical Active End High (R only) [VDEENDH] VDE_EndH <2:0> Bits <10:8> of detected vertical active end line. Vertical Active End Low (R only) [VDE_ENDL] VDE_EndL <7:0> Bits <7:0> of detected vertical active end line. (Unit: 1 line)
18h:
19h:
1Ah:
1Bh:
1Ch:
1Dh:
Whole-frame Automatic positioning: 21h: Horizontal Active Start High (R only) [WHDE_STH] WHDE_STH <2:0> Bits <10:8> of detected horizontal active start pixel position. Horizontal Active Start Low (R only) [WHDE_STL] WHDE_STL <7:0> Bits <7:0> of detected horizontal active start pixel position. (Unit: 1 pixel) Horizontal Active End High (R only) [WHDE_ENDH] WHDE_ENDH<2:0> Bits <10:8> of detected horizontal active end pixel position. Horizontal Active End Low (R only) [WHDE_ENDL] WHDE_ENDL <7:0> Bits <7:0> of detected horizontal active end pixel position (Unit: 1 pixel) Vertical Active Start High (R only) [WVDE_STH] WVDE_STH <2:0> Bits <10:8> of detected vertical active start line Vertical Active Start Low (R only) [WVDE_STL] WVDE_STL <7:0> Bits <7:0> of detected vertical active start line (Unit: 1 line) Vertical Active End High (R only) [WVDE_ENDH] WVDE_ENDH<2:0> Bits <10:8> of detected vertical active end line
22h:
23h:
24h:
25h:
26h:
27h:
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28h:
Vertical Active End Low (R only) [WVDE_ENDL] WVDE_ENDL <7:0> Bits <7:0> of detected vertical active end line (Unit: 1 line)
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9.0 Board Design and Layout Considerations
The AL875 contains both precision analog and high-speed digital circuitry. Noise coupling from digital circuits to analog circuits may result in poor video quality. The layout should be optimized for lowest noise on the power and ground planes by shielding the digital circuitry and providing good decoupling.
9.1 Grounding
Analog and digital circuits are separated within the AL875 chip. To minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL875 is recommended. All the connections to the ground plane should have very short leads. The ground plane should be solid, not cross-hatched.
9.2 Power Planes and Power Supply Decoupling
The analog portion of the AL875 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (AVDD). The analog power plane should be connected to the digital power plane (DVDD) at a single point through a low resistance ferrite bead. Additionally, in order to minimize cross interference, the analog power planes of R, G, B and PLL should also be separated with low resistance ferrite beads. Power supply connection pins should be individually decoupled. For best results, use 0.1F ceramic chip capacitors. Lead lengths should be minimized. The power pins should be connected to the bypass capacitors before being connected to the power planes. 22F capacitors should also be used between the AL875 power planes and the ground planes to control low-frequency power ripple.
9.3 Digital Signal and Clock Interconnect
Digital signals to the AL875 should be isolated as much as possible from the analog outputs and other analog circuitry. The high frequency clock reference or crystal should be handled carefully because jitters and noise on the clock will degrade the video performance. Keep the clock paths to the decoder as short as possible to reduce noise pickup.
9.4 Analog Signal Interconnect
The AL875 should be located closely to the output connectors to minimize noise and reflections. Keep the critical analog traces as short and wide as possible (20~30 mil). Digital signals, especially pixel clocks and data signals should not overlap any of the analog signal circuitry and should be kept as far apart as possible. The AL875 and the decoder IC should have no inputs left floating.
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AL875
10.0 Mechanical Drawing
AL875: 14mm x 20mm 100-pin 0.65-pitch PQFP package
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AL875
11.0 Power Consumption
The AL875 works at single 3.3V power. The following table shows the current consumption of the AL875 at different operating frequencies. Frequency 110MHz 90MHz 65MHz 40MHz Current 135 mA (typ.) 115 mA (typ.) 95 mA (typ.) 65 mA (typ.)
AL875@3.3V AL875@3.3V AL875@3.3V AL875@3.3V
For more information about the AL875 or other AverLogic products, please contact your local authorized representatives, visit our website, or contact us directly.
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CONTACT INFORMATION
AverLogic Technologies, Inc. 6840 Via Del Oro Suite 160 San Jose, CA 95119 USA
Tel Fax E-mail URL
: 1 408 361-0400 : 1 408 361-0404 : sales@averlogic.com : www.averlogic.com

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