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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1818A
Advance Information
104 x 65 STN LCD Segment / Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com Rev 1.2 P 1/47 SSD1818A Mar 2004 Copyright 2004 Solomon Systech Limited
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ....................................................................................................................... 5 2. FEATURES ............................................................................................................................................... 5 3. ORDERING INFORMATION .................................................................................................................... 5 4. BLOCK DIAGRAM ................................................................................................................................... 6 5. DIE PAD ARRANGEMENT ...................................................................................................................... 7 6. PIN DESCRIPTION................................................................................................................................. 10 7. FUNCTIONAL BLOCK DESCRIPTIONS............................................................................................... 15 8. COMMAND TABLE ................................................................................................................................ 23 9. COMMAND DESCRIPTIONS ................................................................................................................. 28 10. MAXIMUM RATINGS ........................................................................................................................... 34 11. DC CHARACTERISTICS...................................................................................................................... 35 12. AC CHARACTERISTICS...................................................................................................................... 37 13. APPLICATION EXAMPLES ................................................................................................................. 41 14. INITIALIZATION ROUTINE .................................................................................................................. 43 15. TAB DRAWING .................................................................................................................................... 44
Solomon Systech
Mar 2004
P 2/47
Rev 1.2
SSD1818A
TABLE OF TABLES
Table 1 - Ordering Information .................................................................................................................. 5 Table 2 - SSD1818A Series Bump Die Pad Coordinates (Bump center) ............................................... 8 Table 3 - Example of ROW pin assignment for programmable MUX of SSD1818A ........................... 14 Table 4 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h.. 20 Table 5 - Write Command Table (D/ C =0, R/ W ( WR )=0, E( RD )=1) ...................................................... 23 Table 6 - Extended Command Table (D/ C = 0,R/W ( WR ) = 0,E=1( RD = 1) unless specific setting is stated) ................................................................................................................................................. 25 Table 7 - Automatic Address Increment ................................................................................................. 27 Table 8 - ROW pin assignment for COM signals for SSD1818A in an 18 MUX display (including icon line) without/with 7 lines display offset towards ROW0........................................................ 33 Table 9 - Maximum Ratings (Voltage Referenced to VSS) ..................................................................... 34 Table 10 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C)........................................................................................................................ 35 Table 11 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C)........................................................................................................................ 37 Table 12 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C) .................. 38 Table 13 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C) .................. 39 Table 14 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C) .................. 40
SSD1818A
Rev 1.2
P 3/47
Mar 2004
Solomon Systech
TABLE OF FIGURES
Figure 1 - SSD1818A Block Diagram......................................................................................................... 6 Figure 2 - SSD1818A Pin Assignment....................................................................................................... 7 Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read........................................ 15 Figure 4 - Oscillator .................................................................................................................................. 16 Figure 5 - DC-DC Converter Configurations........................................................................................... 17 Figure 6 - Voltage Regulator Output for different Gain/Contrast Settings.......................................... 18 Figure 7 - LCD Driving Waveform for Displaying "0" ............................................................................ 22 Figure 8 - Contrast Control Flow Set Segment Re-map........................................................................ 28 Figure 9 - 6800-series MPU Parallel Interface Characteristics ............................................................. 38 Figure 10 - 8080-series MPU Parallel Interface Characteristics ........................................................... 39 Figure 11 - Serial Interface Characteristics ............................................................................................ 40 Figure 12 - Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with: external VEE, internal regulator, divider mode enabled (Command: 2B), 6800-series MPU parallel interface, internal oscillator and master mode ................................................................. 41 Figure 13 - Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with all internal power control circuit enabled, 6800-series MPU parallel interface, internal oscillator and master mode. .............................................................................................................................. 42 Figure 14 - SSD1818AT Copper View Layout ......................................................................................... 44 Figure 15 - SSD1818AT Pin Assignment ................................................................................................ 46
Solomon Systech
Mar 2004
P 4/47
Rev 1.2
SSD1818A
1. GENERAL DESCRIPTION
SSD1818A is a single-chip CMOS LCD driver with controllers for dot-matrix graphic liquid crystal display system. It consists of 169 high-voltage driving outputs for driving maximum 104 Segments, 64 Commons and 1 icon line. SSD1818A consists of 104 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from common MCU through 8-bit Parallel or 4-wire Serial Interface. 6800-series, 8080-series compatible Parallel Interface and Serial Peripheral Interface can be selected by hardware configuration. SSD1818A embeds DC-DC Converter with booster capacitors, On-Chip Oscillator and Bias Divider so as to reduce the number of external components. With the advanced design for low power consumption, stable LCD operating voltage and flexible die layout, SSD1818A is suitable for any portable battery-driven applications requiring long operation period with compact size.
2. FEATURES
Maximum display size: 104 x 64 + 1 Icon Line Single Supply Operation, 2.4 V - 3.5V Minimum -12.0V LCD Driving Output Voltage Low Current Sleep Mode On-Chip Voltage Generator or External LCD Driving Power Supply Selectable 2X / 3X / 4X/ 5X On-Chip DC-DC Converter On-Chip Oscillator On-Chip Bias Divider Programmable bias ratio [1/4-1/9] 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface On-Chip 104 X 65 Graphic Display Data RAM Row Re-mapping and Column Re-mapping Vertical Scrolling Display Offset Control 64 Level Internal Contrast & External Contrast Control Programmable LCD Driving Voltage Temperature Coefficients Programmable MUX ratio [2-64 MUX] (Partial display mode) Available in Gold Bump Die
3. ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number SSD1818AZ SSD1818ATR1 SEG 104 96 COM 64 + 1 54 Package Form Gold Bump Die TAB Reference Figure 2 on page 7 Figure 14 on page 44 Remark -
SSD1818A
Rev 1.2
P 5/47
Mar 2004
Solomon Systech
4. BLOCK DIAGRAM
ICONS ROW0 ~ ROW63 SEG0 ~SEG103
HV Buffer Cell Level Shifter
Level Selector
V L6 V L5 V L4 V L3 V L2 V DD
Display Data Latch
MSTAT M
DOF M/S
Display Timing Generator
VF
LCD Driving Voltage Generator 2X/ 3X/ 4X/ 5X DC/ DC Converter, Voltage Regulator, Contrast Control, Bias Divider Temperature Compensation
VEE VSS1 C4N C3N C 1P C 1N C 2N C 2P IRS
CL CLS
Oscillator
GDDRAM 104 X 65 Bits VSS VDD C0 C1 Command Interface Parallel / Serial Interface Command Decoder
SPI
CS1
CS2
RES D/ C
R/ W
E C68/ 80 P/ S
D7 D 6 D 5 [SDA] [SCK]
D4
D3
D2
D1
D0
( WR ) ( RD )
Figure 1 - SSD1818A Block Diagram
Solomon Systech
Mar 2004
P 6/47
Rev 1.2
SSD1818A
5. DIE PAD ARRANGEMENT
26.25 26.25 26.25 26.25 26.25 26.25
ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31
26.25
26.25
NC
NC
ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35
126 125 104 103
(2755.725, 237.475)
SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43
277
(-3878.7, 237.475)
254 255
276
1
T2 T1 T0 /SPI VSS IRS VDD C1 VSS C0 VDD P/S C68/80 VSS CLS M/S VDD VF VL6 VL6 VL6 VL5 VL5 VL5 VL4 VL4 VL4 VEE VL3 VL3 VL3 VL2 VL2 VL2 VEE C4N C4N C4N C2P C2P C2P C2N C2N C2N VEE C1N C1N C1N C1P C1P C1P C3N C3N C3N TEST2 VEE VEE VEE VEE VEE VEE VSS1 VSS1 VSS1 VSS1 VSS1 VSS VSS VSS TEST1 TEST0 VDD VDD VDD VDD VDD VDD VDD D7 D6 D5 D4 D3 D2 D1 D0 VDD E/RD R/W VSS D/C VEE VEE /RES VDD CS2 /CS1 VSS /DOF CL M MSTAT
X
Center (-3876.1625, 323.6625)
26.25 26.25
X
Center (2751.9625, 323.6625)
52.5
8.75
35
8.75
35
Center: 2751.9625, 323.6625
X
(-3878.7, 237.475)
X
(2755.725, 237.475)
Note: 1. The gold bumps face up in this diagram 2. All dimensions in m and (0,0) is the center of the chip Die Size: Die Thickness: Bump Pitch: Bump Height: Tolerance: 8.66 mm X 1.48 mm 550 +/- 25 um 60 um [Min] Nominal 18 um < 3 um within die
Gold Bump Alignment Mark This alignment mark contains gold bump for IC bumping process alignment and IC identifications. No conductive tracks should be laid underneath this mark to avoid short circuit.
Center: -3876.1625, 323.6625
Center: -3875.55, 149.275 Size: 88.2 x 88.2
16.8 13.65 12.6
16.8 13.65 12.6 73.5
PIN #1
Center (3875.55, 149.275)
ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW62 ICONS
NC
NC
73.5
Figure 2 - SSD1818A Pin Assignment
SSD1818A
Rev 1.2
P 7/47
Mar 2004
Solomon Systech
Table 2 - SSD1818A Series Bump Die Pad Coordinates (Bump center)
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal MSTAT M CL
DOF VSS
X-pos -3873.80 -3797.50 -3721.20 -3644.90 -3568.60 -3492.30 -3416.00 -3339.70 -3263.40 -3178.35 -3102.05 -3017.00 -2940.70 -2864.40 -2788.10 -2711.80 -2635.50 -2557.63 -2481.33 -2403.10 -2325.23 -2248.93 -2172.63 -2096.33 -2020.03 -1943.73 -1867.43 -1791.13 -1714.83 -1638.53 -1562.23 -1485.93 -1409.63 -1333.33 -1257.03 -1180.73 -1095.68 -1019.38 -943.08 -866.78 -790.48 -714.18 -637.88 -561.58 -485.28 -408.98 -332.68 -256.38 -180.08 -103.78
Y-pos -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35
Pad # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Signal C3N C1P C1P C1P C1N C1N C1N VEE C2N C2N C2N C2P C2P C2P C4N C4N C4N VEE VL2 VL2 VL2 VL3 VL3 VL3 VEE VL4 VL4 VL4 VL5 VL5 VL5 VL6 VL6 VL6 VF VDD M/ S CLS VSS C68/ 80 P/ S VDD C0 VSS C1 VDD IRS VSS
X-pos -27.48 48.83 125.13 201.43 277.73 354.03 430.33 506.63 582.93 659.23 735.53 811.83 888.13 964.43 1040.73 1117.03 1193.33 1269.63 1345.93 1422.23 1498.53 1574.83 1651.13 1727.43 1803.73 1880.03 1956.33 2032.63 2108.93 2185.23 2261.53 2337.83 2414.13 2490.60 2566.73 2651.78 2728.08 2804.38 2880.68 2956.98 3033.28 3109.58 3185.88 3262.18 3338.48 3414.78 3491.08 3567.38 3643.68 3723.65
Y-pos -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35 -581.35
Pad # 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Signal T1 T2 NC ROW31 ROW30 ROW29 ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20 ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 NC ROW10 ROW9 ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 ICONS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12
X-pos 3799.95 3876.25 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 4178.48 3834.60 3774.40 3714.20 3654.00 3593.80 3533.60 3473.40 3413.20 3353.00 3292.80 3232.60 3172.40 3112.20 3052.00 2991.80 2931.60 2871.40 2811.20 2751.00 2690.80 2630.60 2570.40 2510.20 2450.00 2389.80
Y-pos -581.35 -581.35 -655.03 -594.83 -534.63 -474.43 -414.23 -354.03 -293.83 -233.63 -173.43 -113.23 -53.03 7.18 67.38 127.58 187.78 247.98 308.18 368.38 428.58 488.78 548.98 609.18 663.25 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83
CS
CS2 VDD
RES
VEE VEE D/ C VSS R/ W E/ RD VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VDD VDD VDD VDD TEST0 TEST1 VSS VSS VSS VSS1 VSS1 VSS1 VSS1 VSS1 VEE VEE VEE VEE VEE VEE TEST2 C3N C3N
SPI
T0
Solomon Systech
Mar 2004
P 8/47
Rev 1.2
SSD1818A
Pad # 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Signal SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62
X-pos 2329.60 2269.40 2209.20 2149.00 2088.80 2028.60 1968.40 1908.20 1848.00 1787.80 1727.60 1667.40 1607.20 1547.00 1486.80 1426.60 1366.40 1306.20 1246.00 1185.80 1125.60 1065.40 1005.20 945.00 884.80 824.60 764.40 704.20 644.00 583.80 523.60 463.40 403.20 343.00 282.80 222.60 162.40 102.20 42.00 -18.20 -78.40 -138.60 -198.80 -259.00 -319.20 -379.40 -439.60 -499.80 -560.00 -620.20
Y-pos 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83
Pad # 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Signal SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40
X-pos -680.40 -740.60 -800.80 -861.00 -921.20 -981.40 -1041.60 -1101.80 -1162.00 -1222.20 -1282.40 -1342.60 -1402.80 -1463.00 -1523.20 -1583.40 -1643.60 -1703.80 -1764.00 -1824.20 -1884.40 -1944.60 -2004.80 -2065.00 -2125.20 -2185.40 -2245.60 -2305.80 -2366.00 -2426.20 -2486.40 -2546.60 -2606.80 -2667.00 -2727.20 -2787.40 -2847.60 -2907.80 -2968.00 -3028.20 -3088.40 -3148.60 -3208.80 -3269.00 -3329.20 -3389.40 -3449.60 -3509.80 -3570.00 -3630.20
Y-pos 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83 587.83
Pad # 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277
Signal ROW41 ROW42 ROW43 NC ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ICONS NC NC
X-pos -3690.40 -3750.60 -3810.80 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -4178.48 -3875.55
Y-pos 587.83 587.83 587.83 663.25 609.18 548.98 488.78 428.58 368.38 308.18 247.98 187.78 127.58 67.38 7.18 -53.03 -113.23 -173.43 -233.63 -293.83 -354.03 -414.23 -474.43 -534.63 -594.83 -655.03 149.28
Bump Size PAD# 1 - 102 103 - 124 125 126 - 253 254 255 - 276 277
X [um] 50.05 66.675 66.675 40.95 66.675 66.675 88.2
Y [um] 50.05 40.95 28.7 66.675 28.7 40.95 88.2
SSD1818A
Rev 1.2
P 9/47
Mar 2004
Solomon Systech
6. PIN DESCRIPTION
MSTAT
This pin is the static indicator driving output. It is only active in master operation. The frame signal output pin, M, should be used as the back plane signal for the static indicator. The duration of overlapping can be programmable. This pin, MSTAT, becomes high impedance if the chip is operating in slave mode. Please see the Extended Command Table for reference.
M
This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices. In slave mode, the pin receives frame signal from the master device.
CL
This pin is the system clock input/output. When the internal oscillator is enabled (CLS pin pulled high), and the master mode is enabled (M/ S pin pulled high), this pin supplies system clock signal to the slave device. When internal oscillator is disabled and the slave mode is enabled, the pin receives system clock signal from the master device or external clock source.
DOF This pin is the display blanking signal control pin. In master mode, this pin supplies "display on" or "display off" signal (blanking signal) to slave devices. In slave mode, this pin receives "display on" or "display off" signal from the master device.
CS1 , CS2
These pins are the chip select inputs. The chip is enabled for MCU communication only when CS1 is pulled low and CS2 is pulled high.
RES
This pin is the reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse width for completing the reset procedure is 5 - 10us.
D/ C
This pin is Data/Command control pin. When the pin is pulled high, the input at D7-D0 is treated as display data. When the pin is pulled low, the input at D7-D0 will be transferred to the command register. For detailed relationship with other MCU interface signals, please refer to the Timing Characteristics Diagrams.
R/ W ( WR )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write (R/ W ) selection input. Read mode will be carried out when this pin is pulled high and write mode when this pin is pulled low. When 8080 interface mode is selected, this pin will be the Write ( WR ) input. Data write operation is initiated when this pin is pulled low and the chip is selected.
E( RD )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/ write operation is initiated when this pin is pulled high and the chip is selected. When 8080 interface mode is selected, this pin receives the Read ( RD ) signal. Data read operation is initiated when this pin is pulled low and the chip is selected.
Solomon Systech Mar 2004 P 10/47 Rev 1.2 SSD1818A
D7-D0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the LSB. When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK).
VDD
These pins are the Chip's Power Supply pins. These pins are also act as the reference for the DC-DC Converter output and the LCD driving voltages.
VSS
These pins are the grounding of the chip. They are also act as the reference for the logic pins.
VSS1
These pins are the inputs for internal DC-DC converter. The voltage of generated, VEE, equals to the multiple factors times the potential different between these pins, VSS1, and VDD. The multiple factors, 2X, 3X, 4X or 5X are selected by different connections of the external capacitors. All voltage levels are referenced to VDD. Note: the potential of Vss1 at this input pin must lower than or equal to VSS.
VEE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. The internal DC-DC converter is turned on when the internal voltage booster option is enabled. Please refer to the Set Power Control Register command for detail description. When using internal DC-DC converter as voltage generator, voltage at this pin is used for internal referencing only. It CANNOT be used for driving external circuitry.
C1P, C1N, C2N, C2P C3N and C4N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or 5X. For detailed connections, please refer to the voltage converter section in the functional block description.
VL2, VL3, VL4 and VL5
These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are referenced to VDD. The voltage levels can be supplied externally or generated by the internal bias divider. The bias divider is turned on when the output op-amp buffers are enabled. Please refer to the Set Power Control Register command for detail description. The voltage potential relationship of these pins are given as: VDD > VL2 > VL3 > VL4 > VL5 > VL6 In addition, assume the bias factor is known as a, VL2 - VDD = 1/a * (VL6 - VDD) VL3 - VDD = 2/a * (VL6 - VDD) VL4 - VDD = (a-2)/a * (VL6 - VDD) VL5 - VDD = (a-1)/a * (VL6 - VDD)
VL6
This pin outputs the most negative LCD driving voltage level. The VL6 can be supplied externally or generated by the internal regulator. Please refer to the Set Power Control Register command for detail description.
SSD1818A
Rev 1.2
P 11/47
Mar 2004
Solomon Systech
M/ S
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected. CL, M, MSTAT and DOF signals will be the output pins for slave devices. When this pin is pulled low, slave mode is selected. CL, M, DOF are input pins getting signal from master device. The state of MSTAT will be high impedance.
VF
This pin is the input of the built-in voltage regulator for generating VL6. When external resistor network is selected (IRS pulled low) to generate the LCD driving level, VL6, two external resistors should be added. R1 should be connected between VDD and VF. R2 should be connected between VF and VL6.
CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled. The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external clock source must be fed into the CL pin.
C68/ 80
This pin is the MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is selected. When the pin is pulled low, 8080 series interface is selected. If Serial Interface is selected (P/ S pulled low), the setting of this pin is ignored. The C68/ 80 pin must be connected to a known logic state (either high or low).
P/ S
This pin is the serial/parallel interface selection input. When this pin is pulled high, parallel interface mode is selected. When this pin is pulled low, serial interface will be selected. Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/ W ( WR ), E/( RD ) are recommended to connect to Vss. Note2: Read back operation is only available in parallel mode.
C1, C0
These pins are the Chip Mode Selection input. The chip mode is determined by multiplex ratio. Altogether there are four chip modes. Please see the following list for reference. C1 C0 Chip Mode 0 0 48 MUX Mode 0 1 54 MUX Mode 1 0 32 MUX Mode 1 1 64 MUX Mode
IRS
This is the input pin to enable the internal resistors network for the voltage regulator. When this pin is pulled high, the internal feedback resistors of the internal regulator for generating VL6 will be enabled. When it is pulled low, external resistors, R1 should be connected to VDD and VF. R2 should be connected between VF and VL6, respectively.
Solomon Systech
Mar 2004
P 12/47
Rev 1.2
SSD1818A
SPI This is the input pin to enable the circuitry for providing serial interface. This pin must be connected to low at any circumstances. When the SPI pin and the P/ S , selection input are both pulled low, the serial interface is enabled. When the SPI pin is pulled low and the P/ S selection input is pulled high, the parallel interface is enabled.
NC/TEST0 - TEST2/T0 - T2
These are the No Connection pins. These pins should be left open individually. Remarks: These pins should not be connected together.
ROW0 - ROW63
These pins provide the Common driving signals to the LCD panel. Please refer to the Table 3 on Page 11 for the COM signal mapping.
SEG0 - SEG103
These pins provide the LCD segment driving signals. The output voltage level of these pins is VDD during sleep mode or standby mode.
ICONS
There are two ICONS pins (pin137 and 275) on the chip. Both pins output exactly the same signal. The reason for duplicating these pins is to enhance the flexibility of the LCD layout.
SSD1818A
Rev 1.2
P 13/47
Mar 2004
Solomon Systech
Table 3 - Example of ROW pin assignment for programmable MUX of SSD1818A
ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 48 MUX Mode NC NC NC NC NC NC NC NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 NC NC NC NC NC NC NC NC 54 MUX Mode NC NC NC NC NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 NC NC NC NC NC 32 MUX Mode NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 64 MUX Mode COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
Note: NC - Row pin will output non-selected COM signal
Solomon Systech
Mar 2004
P 14/47
Rev 1.2
SSD1818A
7. FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input signal is interpreted as data or command. Input is directed to this module based on the input of the D/ C pin. If the D/ C pin is high, input is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D7-D0 is interpreted as a Command. It will be decoded and written to the corresponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), R/ W ( WR ), D/ C , E/( RD ), CS1 and CS2. Read cycle R/ W ( WR ) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3.
R/W(WR )
E(RD)
data bus
N write column address dummy read
n data read1
n+1 data read 2
n+2 data read 3
Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read
Write cycle R/ W ( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the D/ C input. The E( RD ) input serves as data latch signal (clock) when high, provided that CS1 is pulled low and the CS2 is pulled high respectively. Please refer to Figure 9 on Page 38 for Parallel Interface Timing Diagram of 6800-series microprocessors.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D7-D0), E/( RD ), R/ W ( WR ), D/ C , CS1 and CS2.
SSD1818A
Rev 1.2
P 15/47
Mar 2004
Solomon Systech
Read cycle
E( RD ) input serves as data read latch signal (clock) when low, provided that CS1 is pulled low and the CS2 is pulled high respectively. The D/ C signal determines whether the receiving signal is a display data read or a status register read signal. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
Write cycle
R/ W ( WR ) input serves as data write latch signal (clock) when high, provided that CS1 and CS2 are low and high respectively. The D/ C signal determines whether the receiving signal is a display data write or a command register write signal. Please refer to Figure 10 on Page 39 for Parallel Interface Timing Diagram of 8080-series microprocessor.
MPU Serial interface
The serial interface consists of serial clock SCK (D6), serial data SDA (D7), D/ C , CS1 and CS2. Input to SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D7, D6,... D0. D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock.
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable
enable Oscillation Circuit
enable Buffer
(CL)
Internal resistor
OSC1 OSC2
Figure 4 - Oscillator
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for display driving output. With reference to VDD, it takes a single supply input, VSS, and generates necessary voltage levels. This block consists of: 1. 2X, 3X, 4X and 5X DC-DC voltage converter The built-in DC-DC voltage converter is used to generate the negative voltage with reference to VDD from the voltage input (VSS1). For SSD1818A, it is possible to produce 2X, 3X, 4X or 5X boosting from the potential different between VSS1 - VDD. Detailed configurations of the DC-DC converter for different boosting multiples are given in Figure 5.
Solomon Systech
Mar 2004
P 16/47
Rev 1.2
SSD1818A
SSD1818A
VSS1 VEE C3N
C1P
C1N
C2N
C2P
C4N
+ C1
5X Boosting Configuration
+ C1
+ C1
+ C1
+ C1
SSD1818A
VSS1 VEE C3N C1P C1N C2N C2P C4N
+
C1
C1 +
+ C1
+ C1
4X Boosting Configuration
SSD1818A
VSS1 VEE C3N C1P C1N C2N C2P C4N
+
C1
+
C1
+ C1
3X Boosting Configuration
SSD1818A
VSS1 VEE C3N C1P C1N C2N C2P C4N
+
C1
+ C1
2X Boosting Configuration
Remarks: 1. C1= 0.47 - 4.7uF 2. Boosting input from VSS1 3. VSS1 should be lower potential than or equal to VSS 4. All voltages are referenced to VDD
Figure 5 - DC-DC Converter Configurations 2. Voltage Regulator (Voltages referenced to VDD) Internal (IRS pin = H) feedback gain can control the LCD driving contrast curves. If internal resistor network is enabled, eight settings can be selected through software command. If external control is selected, external resistors are connected between VDD and VF (R1), and between VF and VL6 (R2). 3. Contrast Control (Voltage referenced to VDD) Software control of the 64-contrast voltage levels at each voltage regulator feedback gain. The equation of calculating the LCD driving voltage is given as: VL6 -VDD = Gain * [1 + (18 + )] * Vref 81
stands for the contrast set (0 to 63)
SSD1818A
Rev 1.2
P 17/47
Mar 2004
Solomon Systech
Gain = (1 + Rb/Ra), the reference value is shown in table 5. Register ratio Thermal Gradient o D2 D1 D0 = -0.07 %/ C 000 2.92 001 3.40 010 3.89 011 4.37 100 4.85 101 5.23 110 5.72 111 6.19 Gain value at different register ratio and thermal gradient settings Vref is a fixed IC-internal voltage supply and its voltage at room temperature (25 C) is shown in Table 6 for reference. Type Thermal Vref Gradient o TC 0 -0.07 %/ C -1.090V TC 2 TC 4 TC 7 -0.13 %/ C -0.26 %/ C -0.29 %/ C
o o o o o
-1.089V -1.065V -1.071V
External resistor -0.07 %/ C -1.090V gain mode [Gain = 5.00] @ TC0 Vref values at different thermal gradient settings The voltage regulator output for different gain/contrast settings is shown in Figure 6.
Figure 6- Voltage Regulator Output for different Gain/Contrast Settings
Solomon Systech
Mar 2004
P 18/47
Rev 1.2
SSD1818A
4. Bias Ratio Selection circuitry The bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9. Since there will be slightly different in command pattern for different MUX, please refer to Command Descriptions section of this data sheet. If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VL6) to give the LCD driving levels (VL2 ~ VL5). A low power consumption circuit design in this bias divider saves most of the display current comparing to the traditional design. Stabilizing Capacitors (0.1uF ~ 0.47uF) are required to be connected between these voltage level pins (VL2 ~ VL5) and (VDD). If the LCD panel loading is heavy, four additional resistors are suggested to add to the application circuit as follows:
SSD1818A SSD1815B VDD VL2 V L3 V L4 V L5 V L6
R3 R4
R2
R1
V DD
C5
C4
C3
C2
C1
+
+
+
+
Remark: C1 ~ C5~ C5 = ~ 0.47uF 0. 47uF Remark: 1. 1. C1 = 0.1uF 0.01 ~ 2. R1 ~ R1 = 100k ~1M 1M 2. R4 ~ R4 = 100k~
5. Self adjust temperature compensation circuitry This block provides 4 different compensation settings to satisfy various liquid crystal temperature grades by software control. Default temperature coefficient (TC) setting is TC0.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 104 x 65 = 6760 bits. Table 4 on Page 20 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Table 4 on Page 20 shows the case in which the display start line register is set to 38h. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage.
SSD1818A
+
Rev 1.2
P 19/47
Mar 2004
Solomon Systech
Common Pins 48 MUX Mode RAM Row 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Page 8 Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0 RAM Column Normal Remapped D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) Segment Pins 0 1 2 3 00h 67h 01h 66h 02h 65h 03h 64h ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** ****** 100 101 102 103 64h 03h 65h 02h 66h 01h 67h 00h Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 X X X X X X X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 47 46 45 44 43 42 41 40 ICONS 54 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X 53 52 51 50 49 48 47 46 ICONS 32 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 2 3 4 5 6 7 ICONS Remapped 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 ICONS 64 MUX Mode Normal 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 2 3 4 5 6 7 ICONS Remapped 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 ICONS
Remarks : DB0 - DB7 represent the data bit of the GDDRAM
Table 4 - Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h
Solomon Systech
Mar 2004
P 20/47
Rev 1.2
SSD1818A
Reset Circuit
This block includes Power On Reset (POR) circuitry and the hardware reset pin, RES . The POR and Hardware reset performs the same reset function. Once RES receives a reset pulse, all internal circuitry will start to initialize. Minimum pulse width the reset sequence is 5 - 10us. Status of the chip after reset is given by: Display is turned OFF Default Display Mode: 104 x 64 + 1 Icon Line Normal segment and display data column address mapping (Seg0 mapped to Row address 00h) Read-modify-write mode is OFF Power control register is set to 000b Shift register data clear in serial interface Bias ratio is set to default: 1/9 Static indicator is turned OFF Display start line is set to GDDRAM column 0 Column address counter is set to 00h Page address is set to 0 Normal scan direction of the COM outputs Contrast control register is set to 20h Test mode is turned OFF Temperature Coefficient is set to TC0 Note: Please find more explanation in the Applications Note attached at the back of the specification. Display Data Latch This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level. 64 MUX: 104 + 65 = 169
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. The output is shifted out with reference an internal FRM clock that comes from the Display Timing Generator. The level selector, which is synchronized with the internal M signal, gives the voltage levels.
Level Selector
Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
SSD1818A
Rev 1.2
P 21/47
Mar 2004
Solomon Systech
LCD Panel Driving Waveform
Figure 7 is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms illustrate the desired multiplex scheme.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 01234 GGGGG EEEEE
* N+1 1 2 3 4 5 6 7 8 9 N+1 ... *
TIME SLOT
1 2 3 4 5 6 7 89 * . . . N+1 1 2 3 4 5 6 7 8 9 * . . . N+1 1 2 3 4 5 6 7 8 9 . .
VDD VL2 COM0 VL3 VL4 VL5 VL6 VDD VL2 COM1 VL3 VL4 VL5 VL6 VDD VL2 SEG0 VL3 VL4 VL5 VL6 VDD VL2 SEG1 VL3 VL4 VL5 VL6 M
* Note 1: N+1 is the number of multiplex ratio including Icon.
Figure 7 - LCD Driving Waveform for Displaying "0"
Solomon Systech
Mar 2004
P 22/47
Rev 1.2
SSD1818A
8. COMMAND TABLE
Table 5 - Write Command Table (D/ C =0, R/ W ( WR )=0, E( RD )=1) D/C 0 Hex 00 - 0F D7 D6 D5 D4 0000 D3 X3 D2 X2 D1 X1 D0 X0 Command Set Lower Column Address Set Higher Column Address Set Internal Gain Resistor Ratio Set Power Control Register Description Set the lower nibble of the column address register using X3X2X1X0 as data bits. The lower nibble of column address is reset to 0000b after POR. Set the higher nibble of the column address register using X3X2X1X0 as data bits. The higher nibble of column address is reset to 0000b after POR. Feedback gain of the internal regulated DC-DC converter for generating VOUT increases as X2X1X0 increased from 000b to 111b. After POR, X2X1X0 = 100b. X0=0: turns off the output op-amp buffer (POR) X0=1: turns on the output op-amp buffer X1=0: turns off the internal regulator (POR) X1=1: turns on the internal regulator X2=0: turns off the internal voltage booster (POR) X2=1: turns on the internal voltage booster Set GDDRAM display start line register from 0-63 using X5X4X3X2X1X0. Display start line register is reset to 000000 after POR. Select contrast level from 64 contrast steps. Contrast increases (VL6 decreases) as X5X4X3X2X1X0 is increased from 000000b to 111111b. X5X4X3X2X1X0 = 100000b after POR. X0=0: column address 00h is mapped to SEG0 (POR) X0=1: column address 67h is mapped to SEG0 Refer to Table 4 on page 20 for example. X0=0: POR default bias 48 MUX Mode: 1/8 54 MUX Mode: 1/8.4 32 MUX Mode: 1/6 64 MUX Mode: 1/9 X0=1: alternate bias 48 MUX Mode: 1/6 54 MUX Mode: 1/6 32 MUX Mode: 1/5 64 MUX Mode: 1/7 For other bias ratio settings, see "Set 1/4 Bias Ratio" and "Set Bias Ratio" in Extended Command Set.
0
10 - 1F
0
0
0
1
X3
X2
X1
X0
0
20 - 27
0
0
1
0
0
X2
X1
X0
0
28 - 2F
0
0
1
0
1
X2
X1
X0
0
40 - 7F
0
1
X5 X4
X3
X2
X1
X0
Set Display Start Line
0 0
81 00 - 3F
1 *
0 *
00 X5 X4 1 0
0 X3 0
0 X2 0
0 X1 0
1 X0 X0
Set Contrast Control Register Set Segment Re-map
0
A0 - A1
1
0
0
A2 - A3
1
0
1
0
0
0
1
X0
Set LCD Bias
SSD1818A
Rev 1.2
P 23/47
Mar 2004
Solomon Systech
D/C Hex D7 D6 D5 D4 0 A4 - A5 1 0 1 0 0 A6 - A7 1 0 1 0
D3 0 0
D2 1 1
D1 0 1
D0 X0 X0 X0 X0 *
0 0 0
AE - AF B0 - B8 C0 - C8
1 1 1
0 0 1
1 1 0
0 1 0
1 X3 X3
1 X2 *
1 X1 *
0
E0
1
1
1
0
0
0
0
0
0 0
E2 EE
1 1
1 1
1 1
0 0
0 1
0 1
1 1
0 0
0 0
AC - AD 00 - 03
1 *
0 *
1 *
0 *
1 *
1 *
0 X1
X0 X0
0 0 0 0 0
E3 F0 F0 - FF AE A5
1 1 1 1 1
1 1 1 0 0
1 1 1 1 1
0 1 1 0 0
0 0 * 1 0
0 0 * 1 1
1 0 * 1 0
1 0 * 0 1
X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel Set Page Address Set GDDRAM Page Address (0-8) for read/write using X3X2X1X0 Set COM Output X3=0: normal mode (POR) Scan Direction X3=1: remapped mode, COM0 to COM [N-1] becomes COM [N-1] to COM0 when Multiplex ratio is equal to N. See Table 4 on page 20 for detail mapping. Set Read-ModifyRead-Modify-Write mode will be entered in Write Mode which the column address will not be increased during display data read. After POR, Read-modify-write mode is turned OFF. Software Reset Initialize internal status registers. Set End of ReadExit Read-Modify-Write mode. RAM Column Modify-Write Mode address before entering the mode will be restored. After POR, Read-modify-write mode is OFF. Indicator Display This second byte command is required ONLY Mode and Set when "Set Indicator On" command is sent. Indicator On/Off X0 = 0: indicator off (POR, second command byte is not required) X0 = 1: indicator on (second command byte required) X1X0 = 00: indicator off X1X0 = 01: indicator on and blinking at ~1 second interval X1X0 = 10: indicator on and blinking at ~1/2 second interval X1X0 = 11: indicator on constantly NOP Command result in No Operation. Test Mode Reset Set Test Mode Set Power Save Mode Reserved for IC testing. Do NOT use. Reserved for IC testing. Do NOT use. Either standby or sleep mode will be entered using compound commands. Issue compound commands "Set Display Off" followed by "Set Entire Display On".
Command Set Entire Display On/Off Set Normal/Reverse Display Set Display On/Off
Description X0=0: normal display (POR) X0=1: entire display on X0=0: normal display (POR) X0=1: reverse display
Note: " * " stands for don't care bit
Solomon Systech
Mar 2004
P 24/47
Rev 1.2
SSD1818A
EXTENDED COMMAND TABLE
Table 6 - Extended Command Table (D/ C = 0,R/W ( WR ) = 0,E=1( RD = 1) unless specific setting is stated) D/C Hex D7 D6 D5 D4 0 A8 1010 0 00 - 7F 0 X6 X5 X4 D3 1 X3 D2 0 X2 D1 0 X1 D0 0 X0 Command Set Multiplex Ratio Description To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value) for each member (including icon line for 65 MUX mode). Max. MUX ratio: 68 MUX: 68 N = X6X5X4X3X2X1X0 + 1 + ICON*, (*ICON exist for 64/54/32 MUX mode) e.g. N = 001111b + 2 = 17 For 64 MUX Mode X1X0 = 00(POR) 01 10 11 1/9 or 1/7 1/5 1/6 1/8 For 54 MUX Mode X1X0 = 00(POR) 01 10 11 1/8.4 or 1/6 1/5 1/6 1/8 Set Bias Ratio (X1X0) For 48 MUX Mode X1X0 = 00(POR) 01 10 11 1/8 or 1/6 1/5 1/6 1/8 For 32 MUX Mode X1X0 = 00(POR) 01 10 1/6 or 1/5 1/5 1/6
0 0
A9 1010 00 - FF X7 X6 X5 X4
1 X3
0 X2
0 X1
1 X0
11 1/8
Set TC Value (X4X3X2)
X4X3X2 = 000: (TC0) Typ. -0.07 X4X3X2 = 010: (TC2) Typ. -0.13 X4X3X2 = 100: (TC4) Typ. -0.26 X4X3X2 = 111: (TC7) Typ. -0.29 X4X3X2 = 001, 011, 101, 110: Reserved Increase the value of X7X6X5 will increase the oscillator frequency and vice versa. Default Mode: X7X6X5 = 011 (POR for 48 MUX Mode, 54 MUX Mode) : Typ. 31.5kHz
Modify Osc. Freq. (X7X6X5)
X7X6X5 = 011 (POR for 32 MUX Mode, 64 MUX Mode) : Typ. 18.7kHz Remarks: By software program the multiplex ratio, the typical oscillator frequency is listed above.
SSD1818A
Rev 1.2
P 25/47
Mar 2004
Solomon Systech
D/C
Hex
D7 D6
D5
D4
D3
D2
D1
D0
Command
Description
0
AA - AB
1
0
1
0
1
0
1
X0 X0 0 *
0 0 0
D0 - D1 D2 00 - 60
1 1 0
1
0
1 1 *
0 0 *
0 0 *
0 1 *
10 X6 X5
0 0
D4 00 - 30
1 0
1 0
01 X5 X4
0 0
1 0
0 0
0 0
0 0
D3 00 - 3F
1 0
1 0
01 X5 X 4
0 X3
0 X2
1 X1
1 X0
0 0
D6 3C - 3F
1 0
1 0
0 1
1 1
0 1
1 1
1 X1
0 X0
0
00 - FF
D7 D6 D5 D4
D3
D2
D1
D0
X0 = 0: use normal setting (POR) X0 = 1: fixed at 1/4 bias regardless of other bias setting commands Set Smart Icon Smart icon mode used for low power application. Mode X0 = 0: smart icon mode disable (POR) X0 = 1: smart icon mode enable Set Phases of The contrast level of the smart icon is controlled by Smart Icon 4 phases. The more the total phases, the lower the Mode contrast level. X6X5 = 00: 5 phases X6X5 = 01: 7 phases (POR) X6X5 = 10: 9 phases X6X5 = 11: 16 phases Set Total Frame The On/Off of the Static Icon is given by 3 phases / Phases of Static 1 phase overlapping of the M and MSTAT signals. Icon This command set total phases of the M/MSTAT signals for each frame. The more the total phases, the lower the contrast level. X5X4 = 00: 5 phases X5X4 = 01: 7 phases X5X4 = 10: 9 phases (POR) X5X4 = 11: 16 phases Set Display After POR, X5X4X3X2X1X0 = 0 Offset After setting MUX ratio less than default value, data will be displayed at Center of display matrix. To move display towards Row 0 by L, X5X4X3X2X1X0 = L To move display away from Row 0 by L, X5X4X3X2X1X0 = 64-L Note: Max. value of L = (POR default MUX ratio - display MUX)/2 Enable Band X1X0 = Gap Reference 00 01(POR) 10 11 Circuit 100 ms 200 ms 400 ms 800 ms Approx. band gap clock period Recommendation: set the band gap clock period to approx. 200ms Status Register D7=0: indicates the driver is ready for command. Read D7=1: indicates the driver is Busy. D6=0: indicates reverse segment mapping with column address. D6=1: indicates normal segment mapping with column address. D5=0: indicates the display is ON. D5=1: indicates the display is OFF. D4=0: initialization is completed. D4=1: initialization process is in progress after RES or software reset. D3D2D1D0 = 1001 or 0011, the 4-bit is fixed to either 1001 or 0011 which could be used to identify as Solomon Systech Device.
Set 1/4 Bias Ratio
Solomon Systech
Mar 2004
P 26/47
Rev 1.2
SSD1818A
Note: - " * " stands for don't care bit - Command patterns other than that given in Command Table and Extended Command Table are prohibited. Otherwise, unexpected result will occur.
Data Read / Write
To read data from the GDDRAM, input High to R/ W ( WR ) pin and D/ C pin for 6800-series parallel mode, input Low to E ( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided in serial interface mode. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a dummy read is required before first valid data is read. See Figure 3 on page 15 in Functional Block Descriptions section for detail waveform diagram. To write data to the GDDRAM, input Low to R/ W ( WR ) pin and High to D/ C pin for both 6800-series and 8080-series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. It should be noted that, after the automatic column address increment, the pointer would NOT wrap round to 0. The pointer will exit the memory address space after accessing the last column. Therefore, the pointer should be re-initialized when progress to another page address
D/ C 0 0 1 1
R/ W ( WR )
0 1 0 1
Action Write Command Read Status Write Data Read Data
Auto Address Increment No No Yes Yes
Table 7 - Automatic Address Increment
SSD1818A
Rev 1.2
P 27/47
Mar 2004
Solomon Systech
9. COMMAND DESCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU.
Set Higher Column Address
This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be increased by each data access after it is pre-set by the MCU.
Set Internal Regulator Resistors Ratio
This command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (IRS pin pulled high). In other words, this command is used to select which contrast curve from the eight possible selections. Please refer to Functional Block Descriptions section for detail calculation of the LCD driving voltage.
Set Power Control Register
This command turns on/off the various power circuits associated with the chip. There are three related power sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the negative voltage supply (VEE) from the voltage input (VSS1 - VDD). An external negative power supply is required if this option is turned off. Internal regulator is used to generate the LCD driving voltage, VL6, from the negative power supply, VEE. Output op-amp buffer is the internal divider for dividing the different voltage levels (VL2, VL3, VL4, VL5) from the internal regulator output, VL6. External voltage sources should be fed into this driver if this circuit is turned off.
Set Display Start Line
This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 63 are assigned to Page 0 to 7. Please refer to Table 4 on Page 20 as an example for display start line set to 56 (38h).
Set Contrast Control Register
This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, VL6, provided by the On-Chip power circuits. VL6 is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. See Figure 8 for the contrast control flow.
Set Contrast Control Register Contrast Level Data No Changes Complete? Yes
Figure 8 - Contrast Control Flow Set Segment Re-map
Solomon Systech
Mar 2004
P 28/47
Rev 1.2
SSD1818A
This command changes the mapping between the display data column addresses and segment drivers. It allows flexibility in mechanical layout of LCD glass design. Please refer to Table 4 on Page 20 for example.
Set LCD Bias
This command is used to select a suitable bias ratio required for driving the particular LCD panel in use. The selectable values of this command for 64 MUX are 1/9 or 1/7, for 54 MUX are 1/8.4 or 1/6, for 48 MUX are 1/8 or 1/6, for 32 MUX are 1/6 or 1/5. For other bias ratio settings, extended commands should be used.
Set Entire Display On/Off
This command forces the entire display, including the icon row, to be illuminated regardless of the contents of the GDDRAM. In addition, this command has higher priority than the normal/reverse display. This command is used together with "Set Display ON/OFF" command to form a compound command for entering power save mode. See "Set Power Save Mode" later in this section.
Set Normal/Reverse Display
This command turns the display to be either normal or reverse. In normal display, a RAM data of 1 indicates an illumination on the corresponding pixel, while in reverse display, a RAM data of 0 will turn on the pixel. It should be noted that the icon line will not affect, that is not reverse by this command.
Set Display On/Off
This command is used to turn the display on or off. When display off is issued with entire display is on, power save mode will be entered. See "Set Power Save Mode" later in this section for details.
Set Page Address
This command enters the page address from 0 to 8 to the RAM page register for read/write operations. Please refer to Table 4 on Page 20 for detail mapping.
Set COM Output Scan Direction
This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. See Table 4 on Page 20 for the relationship between turning on or off of this feature. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect.
Set Read-Modify-Write Mode
This command puts the chip in read-modify-write mode in which: 1. column address is saved before entering the mode 2. column address is increased only after display data write but not after display data read. This Read-Modify-Write mode is used to save the MCU's loading when a very portion of display area is being updated frequently. As reading the data will not change the column address, it could be get back from the chip and do some operation in the MCU. Then the updated data could be writing back to the GDDRAM with automatic address increment. After updating the area, "Set End of Read-Modify-Write Mode" is sent to restore the column address and ready for next update sequence.
Software Reset
Issuing this command causes some of the chip's internal status registers to be initialized: Read-Modify-Write mode is off Static indicator is turned OFF
SSD1818A Rev 1.2 P 29/47 Mar 2004 Solomon Systech
Display start line register is cleared to 0 Column address counter is cleared to 0 Page address is cleared to 0 Normal scan direction of the COM outputs Internal regulator resistors Ratio is set to 4 Contrast control register is set to 20h
Set End of Read-Modify-Write Mode
This command relieves the chip from read-modify-write mode. The column address before entering readmodify-write mode will be restored no matter how much modification during the read-modify-write mode.
Set Indicator On/Off
This command turns on or off the static indicator driven by the M and MSTAT pins. When the "Set Indicator On" command is sent, the second command byte "Indicator Display Mode" must be followed. However, the "Set Indicator Off" command is a single byte command and no second byte command is required. The status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. See "Set Power Save Mode" later in this section.
NOP
A command causing the chip takes No Operation.
Set Test Mode
This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, users should NOT use this command.
Set Power Save Mode
Entering Standby or Sleep Mode should be done by using a compound command composed of "Set Display ON/OFF" and "Set Entire Display ON/OFF" commands. When "Set Entire Display ON" is issued when display is OFF, either Standby Mode or Sleep Mode will be entered. The status of the Static Indicator will determine which power save mode is entered. If static indicator is off, the Sleep Mode will be entered: Internal oscillator and LCD power supply circuits are stopped Segment and Common drivers output VDD level The display data and operation mode before sleep are held Internal display RAM can still be accessed If the static indicator is on, the chip enters Standby Mode, which is similar to sleep mode except addition with: Internal oscillator is on Static drive system is on Please also be noted that during Standby Mode, if the software-reset command is issued, Sleep Mode will be entered. Both power-save modes can be exited by the issue of a new software command or by pulling Low at hardware pin RES .
Status register Read
This command is issued by pulling D/ C Low during a data read (refer to Figure 9 on Page 38 and Figure 10 on Page 39 for parallel interface waveforms). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode.
Solomon Systech
Mar 2004
P 30/47
Rev 1.2
SSD1818A
EXTENDED COMMANDS
These commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip.
Set Multiplex Ratio
This command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (POR value), including the icon line. Max. MUX ratio: 65 The chip pins ROW0-ROW63 will be switched to corresponding COM signal output, see Table 8 on Page 33 for examples of 18 multiplex (including icon line) settings with and without 7 lines display offset for different MUX. It should be noted that after changing the display multiplex ratio, the bias ratio might also need to be adjusted to make display contrast consistent.
Set Bias Ratio
Except the 1/4 bias, all other available bias ratios could be selected using this command plus the "Set LCD Bias" command. For detail setting values and POR default, please refer to the extended command table, Table 6 on Page 25.
Set Temperature Coefficient (TC) Value
One out of 4 different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. Please refer to the extended command table, Table 6 on Page 25, for detailed TC values.
Modify Oscillator Frequency
The oscillator frequency can be fine tuned by applying this command. Since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. Please contact SOLOMON Systech Limited application engineers for more detail explanation on this command.
Set 1/4 Bias Ratio
This command sets the bias ratio directly to 1/4. This bias ratio is especially designed for use in under 12 MUX display. In order to restore to other bias ratio, this command must be executed, with LSB=0, before the "Set Multiplex ratio" or "Set LCD Bias" command is sent.
Set Smart Icon Mode
The smart icon mode is designed for the low power application. This command is used to enable the smart icon mode.
Set Phases of Smart Icon Mode
The contrast level of the smart icon is controlled by 4 phases. The more the total phases, the shorter overlap time and thus the lower effective driving voltage. As a result, the contrast level of the smart icon will be lower. Change of this smart icon mode phases will not affect the total frame phases of the static icon. They are independent commands.
Set Total Frame Phases of Static Icon
The total number of phases for one display frame is set by this command. The overlapping of the M and MSTAT signals generates the Static Icon. These two pins output either VSS or VDD at same frequency but with phase different.
SSD1818A
Rev 1.2
P 31/47
Mar 2004
Solomon Systech
To turn on the Static Icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the off status. The more the total frame phases, the shorter overlap time and thus the lower effective driving voltage. As a result, the contrast level of the static icon will be lower.
Set Display Offset
This command should be sent ONLY when the multiplex ratio is set less than the default value. When a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the LCD, see the no offset columns on Table 8 on Page 33. Use this command could move the display vertically within the 64 commons. To make the Reduced-MUX Com 0 (Com 0 after reducing the multiplex ratio) towards the Row 0 direction for L lines, the 6-bit data in second command should be given by L. An example for 21 lines moving towards to Com0 direction is given on Table 8 on Page 33. To move in the other direction by L lines, the 6-bit data should be given by 64-L. Please note that the display is confined within the default multiplex value. That is the half of the default value minus the reduced-multiplex ratio gives the maximum value of L. For an odd display MUX after reduction, moving away from Row 0 direction will has 1 more step.
Enable Band Gap Reference Circuit
This command enables or disables the band gap reference circuit. There are four selections on the band gap clock period. We recommended setting the band gap clock period to 200ms in normal operation.
Solomon Systech
Mar 2004
P 32/47
Rev 1.2
SSD1818A
48 MUX Mode No Offset ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 NC NC NC NC NC NC NC NC X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X NC NC NC NC NC NC NC NC
7 lines Offset NC NC NC NC NC NC NC NC COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 NC NC NC NC NC NC NC NC
54 MUX Mode No Offset NC NC NC NC NC X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X NC NC NC NC NC
7 lines Offset NC NC NC NC NC COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 NC NC NC NC NC
32 MUX Mode No Offset NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
7 lines Offset NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM14 COM15 COM16 X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
64 MUX Mode No Offset X X X X X X X X X X X X X X X X X X X X X X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X
7 lines Offset X X COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Table 8 - ROW pin assignment for COM signals for SSD1818A in an 18 MUX display (including icon line) without/with 21 lines display offset towards ROW0
Note: X-Row pin will output non-selected COM signal
SSD1818A
Rev 1.2
P 33/47
Mar 2004
Solomon Systech
10. MAXIMUM RATINGS
Table 9 - Maximum Ratings (Voltage Referenced to VSS)
Symbol VDD VEE Vin I TA Tstg Parameter Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Value -0.3 to +4.0 0 to -12.0 VSS-0.3 to VDD+0.3 25 -30 to +85 -65 to +150 Unit V V V mA
o o
C C
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VDD and VEE be constrained to the range VSS < or = (VDD or VEE) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
Solomon Systech
Mar 2004
P 34/47
Rev 1.2
SSD1818A
11. DC CHARACTERISTICS
Table 10 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C) Symbol VDD Parameter Test Condition Logic Circuit Supply Voltage Recommend Operating Voltage Range Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Access Mode Supply Enabled, Write accessing, Tcyc Current Drain (VDD Pins) =3.3MHz, Typ. Osc. Freq., Display On, no panel attached. VDD = 2.7V, VEE = -8.1V, Voltage Display Mode Supply Current Drain (VDD Pins) Generator Disabled, R/ W ( WR ) Halt, Typ. Osc. Freq., Display On, VL6 - VDD = -9V, no panel attached. VDD = 2.7V, VEE = -8.1V, Voltage Generator On, 4x DC-DC Converter Enabled, R/ W ( WR ) Halt, Typ. Osc. Freq., Display On, VL6 - VDD = -9V, no panel attached. VDD = 2.7V, LCD Driving Waveform Off, Typ. Osc. Freq., R/ W ( WR ) halt. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, R/ W ( WR ) halt. Display On, Voltage Generator Enabled, DC-DC Converter Enabled, Typ. Osc. Freq., Regulator Enabled, Divider Enabled. Voltage Generator Disabled. Iout=-100mA Iout=100mA Min 2.4 Typ 2.7 Max 3.5 Unit V V A
IAC
-
480
600
IDP1
-
50
100
A
IDP2
Display Mode Supply Current Drain (VDD Pins)
-
120
200
A
ISB
Standby Mode Supply Current Drain (VDD Pins) Sleep Mode Supply Current Drain (VDD Pins) LCD Driving Voltage Generator Output (VEE Pin) LCD Driving Voltage Input (VEE Pin) Logic High Output Voltage Logic Low Output Voltage
-
5
10
A
ISLEEP
-
1
5
A
VEE
-12.0
-
-2.4
V
VLCD VOH1 VOL1 VL6 VL6 VIH1 VIL1
-12.0 0.9*VDD 0 VEE-0.5 0.8*VDD 0
floating -
-2.4 VDD 0.1* VDD VDD VDD 0.2* VDD
V V V V V V V
Regulator Enabled (VL6 voltage LCD Driving Voltage Source depends on Int/Ext Contrast (VL6 Pin) Control) LCD Driving Voltage Source Regulator Disable (VL6 Pin) Logic High Input voltage Logic Low Input voltage
SSD1818A
Rev 1.2
P 35/47
Mar 2004
Solomon Systech
VL2 VL3 VL4 VL5 VL6 VL2 VL3 VL4 VL5 VL6 IOH IOL IOZ IIL/IIH CIN VL6
Voltage reference to VDD, Bias LCD Display Voltage Output Divider Enabled, 1:a bias ratio (VL2, VL3, VL4, VL5, VL6 Pins) VL3 VL4 VL5 VL6 -12V 50 -1 -1 Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 -3
LCD Display Voltage Input (VL2, VL3,VL4, VL5, VL6 Pins) Logic High Output Current Source Logic Low Output Current Drain Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Variation of VL6 Output (VDD is fixed) Temperature Coefficient
Voltage reference to VDD, External Voltage Generator, Bias Divider Disabled Vout = VDD-0.4V Vout = 0.4V
1/a*VL6 2/a*VL6 (a-2)/a *VL6 (a-1)/a *VL6 VL6 5 0
VDD VL2 VL3 VL4 VL5 -50 1 1 7.5 3
V V V V V V V V V V A A A A pF %
TC0
Compensation Flat Temperature Coefficient Voltage Regulator Enabled (POR) Temperature Coefficient 2* Temperature Coefficient 4* Temperature Coefficient 7*
0
-0.07
-0.11 %/ C
o
TC2 TC4 TC7
-0.11 -0.15 -0.28
-0.13 -0.26 -0.29
-0.15 -0.28 -0.30
%/ C o %/ C o %/ C
o
The formula for the temperature coefficient is: TC(%) = Vref at 50 C - Vref at 0 C x o o 50 C - 0 C
o o
1 o Vref at 25 C
x 100 %
Solomon Systech
Mar 2004
P 36/47
Rev 1.2
SSD1818A
12. AC CHARACTERISTICS
Table 11 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = -30 to 85C) Symbol Fosc Parameter Oscillation Frequency of Display Timing Generator for: 64/32 Mux Mode: 54/48 Mux Mode: Test Condition Internal Oscillator Enabled (default), VDD = 2.7V Remark: Oscillation Frequency vs. Temperature change (-20C to 70C): -0.29%/C (64 Mux), -0.31%/C (54/48 Mux) and -0.24%/C (32 Mux) 104 x 64 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 64 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 54 Mux Mode 104 x 54 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 54 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 48 Mux Mode 104 x 48 Graphic Display Mode, Display ON, Internal Oscillator Enabled 104 x 48 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. 32 Mux Mode 104 x 32 Graphic Display Mode, Display ON, Internal Oscillator Enabled Min 15.9 26.4 Typ 18.7 31.5 Max 25.7 42.72 Unit KHz
FFRM
Frame Frequency 64 Mux Mode Fosc 4x65 Fext 4x65 Hz
Hz
Fosc 8x54 Fext 8x54
Hz
Hz
Fosc 8x49 Fext 4x49
Hz
Hz
Fosc 8x33
Hz
Remarks:
104 x 32 Graphic Display Mode, Fext Display ON, Internal Oscillator 4x33 Disabled, External clock with freq., Fext, feeding to CL pin. Fext stands for the frequency value of external clock feeding to the CL pin Fosc stands for the frequency value of internal oscillator Frequency limits are based on the software command set: set multiplex ratio to 64 MUX
Hz
SSD1818A
Rev 1.2
P 37/47
Mar 2004
Solomon Systech
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min 300 0 0 40 15 20 120 60 60 60 -
Typ -
Max 70 140 15 15
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Table 12 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
R/W
D/C tAS
E
tAH
tcycle PWCSL PWCSH
CS1 CS2 = 1
tF tDSW D0-D7 (Write data to driver) Valid Data
tR tDHW
D0-D7 (Read data from driver)
tACC Valid Data
tDHR
tOH
Figure 9 - 6800-series MPU Parallel Interface Characteristics
Solomon Systech
Mar 2004
P 38/47
Rev 1.2
SSD1818A
Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min 300 0 0 40 15 20 120 60 60 60 -
Typ -
Max 70 140 15 15
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Table 13 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
D/C tAS CS1 CS2 = 1 tcycle PWCSL
RD
tAH
PWCSH
WR
tF tDSW D0-D7 (Write data to driver) Valid Data
tR
tDHW
D0-D7 (Read data from driver)
tACC Valid Data
tDHR
tOH
Figure 10 - 8080-series MPU Parallel Interface Characteristics
SSD1818A
Rev 1.2
P 39/47
Mar 2004
Solomon Systech
Symbol tcycle tAS tAH tDSW tDHW TCLKL TCLKH tCSS tCSH tR tF
Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Chip Select Setup Time (for D7 input) Chip Select Hold Time (for D0 input) Rise Time Fall Time
Min 250 150 150 100 100 100 100 120 60 -
Typ -
Max 15 15
Unit ns ns ns ns ns ns ns ns ns ns ns
Table 14 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85C)
D/C tAS CS1 CS2 = 1 tCLKL tCSS tcycle tAH
tCLKH
SCK
tF tDSW SDA Valid Data
tR tDHW
D/C
CS1 (CS2 = 1) SDA
D7 D6 D5 D4 D3 D2 D1 D0
SCK
Figure 11 - Serial Interface Characteristics
Solomon Systech
Mar 2004
P 40/47
Rev 1.2
SSD1818A
13. APPLICATION EXAMPLES
ICONS COM0 : : COM10 COM11 : : COM30 COM31
DISPLAY PANEL SIZE 104 x 64 + 1 ICONS LINE
COM32 COM33 : : : : COM63 ICONS
SEG0..................................SEG103
Segment Remapped [Command: A1]
COM43............COM32 G103............................SEG0 ICONS COM44 COM45 : : : : : COM63 ICONS Remapped COM SCAN Directiion [Command: C8] COM0 ........... COM10 COM11 : : COM18 COM19 : : COM30 COM31
Remapped COM SCAN Directiion [Command: C8]
SSD1818A IC 64 MUX
VL2
VL3
VL4
VL5
VL6
D0-D7 /CS1 /RES D/C R/W VSS[GND] VEE IRS
VDD = 2.775V
External Vneg = -9.5V
0.1 ~ 0.47 uF x 5
Logic pin connections not specified above: Pins connected to VDD: CS2, E/ RD , M/ S , CLS, C68/ 80 , P/ S , HPM Pins connected to VSS: VSS1 Pins floating: DOF , CL
Figure 12 - Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with: external VEE, internal regulator, divider mode enabled (Command: 2B), 6800-series MPU parallel interface, internal oscillator and master mode
SSD1818A
Rev 1.2
P 41/47
Mar 2004
Solomon Systech
ICONS COM0 : : COM10 COM11 : : COM30 COM31
DISPLAY PANEL SIZE 104 x 64 + 1 ICONS LINE
COM32 COM33 : : : : COM63 ICONS
SEG0.................................SEG103
COM43............COM32 COM44 COM45 : : : : : COM63 ICONS Remapped COM SCAN Directiion [Command: C8]
SEG103............................SEG0
ICONS
COM0 .......... .
SSD1818A IC 64 MUX (DIE FACE UP)
VSS VEE C3N C1P C1N C2N C2P C4N
COM10 COM11 : : COM18 COM19 : : COM30 COM31
Remapped COM SCAN Directiion [Command: C8]
VL2
VL3
VL4
VL5
VL6
D0-D7 and Control Bus
0.47 - 4.7uF x 5 5X boosting VSS [GND]
VDD = 2.775V
0.1 ~ 0.47 uF x 5
Logic pin connections not specified above: Pins connected to VDD: CS2, E/ RD , M/ S , CLS, C68/ 80 , P/ S , HPM Pins connected to VSS: VSS1 Pins floating: DOF , CL
Figure 13 - Application Circuit of 104 x 64 plus an icon line using SSD1818A, configured with all internal power control circuit enabled, 6800-series MPU parallel interface, internal oscillator and master mode.
Solomon Systech
Mar 2004
P 42/47
Rev 1.2
SSD1818A
14. Initialization Routine
Command (Hex)
(Refer to Figure 12: All internal power control circuit enable)
Command (Hex)
(Refer to Figure 13: External VEE, Internal regulator and divider enable)
Description Software Reset Set power control register Set internal resistor gain = 24h Set contrast level = 20h Enable band gap reference circuit Set band gap clock period = 200ms Set Column address is map to SEG0 Set Row address is map to COM0 Set entire display on/off = Normal display Set normal / reverse display = Normal display Set Display On
1 2 3 4 5
E2 2F 24 81 20 D6 3D
E2 2B 24 81 20 D6 3D A0 C0 A4 A6 AF External booster, Internal regulator and divider are enabled. VOP = approx. -8.593V with reference to VDD
6 7 8 9 10 Example
A0 C0 A4 A6 AF Internal booster, regulator and divider are enabled. VOP = approx. -8.573V with reference to VDD
SSD1818A
Rev 1.2
P 43/47
Mar 2004
Solomon Systech
15. TAB DRAWING
Figure 14 - SSD1818AT Copper View Layout
Solomon Systech
Mar 2004
P 44/47
Rev 1.2
SSD1818A
SSD1818A
Rev 1.2
P 45/47
Mar 2004
Solomon Systech
SSD1818AT Detail descriptions
Figure 15 - SSD1818AT Pin Assignment
Solomon Systech
Mar 2004
P 46/47
Rev 1.2
SSD1818A
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
http://www.solomon-systech.com
SSD1818A
Rev 1.2
P 47/47
Mar 2004
Solomon Systech

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