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Final Electrical Specifications
LTC4056-4.2 Linear Li-Ion Charger with Termination in ThinSOT
February 2003
FEATURES
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DESCRIPTIO
Standalone Li-Ion Charger with Termination Programmable Termination Timer No Sense Resistor or Blocking Diode Required Suitable for USB-Powered Charging Undervoltage Charge Current Limiting Preset Charge Voltage with 0.6% Accuracy Programmable Charge Current: 200mA to 700mA Automatic Recharge Self-Protection for Overcurrent/Overtemperature 40A Supply Current in Shutdown Mode Negligible Battery Drain Current in Shutdown Low Battery Charge Conditioning (Trickle Charging) CHRG Status Output including AC Present Sense Low Profile (1mm) ThinSOTTM Package PCB Total Solution Area only 75mm2 (700mA)
The LTC(R)4056 is a low cost, single-cell, constant-current/ constant-voltage Li-Ion battery charger controller with a programmable termination timer. When combined with a few external components, the LTC4056 forms a very small standalone charger for single cell lithium-ion batteries. Charge current and charge time are set externally with a single resistor and capacitor, respectively. The LTC4056 charges to a final float voltage accurate to 0.6%. Manual shutdown is accomplished by grounding the TIMER/ SHDN pin, while removing input power automatically puts the LTC4056 into a sleep mode. Both the shutdown and sleep modes drain near zero current from the battery and the shutdown mode reduces supply current to 40A. The output driver is both current limited and thermally protected to prevent operating outside of safe limits. No external blocking diode or sense resistor is required. The LTC4056 also includes low battery charge conditioning (trickle charging), undervoltage charge current limiting, automatic recharge and a charge status output. The LTC4056 is available in a low profile (1mm) 8-lead ThinSOT package.
, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
APPLICATIO S
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Cellular Telephones Handheld Computers Digital Cameras Charging Docks and Cradles Low Cost and Small Size Chargers
TYPICAL APPLICATIO
VIN Undervoltage Charge Current Limiting
800 VBAT = 4V 700 RPROG = 1.3k ICHRG = 700mA INPUT Z = 100m 600
IBAT (mA)
VIN 4.5V TO 6.5V CHARGE STATUS 1F 1F 1.3k
LTC4056 1 2 VCC ISENSE 8 3 DRIVE CHRG 7 6 TIMER/SHDN BAT 5 PROG GND
700mA ZXT1M322
500 400 300 200
UNDERVOLTAGE CHARGE CURRENT LIMITING
+
1-CELL 4.2V Li-Ion
4056-4.2 TA01
100
0 4.40 4.45
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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CONSTANT CURRENT UNDERVOLTAGE LOCKOUT AT 4.35V 4.50 4.55 4.60 4.65 4.70 4.75 VIN (V)
4056 TA02
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LTC4056-4.2
ABSOLUTE
(Note 1)
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PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC 1 ISENSE 2 DRIVE 3 GND 4 8 CHRG 7 TIMER/SHDN 6 BAT 5 PROG
Input Supply Voltage (VCC) ........................- 0.3V to 10V BAT, CHRG ................................................- 0.3V to 10V DRIVE, PROG, TIMER/SHDN ....... - 0.3V to (VCC + 0.3V) Output Current (ISENSE) ...................................... 900mA Short-Circuit Duration (BAT, ISENSE) ............Continuous Junction Temperature ........................................... 125C Operating Ambient Temperature Range (Note 2) .............................................. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4056ETS8-4.2 TS8 PART MARKING LTG5
TS8 PACKAGE 8-LEAD PLASTIC SOT-23
TJMAX = 125C, JA = 120C/W TO 200C/W DEPENDING ON PC BOARD LAYOUT
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V.
SYMBOL VCC Supply VCC ICC ISHDN IBMS IBSL VUVLOI VUVLOD VUVHYS VUVCL Input Supply Voltage (Note 3) Quiescent VCC Supply Current VCC Supply Current in Manual Shutdown Battery Drain Current in Manual Shutdown (Note 4) Battery Drain Current in Sleep Mode (Note 5) Undervoltage Rising Threshold Undervoltage Falling Threshold Undervoltage Hysteresis Undervoltage Charge Current Limit Threshold
q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN 4.5
TYP
MAX 6.5
UNITS V A A A A V V mV V
VBAT = 4.5V (Forces IDRIVE = 0) IPROG = 200A (RPROG = 5k) VTIMER/SHDN = 0V VTIMER/SHDN = 0V VCC = 0V VCC Increasing VCC Decreasing VUVLOI-VUVLOD
q
400 40 -1 -1 4.325 4.275 0 0 4.40 4.35 50 4.575 90 4.175 4.158 137 590 170 4.200 4.200 183 640
600 60 1 1 4.475 4.425
q q q q
VUVCL-VUVLOI UV Charge Current to UVLO Threshold Margin Charging Performance VFLOAT IBAT Output Float Voltage in Constant Voltage Mode Output Full-Scale Current in Constant Current Mode IBAT = 10mA IBAT = 10mA, 4.75V VCC 6.5V RPROG = 5k, 4.75V VCC 6.5V, Pass PNP Beta > 50, 0C TA 85C RPROG = 1.43k, 4.75V VCC 6.5V, Pass PNP Beta > 50, 0C TA 85C IDSINK ITRIKL VTRIKL VTRIKL VPROG1 VPROG2 Drive Output Current Trickle Charge Current Trickle Charge Threshold Trickle Charge Hysteresis PROG Pin Voltage PROG Pin Voltage RPROG = 5k (IPROG = 200A) RPROG = 1.43k (IPROG = 700A) VDRIVE = 3V VBAT = 2V, RPROG = 5k VBAT = 2V, RPROG = 1.43k VBAT Falling
250 4.225 4.242 228 690
q
q
30 5 12 7 20 2.80 70 1 1 10 28 2.87 95 1.02 1.02
q
2.73 45 0.98 0.98
q q
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mV V V mA mA mA mA mA V mV V V
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LTC4056-4.2
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V.
SYMBOL VRECHRG TTIMER VMSDT VMSHYS ISHDN Protection IDSHRT IPSHRT Status Output ICHRG VCHRG CHRG Pin Weak Pull-Down Current CHRG Output Low Voltage VCHRG = 1V, VTIMER/SHDN = 0V ICHRG = 10mA
q
ELECTRICAL CHARACTERISTICS
PARAMETER Recharge Voltage Threshold TIMER/SHDN Accuracy Manual Shutdown Threshold Manual Shutdown Hysteresis TIMER/SHDN Pin Pull-up Current Drive Output Short-Circuit Current Limit PROG Pin Short-Circuit Current Limit
CONDITIONS VFLOAT - VRECHRG, VBAT > VTRIKL, Charge Termination Timer Expired CTIMER = 1F RPROG = 1.43k VTIMER/SHDN Increasing VTIMER/SHDN Decreasing VTIMER/SHDN = 0V VDRIVE = VCC VPROG = 0V
q q
MIN 100
TYP 150 10
MAX 200 12 1 125 -4 130
UNITS mV % V mV A mA mA
Charger Manual Control
q
0.6 50 - 10 30
0.82 75 -7 65 1.4
6
12 0.2
18 0.4
A V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC4056E is guaranteed to meet performance specifications from 0C to 70C ambient temperature range. Specifications over the - 40C to 85C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Although the LTC4056 will operate with input voltages as low as 4.5V, charging will not begin until VCC exceeds VUVCL.
Note 4: Assumes that the external PNP pass transistor has negligible B-C reverse-leakage current when the collector is biased at 4.2V (VBAT) and the base is biased at 5V (VCC). Note 5: Assumes that the external PNP pass transistor has negligible B-E reverse-leakage current when the emitter is biased at 0V (VCC) and the base is biased at 4.2V (VBAT).
PI FU CTIO S
VCC (Pin 1): Positive Input Supply Voltage. This pin supplies power to the internal control circuitry and external PNP transistor through the internal current sense resistor. This pin should be bypassed to ground with a capacitor in the range of 1F to 10F. ISENSE (Pin 2): Sense Node for Charge Current. Current from VCC passes through the internal current sense resistor and out of the ISENSE pin to supply current to the emitter of the external PNP transistor. The collector of the PNP provides charge current to the battery. DRIVE (Pin 3): Base Drive Output for the External PNP Pass Transistor. Provides a controlled sink current that drives the base of the PNP. This pin has current limiting protection. GND (Pin 4): Ground. Provides a reference for the internal voltage regulator and a return for all internal circuits. When in the constant voltage mode, the LTC4056 will precisely regulate the voltage between the BAT and GND pins. The battery ground should connect close to the GND pin to avoid voltage drop errors. BAT (Pin 5): Battery Voltage Sense Input. A precision internal resistor divider sets the final float voltage on this pin. This divider is disconnected in the manual shutdown or sleep mode. No bypass capacitance is needed on this pin for stable operation when a battery is present. However, any low ESR capacitor exceeding 22F on this pin should be decoupled with 0.2 to 1 resistor. Without a battery, a minimum bypass capacitance of 4.7F with 0.5 series resistance is required. PROG (Pin 6): Charge Current Programming Pin. Provides a virtual reference voltage of 1V for an external resistor (RPROG) connected between this pin and ground to program the battery charge current. The typical charge current is 915 times the current through this resistor (IBAT = 915V/RPROG). Current is limited to approximately 1.4mA (IBAT of approximately 1.4A).
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LTC4056-4.2
PI FU CTIO S
TIMER/SHDN (Pin 7): Programmable Charge Termination Timer and Shutdown Input. Pulling this pin below the shutdown threshold voltage will shut down the charger reducing the supply current to approximately 40A and the battery drain current to near 0A. A capacitor on this pin programs the charge termination timer. CHRG (Pin 8): Open-Drain Charge Status Output. When the battery is being charged, the CHRG pin is pulled low by an internal N-channel MOSFET. When the timer has timed out (terminating the charge cycle) or when the LTC4056 is in shutdown, but power is applied to the IC (i.e., VCC > VUVLOI), a 12A current source is connected from the CHRG pin to ground. The CHRG pin is forced to a high impedance state when input power is not present (i.e., VCC < VUVLOD).
BLOCK DIAGRA
CHRG 100 UVLO 10A 110m ISENSE
5A TIMER/SHDN OSCILLATOR 1.2V VOLTAGE REFERENCE REF 1V C1 BAT
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VCC LTC4056-4.2
-
CA
+
SHDN TEMPERATURE AND CURRENT LIMIT OUTPUT DRIVER ITRIKL 20 * IPROG DRIVE
CHRG UV LOGIC SHDN
20A SHDN
COUNTER
+ + -
1.2V
+
IA
-
IPROG
+
VA
-
SHDN
PROG RPROG
4056-4.2 BD
GND
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OPERATIO
The LTC4056 is a linear battery charger controller with a programmable charge termination timer. Operation can be understood by referring to the Block Diagram. A charge cycle begins when VCC rises above the UVLO (undervoltage lockout) threshold VUVLOI (nominally 4.4V), an external current programming resistor is connected between the PROG pin and ground and the TIMER/SHDN pin is allowed to rise above the shutdown threshold VMSDT (nominally 0.82V). If the battery voltage is below VTRIKL (2.8V) at the beginning of the charge cycle, the charger goes into trickle charge mode to bring the cell voltage up to a safe level for charging at full current. In this mode, an internal current source provides approximately 2% of the programmed charge current to the BAT pin. The charger goes into the full charge constant current mode once the voltage on the BAT pin rises above VTRIKL + VTRIKL (2.9V). During full current charging, the collector of the external PNP provides the charge current. The PNP emitter current flows through the ISENSE pin and through the internal 110m current sense resistor. This current is close in magnitude, but slightly more than the collector current since it includes base current. Amplifier A1 forces 1V on the PROG pin. Therefore, a current equal to 1V/RPROG will flow through the internal 100 resistor. Amplifier CA will force the same voltage that appears across the 100 resistor to appear across the internal 110m resistor. This amplifier ensures that the current flowing out of the ISENSE pin is equal to 915 times the current flowing out of the PROG pin. Therefore, neglecting base current, the charge current will be 915V/RPROG. This region of operation is referred to as constant current mode.
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As the battery accepts charge, its voltage rises. When it reaches the preset float voltage of 4.2V, a precisely divided down version of this voltage (1.2V) is compared to the 1.2V internal reference voltage by amplifier VA. If the battery voltage attempts to exceed 4.2V (1.2V at the input of amplifier VA), the amplifier will divert current away from the output driver thus limiting charge current to maintain 4.2V on the battery. This is the constant voltage mode. An external capacitor on the TIMER/SHDN pin and the resistance between the PROG pin and ground set the total charge time. When this time elapses, the charge cycle terminates and the CHRG pin transitions from a strong pull-down to a weak 12A pull-down. To restart the charge cycle, simply remove the input voltage and reapply it or momentarily force the TIMER/SHDN pin to ground. The charge cycle will also restart if the BAT pin voltage falls below the recharge threshold (VRECHRG is nominally 4.05V). When VCC is applied, pulling the TIMER/SHDN pin to ground will manually shut down the charger and reset the timer. When this pin is released an internal 7A current source pulls the TIMER/SHDN pin above the 0.82V shutdown threshold to resume charging. Fault conditions such as overheating of the die or excessive DRIVE pin or PROG pin current are monitored and limited. When input power is removed or manual shutdown is entered, the charger will drain only tiny leakage currents (<1A) from the battery, thus maximizing battery standby time. With VCC removed the external PNP base is connected to the battery by the charger. In manual shutdown the base is connected to VCC by the charger.
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APPLICATIO S I FOR ATIO
Undervoltage Lockout An internal undervoltage lockout (UVLO) circuit monitors the input voltage and keeps the charger in shutdown mode until VCC rises above the UVLO threshold (VUVLOI is typically 4.4V). Approximately 50mV of hysteresis is built in to prevent oscillation around the threshold level. In undervoltage lockout, battery drain current is very low (<1A) and supply current is approximately 40A. Undervoltage Charge Current Limiting The LTC4056 includes undervoltage charge current limiting that prevents full charge current until the input supply voltage reaches a threshold value (VUVCL). This feature is particularly useful if the LTC4056 is powered from a supply with long leads (or any relatively high output impedance). For example, USB powered systems tend to have highly variable source impedances (due primarily to cable quality and length). A transient load combined with such an impedance can easily trip the UVLO threshold and turn the charger off unless undervoltage charge current limiting is implemented. Consider a situation where the LTC4056 is operating under normal conditions and the input supply voltage begins to sag (e.g. an external load drags the input supply down). If the input voltage reaches VUVCL (approximately 170mV above the rising undervoltage lockout threshold, VUVLOI), undervoltage charge current limiting will begin to reduce the charge current in an attempt to maintain VUVCL at the VCC input of the IC. The LTC4056 will continue to operate at the reduced charge current until the input supply voltage is increased or voltage mode reduces the charge current further. Trickle Charge and Defective Battery Detection At the beginning of a charge cycle, if the battery voltage is low (below VTRIKL of about 2.8V) the charger goes into trickle charge mode reducing the charge current to approximately 2% of the full-scale current. If the low battery voltage persists for one quarter of the total charge time, the battery is assumed to be defective, the charge cycle is terminated and the CHRG pin output transitions from a strong pull-down to a 12A pull-down. To restart the
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charge cycle, simply remove the input voltage and reapply it or momentarily force the TIMER/SHDN pin to ground. Programming Charge Current When in the constant current mode, the full-scale charge current is programmed using a single external resistor between the PROG pin and ground, RPROG. The current delivered to the ISENSE pin (flowing from VCC through the internal 110m sense resistor) will be 915 times the current in RPROG. Because the LTC4056 provides a virtual 1V source at the PROG pin, the charge current is given by:
1V ICHRG = IPROG * 915 = * 915 or RPROG 1V RPROG = * 915 ICHRG
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Under trickle charge conditions, this current is reduced to approximately 2% of the full-scale value. The actual battery charge current (IBAT) is slightly lower than the expected charge current because the charger forces the emitter current and the battery charge current will be reduced by the base current. In terms of (IC/IB), IBAT can be calculated as follows:
915V IBAT A = 915 * IPROG * = + 1 RPROG + 1
()
If = 50, then IBAT is 2% low. If desired, reducing RPROG by 2% can compensate for the 2% loss. For example, if 700mA charge current is required, calculate:
1V RPROG = * 915 = 1.3k 700mA
If a low needs to be compensated for, say = 50, calculate:
RPROG =
915V 50 * = 1.27k 700mA 50 + 1
For best stability over temperature and time, 1% metalfilm resistors are recommended. 405642i
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APPLICATIO S I FOR ATIO
Termination Timer The programmable timer is used to terminate the charge cycle. The timer duration is programmed by an external capacitor at the TIMER/SHDN pin and the external PROG resistor. The total charge time is: Time(Hours) = 2.1 * RPROG(k) * CTIMER(F) or CTIMER(F) = Time(Hours)/2.1 * RPROG(k) For example, to program a three hour timer with a 640mA charge current (i.e., RPROG = 1.43k), calculate: C TIMER = 3 = 1F 2.1* 1.43
The timer starts when an input voltage greater than the undervoltage lockout threshold level is applied, a program resistor is connected to ground and the TIMER/SHDN pin is allowed to rise above the shutdown threshold. After a time-out occurs, the charge current stops and the CHRG output transitions from a strong pull-down to a 12A pulldown to indicate charging has stopped. As long as the input supply remains above VUVLOD and the battery voltage remains above VRECHRG the charger will remain in this standby mode. If the battery voltage remains below VTRIKL for 25% of the programmed time, the charger will enter standby mode. Furthermore, if the battery voltage is above the recharge threshold (VRECHRG is typically 4.05V) at the beginning of a charge cycle or if a falling battery voltage triggers a recharge cycle (following a previous time-out), the charger will enter standby mode after 50% of the programmed time. This feature reduces the charge time for batteries that are near full capacity. Connecting the TIMER/SHDN pin to VCC disables the timer function. Manual Shutdown Pulling the TIMER/SHDN pin below VMSDT - VMSHYS (typically 0.745V) will put the charger into shutdown mode. In this mode, the LTC4056 consumes 40A of supply current and drains a negligible leakage current from the battery (IBMS). A 7A current source pulls up on the TIMER/SHDN pin while in shutdown to ensure that the IC will start up once
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the TIMER/SHDN pin is released. Given the low magnitude of this current, it is a simple matter for an external opendrain (or open-collector) output to pull the TIMER/SHDN pin to ground for shutdown and release the pin for normal operation. Sleep Mode When the input supply is disconnected, the IC enters the sleep mode. In this mode, the battery drain current (IBSL) is a negligible leakage current, allowing the battery to remain connected to the charger for an extended period of time without discharging the battery. The leakage current is due to the reverse-biased B-E junction of the external PNP transistor. Furthermore, the CHRG pin assumes a high impedance state. CHRG Status Output Pin When the charge cycle starts, the CHRG pin is pulled to ground by an internal N-channel MOSFET capable of driving an LED. Upon termination, the strong pull-down transitions to a 12A pull-down on the CHRG pin as long as the input supply remains above the UVLO threshold (VUVLOD) and the battery voltage remains above VRECHRG. If the input supply falls below VUVLOD, the CHRG pin assumes a high impedance state. Figure 1 shows a flow diagram for a typical charge cycle. This diagram indicates the status of the CHRG pin in each charger state. A microprocessor can be used to distinguish the three states of the CHRG pin (see Figure 2). To detect whether the LTC4056 is in trickle charge, charge, or short charge mode (i.e., strong pull-down), force the digital output pin (OUT) high and measure the voltage at the CHRG pin. The internal N-channel MOSFET will pull the pin voltage low even with the 2k pull-up resistor. Once the charge cycle terminates, the strong pull-down transitions to a 12A pull-down. The IN pin will then be pulled high by the 2k pull-up resistor. To determine whether sufficient input voltage is present for charging (i.e., high impedance), the OUT pin should be forced to a high impedance state. If VCC > VUVLOI then the 12A CHRG pull-down will pull the IN pin low through the 800k resistor; otherwise, the 800k resistor will pull the IN pin high, indicating that VCC < VUVLOD.
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APPLICATIO S I FOR ATIO
POWER ON TIMER/SHDN RELEASED OR VCC > VUVLOI SHUTDOWN MODE ICC DROPS TO < 40A CHRG: Hi-Z if VCC < VUVLOD WEAK PULLDOWN OTHERWISE TIMER/SHDN GROUNDED OR VCC < VUVLOD
Figure 1. State Diagram for a Typical Charge Cycle
V+ 1 VCC LTC4056 CHRG 8 2k 800k PROCESSOR OUT IN
4056-4.2 F02
V DD
Figure 2. Using a Microprocessor to Determine CHRG State
Recharge If the battery voltage drops below VRECHRG (typically 4.05V) after a charge cycle has terminated, a new charge cycle will begin. The recharge circuit integrates the BAT pin voltage for approximately a millisecond to prevent a transient from restarting the charge cycle. During a recharge cycle the timer will terminate the charge cycle after one-half of the programmed time has elapsed. If the battery voltage remains below VTRIKL (typically 2.8V) during trickle charge for one-fourth of the programmed time, the battery may be defective and the charge cycle will end. In addition, the recharge comparator is disabled and a new charge cycle will not begin unless the input voltage is toggled off then on, or the TIMER/SHDN pin is momentarily pulled to ground.
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BAT < 2.8V TRICKLE CHARGE MODE 2% FULL CURRENT CHRG: STRONG PULLDOWN BAT > 2.9V CHARGE MODE FULL CURRENT CHRG: STRONG PULLDOWN PROGRAMMED TIME ELAPSES STANDBY MODE NO CHARGE CURRENT CHRG: WEAK PULLDOWN 2.8V < BAT < 4.05V RECHARGE/SHORT CHARGE MODE CHRG: STRONG PULLDOWN
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25% PROGRAMMED TIME ELAPSES BAT > 4.05V
2.8V < BAT < 4.05V
50% PROGRAMMED TIME ELAPSES
External PNP Transistor The external PNP pass transistor must have adequate beta, low saturation voltage and sufficient power dissipation capability (including any heat sinking, if required). To provide 700mA of charge current with the minimum available base drive of approximately 30mA requires a PNP beta greater than 23. If lower beta PNP transistors are used, more base current is required from the LTC4056. This can result in the output drive current limit being reached, or thermal shutdown due to excessive power dissipation. With low supply voltages, the PNP saturation voltage (VCESAT) becomes important. The VCESAT must be less than the minimum supply voltage minus the maximum voltage drop across the internal sense resistor and bond wires (0.20) and battery float voltage. If the PNP transistor cannot achieve the low saturation voltage required, base current will dramatically increase. This is to be avoided for a number of reasons: output drive may reach current limit resulting in the charger characteristics to go out of specifications, excessive power dissipation may force the IC into thermal shutdown, or the battery could become discharged because some of the current from the
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APPLICATIO S I FOR ATIO
DRIVE pin could be pulled from the battery through the forward biased collector base junction. For example, to program a charge current of 500mA with a minimum supply voltage of 4.75V, the minimum operating VCE is: VCE(MIN)(V) = 4.75 - (0.5) * (0.2) - 4.2 = 0.45V Another important factor to consider when choosing the PNP pass transistor is the power handling capability. The transistor data sheet will usually give the maximum rated power dissipation at a given ambient temperature with a power derating for elevated temperature operation. The maximum power dissipation of the PNP when charging is: PD(MAX)(W) = IBAT * (VCC(MAX) - VBAT(MIN)) VCC(MAX) is the maximum supply voltage and VBAT(MIN) is the minimum battery voltage when discharged. Once the maximum power dissipation and VCE(MIN) are known, Table 1 can be used as a guide in selecting some PNPs to consider. In the table, very low VCESAT is less than 0.25V, low VCESAT is 0.25V to 0.5V and the others are 0.5V to 0.8V all depending on the current. See the manufacturer data sheet for details. All of the transistors are rated to carry at least 1A continuously as long as the power dissipation is within limits. In addition, the maximum supply voltage, minimum battery voltage and chosen
Table 1. PNP Pass Transistor Selection Guide
MAXIMUM PD(W) MOUNTED ON BOARD PACKAGE STYLE ZETEX PART NUMBER AT TA = 25C 3 0.5 0.625 1 1.1 1 to 2 2 2 0.75 1 2 10 (TC = 25C) 2 x 2MLP SOT-23 SOT-23 SOT-89 SOT-23-6 SOT-89 SOT-223 SOT-223 FTR ATV SOT-89 TO-252 ZXT1M322 FMMT549 FMMT720 FCX589 or BCX69 ZXT13P12DE6 FCX717 FZT589 BCP69 or FZT549 2SB822 2SB1443 2SA1797 2SB1182 Low VCESAT Low VCESAT Low VCESAT Low VCESAT, High Beta
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charge current should be checked against the manufacturer's data sheet to ensure that the PNP transistor is operating within its safe operating area. The Stability section addresses caution in the use of very high beta PNPs. Should overheating of the PNP transistor be a concern, protection can be achieved with a positive temperature coefficient (PTC) thermistor wired in series with the current programming resistor and thermally coupled to the transistor. The PTH9C chip series from Murata has a steep resistance increase at temperature thresholds from 85C to 145C making it behave somewhat like a thermostat switch. For example, the model PTH9C16TBA471Q thermistor is 470 at 25C but abruptly increases its resistance to 4.7k at 125C. Below 125C, the device exhibits a small negative TC. The 470 thermistor can be added in series with a 976 resistor to form the current programming resistor for a 640mA charger. Should the thermistor reach 125C, the charge current will drop to 160mA and inhibit any further increase in temperature. Stability The LTC4056 contains two control loops: constant voltage and constant current. The constant voltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length,
ROHM PART NUMBER COMMENTS Very Low VCESAT Low VCESAT Very Low VCESAT, High Beta Very Low VCESAT, High Beta, Small Very Low VCESAT, High Beta Low VCESAT
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APPLICATIO S I FOR ATIO
however, may add enough series inductance to require a bypass capacitor of at least 1F from BAT to ground. Furthermore, a 4.7F capacitor with a 0.2 to 1 series resistor from BAT to ground is required to keep ripple voltage low when the battery is disconnected. High value capacitors with very low ESRs (especially ceramic) reduce the constant voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22F may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. In the constant current mode, the PROG pin is in the feedback loop, not the battery. Because of the additional pole created by PROG capacitance, capacitance on this pin must be limited. Although higher charge current applications (i.e., lower program resistance) can tolerate more PROG capacitance, a good rule of thumb is to keep the capacitive loading on the PROG pin to less than 660pF. If additional capacitance on this pin is required (e.g., to provide an accurate, filtered low current 1V reference to external circuitry) a 1k to 10k decoupling resistor may be needed (see Figure 3).
LTC4056 PROG 6 10k ACCURATE, FILTERED 1V REFERENCE
GND 4
RPROG
CFILTER
4056-4.2 F03
Figure 3. Isolating Capacitive Load on PROG Pin and Filtering
Reverse Polarity Input Voltage Protection In some applications, protection from reverse polarity voltage on VCC is desired. If the supply voltage is high enough, a series blocking diode can be used. In other cases, where the voltage drop must be kept low, a P-channel MOSFET can be used (as shown in Figure 4).
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* LTC4056 VIN VCC
4056-4.2 F04
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*DRAIN-BULK DIODE OF FET
Figure 4. Low Loss Input Reverse Polarity Voltage Protection
VCC Bypass Capacitor Many types of capacitors with values ranging from 1F to 10F located close to the LTC4056 will provide adequate input bypassing. However, caution must be exercised when using multilayer ceramic capacitors. Because of the self-resonant and high Q characteristics of some types of ceramic capacitors, high voltage transients can be generated under some start-up conditions, such as connecting the charger input to a hot power source. For more information refer to Application Note 88. Internal Protection Internal protection is provided to prevent excessive PROG pin currents (IPSHRT), excessive DRIVE pin currents (IDSHRT) and excessive self-heating of the LTC4056 during a fault condition. The faults can be generated from a shorted PROG pin, a shorted DRIVE pin or from excessive DRIVE pin current to the base of the external PNP transistor when it is in deep saturation from a very low VCE. This protection is not designed to prevent overheating of the external pass transistor. However, thermal coupling between the external PNP and the LTC4056 will allow the internal thermal limit to deprive the PNP of base current when the junction temperature of the IC rises above about 135C. The temperature of the PNP at that point, however, will be well in excess of 135C. The exact temperature of the PNP depends on the thermal coupling between the LTC4056 and the PNP and on the JA of the transistor. See the section titled "External PNP Transistor" for information on protecting the transistor from overheating.
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LTC4056-4.2
PACKAGE DESCRIPTIO U
TS8 Package 8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.65 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID 0.65 BSC 0.22 - 0.36 8 PLCS (NOTE 3) 0.80 - 0.90 0.20 BSC 1.00 MAX DATUM `A' 0.01 - 0.10 0.09 - 0.20 (NOTE 3) 1.95 BSC
TS8 TSOT-23 0302
0.52 MAX
3.85 MAX 2.62 REF
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.30 - 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
405642i
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LTC4056-4.2
RELATED PARTS
PART NUMBER LT1571 LTC1729 LTC1730 LTC1731 LTC1732 LTC1733 LTC1734 LTC1734L LTC4050 LTC4052 LTC4053 DESCRIPTION 200kHz/500kHz Switching Battery Charger Lithium-Ion Battery Charger Termination Controllers Lithium-Ion Battery Pulse Charger Lithium-Ion Linear Battery Charger Controller Charger Detection and Programmable Timer Lithium-Ion Linear Battery Charger Controller Monolithic Lithium-Ion Linear Battery Charger Lithium-Ion Linear Battery Charger in ThinSOT Lithium-Ion Linear Battery Charger Controller Lithium-Ion Linear Battery Charger Controller Lithium-Ion Linear Battery Pulse Charger USB Compatible Lithium-Ion Battery Linear Monolithic Charger Standalone Lithium-Ion Linear Battery Charger in ThinSOT USB Power Manager COMMENTS Up to 1.5A Charge Current; Preset and Adjustable Battery Voltages Time or Charge Current Termination, Preconditioning 8-Lead MSOP No Blocking Diode Required, Current Limit for Maximum Safety Simple Charger uses External FET, Features Preset Voltages, C/10 Simple Charger uses External FET, Features Preset Voltages, C/10 Charger Detection and Programmable Timer, Input Power Good Indication Standalone charger with Programmable Timer, Up to 1.5A Charge Current, Thermal Regulation Prevents Overheating 200mA to 700mA, Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed 50mA to 180mA, No Blocking Diode, No Sense Resistor Needed Simple Charger uses External FET, Thermistor Input for Battery Temperature Sensing Fully Integrated, Standalone Pulse Charger, Minimal Heat Dissipation, Over Current Protection Fully Integrated, Standalone Charger, 10-Lead MSOP, Thermal Regulation Prevents Overheating when Powered from Wall Adapter and 1A Charge Current Programmable Charge Current Up to 800mA; C/10 Charge Termination, Complete Charger; No External MOSFET, Diode or Sense Resistor Manages Total Power Between a USB Peripheral and Battery Charger; Ensures Simultaneous Charging and use of Peripheral, ThinSOT Package
LTC4054 LTC4410
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12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0203 1.5K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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