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Advance Product Information
July 14, 2005
X-Band Low Noise Amplifier
Key Features
* * * * * *
TGA2512
Typical Frequency Range: 5 - 15 GHz 1.4 dB Nominal Noise Figure 27 dB Nominal Gain Bias: 5 V, 160 mA Gate Bias 5 V, 90 mA Self Bias 0.15 um 3MI pHEMT Technology Chip Dimensions 2.05 x 1.20 x 0.10 mm (0.081 x 0.047 x 0.004 in)
Product Description
The TriQuint TGA2512 is a wideband LNA with AGC amplifier for EW, ECM, and RADAR receiver or driver amplifier applications. Offering high gain 27dB typical from 5-15GHz, the TGA2512 provides excellent noise performance with typical midband NF 1.4dB, while the balanced topology offers good return loss typically 15dB. The TGA2512 is designed for maximum ease of use. The large input FETs can handle up to 21dBm input power reliably, while the build-in gain control provides 15dB of typical gain control range. The part is also assembled in self-biased mode, using a single +5V supply connection from either side of the chip, or in gate biased mode, allowing the user to control the current for a particular applications. In self-biased mode the TGA2512 offers 6dBm typical P1dB, while in gate-biased mode the typical P1dB is over 13dBm. The small size of 2.46mm2 allows ease of compaction into MultiChip-Modules (MCMs). The TGA2512 is 100% DC and RF tested onwafer to ensure performance compliance. Lead-Free & RoHS compliant.
Noise Figure (dB)
Primary Applications
* * * X-Band Radar EW, ECM Point-to-Point Radio
Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA
40 30 S-Parameter (dB) 20 10 0 -10 -20 -30 -40 5
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 5 6 7 8 9 10 11 12 13 14 15 Frequency (GHz)
GAIN
IRL ORL
6 7 8 9 10 11 12 13 14 15
Frequency (GHz)
Note: Devices is early in the characterization process prior to finalizing all electrical specifications. Specifications are subject to change without notice
1
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July 14, 2005
TGA2512
TABLE I MAXIMUM RATINGS 1/ SYMBOL
Vd Vg Id Ig PIN PD TCH TM TSTG 1/ 2/ 3/ 4/ 5/ Drain Voltage Gate Voltage Range Drain Current (gate biased) Gate Current Input Continuous Wave Power Power Dissipation Operating Channel Temperature Mounting Temperature (30 Seconds) Storage Temperature
PARAMETER
VALUE
[3.5 + (0.0125)(Id)] V -1 TO +0.5 V 240 mA 7.04 mA 21 dBm See Note 5/ 117 C 320 0C -65 to 150 0C
0
NOTES
2/ 3/
2/ 4/ 4/
2/ 6/ 7/
These ratings represent the maximum operable values for this device. Combinations of supply voltage, supply current, input power, and output power shall not exceed P D. Unit for Id is A Total current for the entire MMIC. For a median life time of 1E+6 hrs, Power dissipation is limited to: PD(max) = (117 0C - TBASE 0C) / JC (0C/W) Where TBASE is the base plate temperature. JC for self bias is 35.5 0C/W JC for gate bias is 35.0 0C/W
6/
Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum life, it is recommended that junction temperatures be maintained at the lowest possibl levels. These ratings apply to each individual FET.
7/
TABLE II DC PROBE TESTS (Ta = 25 0C, Nominal) SYMBOL
VBVGS, Q1 VP, Q1,2,4,5,6
PARAMETER
Breakdown Voltage GateSource Pinch-Off Voltage
MIN.
-30 -0.7
TYP.
MAX.
-5 -0.1
UNITS
V V
Q1, Q4, Q5 are 400 um FETs. Q2, Q6 are 300 um FETs.
2
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July 14, 2005
TGA2512
TABLE III ELECTRICAL CHARACTERISTICS (Ta = 25 0C Nominal)
PARAMETER
Frequency Range Drain Voltage, Vd Drain Current, Id Gate Voltage, Vg Small Signal Gain, S21 Input Return Loss, S11 Output Return Loss, S22 Noise Figure, NF Output Power @ 1dB Gain Compression, P1dB OIP3
Gate Bias
5 - 15 5.0 160 -0.1 27 15 20 1.4 13 24
Self Bias
5 - 15 5.0 90 24 15 20 1.4 6 16
UNITS
GHz V mA V dB dB dB dB dBm dBm
TABLE IV THERMAL INFORMATION
PARAMETER TEST CONDITIONS Vd = 5 V Id = 160 mA Gate Bias Pdiss = 0.80 W Vd = 5 V Id = 90 mA Self Bias Pdiss = 0.45 W TCH (OC) 100 TJC (qC/W) 37.6 TM (HRS) 5.8E+6
TJC Thermal Resistance (channel to Case)
TJC Thermal Resistance (channel to Case)
82.7
28.2
4.1E+7
Note: Assumes eutectic attach using 1.5 mil 80/20 AuSn mounted to a 20 mil CuMo Carrier at 70oC baseplate temperature. Worst case condition with no RF applied, 100% of DC power is dissipated.
3
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July 14, 2005
Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA
TGA2512
34 32 30 28 G ain (dB) 26 24 22 20 18 16 14 4
5.0 4.5 4.0 Noise Figure (dB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Frequency (GHz)
4
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July 14, 2005
TGA2512 Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA
0 -5 Input Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 -50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
0 -5 O utput Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 -50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
5
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July 14, 2005
TGA2512 Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA
16 14 12 P1dB (dBm) 10 8 6 4 2 0 6 7 8 9 10 11 12 13 14 15 16 Frequency (GHz)
28 26 24 22 OIP3 (dBm) 20 18 16 14 12 10 8 6 7 8 9 10 11 12 13 Frequency (GHz)
6
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July 14, 2005
TGA2512 Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA Over Temperature
35 30 Gain Over Temperature (dB) 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz)
-40C +25C +70C
7
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July 14, 2005
TGA2512 Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA
34 32 30 28 Gain (dB) 26 24 22 20 18 16 14
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
5.0 4.5 4.0 Noise Figure (dB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
8
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July 14, 2005
Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA
TGA2512
0 -5 -10
Input Return Loss (dB)
-15 -20 -25 -30 -35 -40 -45 -50
4
5
6
7
8
9
10 11 12 13 Frequency (GHz)
14
15
16
17
18
0 -5 -10 Output Return Loss (dB) -15 -20 -25 -30 -35 -40 -45 -50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency (GHz)
9
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July 14, 2005
TGA2512 Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA
16 14 12 P1dB (dBm) 10 8 6 4 2 0 6 7 8 9 10 11 12 13 14 15 16 Frequency (GHz) 28 26 24 22 OIP3 (dBm) 20 18 16 14 12 10 8 6 7 8 9 10 11 12 13 Frequency (GHz)
10
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July 14, 2005
Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA Over Temperature
TGA2512
30
25 Gain Over Temperature (dB)
20
15
10
5
-40C +25C +70C
0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz)
11
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July 14, 2005
Measured Fixtured Data
Self Biased variation over Vctrl
TGA2512
30
Vctrl=0 v Vctrl=3V Vctrl=3.2V Vctrl=3.5V Vctrl=4 V Vctrl=5 V Vctrl=6V
25
20 Gain (dB)
15
10
5
0 2 4 6 8 10 12 14 16 18 Frequency (GHz)
5.0 4.5 4.0 Noise Figure (dB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 4 6 8 10 Frequency (GHz) 12 14 16 18
Vctrl=0V Vctrl=2V Vctrl=2.25V Vctrl=2.5V Vctrl=2.75V Vctrl=3V Vctrl=3.5V Vctrl=4V Vctrl=5V
12
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July 14, 2005
TGA2512
Mechanical Drawing
0.095 (0.004) 0.642 (0.025) 0.914 (0.036) 1.086 (0.043) 1.327 (0.052) 1.755 (0.069)
1.200 (0.047)
2
3
4
5
6
1.105 (0.044)
RC
B
RC
B
NE
0.145 (0.006) 0.095 (0.004) 0
1
13
12
11
10
9
8
7
0.145 (0.006)
0
0.642 (0.025)
0.914 (0.036)
1.086 (0.043)
1.327 (0.052)
1.675 1.815 1.955 2.050 (0.060) (0.072) (0.077) (0.081)
Units: millimeters (inches) Thickness: 0.100 (0.004) Chip edge to bond pad dimensions are shown to center of bond pad Chip size tolerance: +/- 0.051 (0.002) GND is back side of MMIC Bond pad #1 Bond pad #2, 3, 8, 12, 13 Bond pad #4, 11 Bond pad #5, 10 Bond pad #6, 9 Bond pad #7 (RF In) (Vs) (Vg) (Vctrl) (Vd) (RF Out) 0.100 x 0.200 (0.004 x 0.008) 0.100 x 0.100 (0.004 x 0.004) 0.100 x 0.100 (0.004 x 0.004) 0.100 x 0.100 (0.004 x 0.004) 0.100 x 0.100 (0.004 x 0.004) 0.100 x 0.200 (0.004 x 0.008)
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
13
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July 14, 2005
TGA2512
Recommended Chip Assembly Diagram
Option 1: Self Bias - No Gain Control
Vd
100pF
RF In
RF Out
All DC connections may be brought in from either side of the chip (Use Pad 6 or 9) 0.01uF external Cap is recommended on Drain Bias: Vd = 5V (Id = ~90mA)
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
14
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July 14, 2005
TGA2512
Recommended Chip Assembly Diagram (Con't)
Option 2: Self Bias - With Gain Control
Vctrl
Vd
100pF 100pF
RF In
RF Out
All DC connections may be brought in from either side of the chip (Use Pad 5 or 10, and Pad 6 or 9) 0.01uF external Caps are recommended on Drain line Bias: Vd = 5V (Id = ~90mA), Vctrl = 0 to +5V for Gain adjustment
15
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July 14, 2005
TGA2512
Recommended Chip Assembly Diagram (Con't)
Option 3: Gate Bias - With Gain Control
Vg
Vctrl
Vd
100pF 100pF 100pF
RF In
RF Out
All DC connections may be brought in from either side of the chip (Use Pad 4 or 11, Pad 5 or 10, and Pad 6 or 9) 0.01uF external Caps are recommended on Drain, Gate line, 10 ohm external series R between 100pF cap and 0.01uF cap is recommended for Gate line Source connections (Pad 2, 3, 8, 12, 13) are bonded to ground Bias: Vd = 5V , Vctrl = 0 to +5V for Gain adjustment Vg = Range, -0.5 to 0, typically ~ -0.1 will provide ~160mA of Id.
16
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July 14, 2005
TGA2512
Equivalent DC schematic
17
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July 14, 2005
TGA2512 Assembly Process Notes
Reflow process assembly notes: * * * * * Use AuSn (80/20) solder with limited exposure to temperatures at or above 300 C (30 seconds max). An alloy station or conveyor furnace with reducing atmosphere should be used. No fluxes should be utilized. Coefficient of thermal expansion matching is critical for long-term reliability. Devices must be stored in a dry nitrogen atmosphere.
0
Component placement and adhesive attachment assembly notes: * * * * * * * Vacuum pencils and/or vacuum collets are the preferred method of pick up. Air bridges must be avoided during placement. The force impact is critical during auto placement. Organic attachment can be used in low-power applications. Curing should be done in a convection oven; proper exhaust is a safety concern. Microwave or radiant curing should not be used because of differential heating. Coefficient of thermal expansion matching is critical.
Interconnect process assembly notes: * * * * Thermosonic ball bonding is the preferred interconnect technique. Force, time, and ultrasonics are critical parameters. Aluminum wire should not be used. 0 Maximum stage temperature is 200 C.
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test.
18
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