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SPCA711A
DIGITAL VIDEO ENCODER FOR VIDEOCD GENERAL DESCRIPTION
The SPCA711A is designed specifically for VideoCD, video games and other digital video systems, which require the conversion of digital YCrCb (MPEG) data to analog NTSC/PAL video. less interface to most popular MPEG decoders. The device supports a glue-
The SPCA711A supports worldwide video standards, including
NTSC (N America, Japan) PAL-B, D, G, H, I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), and PAL-Nc (Argentina). single 3.3V supply. Furthermore, the SPCA711A operates with a single 2x clock and can be powered with a The composite analog video signal is output simultaneously onto two outputs. Therefore,
it allows one output to provide base-band composite video while the other drives a RF modulator.
Alternatively, As a
analog luminance (Y) and chrominance (C) information is available for interfacing to S-video equipment.
slave, the SPCA711A automatically detects the input data formats (PAL/NTSC, CCIR601) and switches internally to provide the proper format on the outputs. This feature, along with the on-board voltage reference In addition, use of 2x over-sampling
and single clock interface, makes the SPCA711A extremely simple to use.
on-chip simplifies external filter design resulting in reduced overall system cost.
FEATURES
! 8-bit 4:2:2 YCrCb inputs for glue-less interface to MPEG decoders ! NTSC/PAL/PAL-M/PAL-Nc composite video outputs
BLOCK DIAGRAM
VBIAS VREFOUT FSADJUST
CLK
! CVBS or S-video outputs ! 3.3 V supply voltage ! CCIR 601 operation ! 2x over sampling simplifies external filtering ! 9-bit DACs ! Master or slave video timing ! Interlaced operation
MODE[3:0] MASTER P[7:0]
Internal VREF
COMP
VRDAC
9 DAC 2x Upsample Latch 1.3MHz LPF VSYNC* Mod. and Mixer 9 DAC CVBS/C CVBS/Y
HSYNC*
CBSWAP
SVIDEO
SLEEP
! Automatic mode detection/switching in slave mode ! On-board voltage reference ! 27MHz crystal oscillator input ! 32-pin PLCC package
APPLICATIONS
! VideoCD ! Karaoke/video games ! Digital Video Disk (DVD) ! Digital VCR ! Digital set top box

SPCA711A
PINOUT and DESCRIPTION
HSYNC VSYNC CVBSY DGND 30 AGND TEST
32
31
4
3
2
1
VDD
FSADJUST COMP VAA VREFOUT VREFIN VBIAS CVBSC AGND SLEEP
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
29 28 27 26 25 24 23 22 21 20
CLKOUT DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
CBSWAP
SVIDEO
CLK
MODEA
(Table 1.)
Mnemonic DATA[7:0] PIN No. 21 - 28 Type I YCrCb pixel inputs. Description They are latched on the rising edge of CLK.
MASTER
YCrCb input data conform to CCIR 601. CLKOUT VSYNC 29 32 O I/O Pixel clock output Vertical sync input/output. edge of CLK. HSYNC 1 I/O Horizontal sync input/output. rising edge of CLK. MASTER 16 I Master/slave mode selection. operation. CBSWAP 15 I A logical high for master mode HSYNC is latched/output following the VSYNC is latched/output following the rising
MODEB
A logical 0 for slave mode operation. A logic high swap the
Cr and Cb pixel sequence configuration pin.

XTALO
SPCA711A
Mnemonic PIN No. Type Cr and Cb sequence. SVIDEO 14 I SVIDEO select input pin. A logic high selects Y/C output. A logic low Description
selects composite video output. SLEEP 13 I Power save mode. A logic high on this pin puts the chip into power-
down mode. This pin is equal to reset pin. An external logic high pulse should input to the pin when power on. MODEA MODEB CLK 17 18 19 I I I Mode configuration pin. Mode configuration pin. 27MHz crystal oscillator input. A crystal with 27MHz clock frequency can be connected between this pin and XTALO. XTALO TEST VREFIN 20 2 9 O I I Crystal oscillator output. Test pin. These pins must be connected to DGND. Voltage reference input. typical 1.235V to this pin. An external voltage reference must supply A 0.1F ceramic capacitor must be used to The decoupling capacitor must be as This pin may be
de-couple this input to GND.
closed as possible to minimize the length of the load. connected directly to VREFOUT. VREFOUT 8 O Voltage reference output.
It generates typical 1.2V voltage reference
and may be used to drive VREFIN pin directly. FSADJ 5 Full-Scale adjust control pin. The Full-Scale current of D/A converters
can be adjusted by connecting a resistor (RSET) between this pin and ground. COMP 6 Compensation pin. A 0.1F ceramic capacitor must be used to bypass
this pin to VAA. The lead length must be kept as short as possible to avoid noise. VBIAS VDD DGND CVBSY 10 31 30 4 O DAC bias voltage. Digital power pin Digital ground pin Composite/Luminance output. output. CVBSY can drive a 37.5 load. CVBSC 11 O Composite/Chroma output. Output. can drive a 37.5 load.
This is a high impedance current source The pin This is a high-impedance current source The Potential normally 0.7V less than COMP.
The output format can be selected by the PAL pin.
The output format can be selected by the PAL pin.
SPCA711A
Mnemonic VAA AGND PIN No. 7 3,12 Type Analog power pin Analog ground pin Description
MODE SELECTION
The master mode is selected when MASTER = 1; slave mode is selected when MASTER = 0. MODEA, MODEB, drive three different configuration registers. selected with these pins while in the master mode. Two pins, The most common operating modes can be
In the slave mode, as well as the common operating modes,
are automatically determined from the timing of the incoming HSYNC* and VSYNC* signals.
NOTE: The term "common operating mode" refers to the North American NTSC and Western European PAL. Table 2 illustrates the multi-functionality of the mode pins in the master and slave mode. To access the more exotic video If the master mode is
formats, slave mode is preferred since the necessary registers are always accessible.
needed, the less common modes can still be programmed by first registering the modes as slave and then switching to a master. written. During power-up, the MODE [3:2] pins configure the master registers, i.e., EFIELD and PAL625 are
Also, during power-up, the slave registers are reset to zero, i.e., YCSWAP.
Table 2. Mode Selection
PIN Description The MASTER pin 0 1 MODEA YCSWAP EFIELD MODEB PALSA PAL625

SPCA711A
Table 3. Configuration Register Settings
Mode Register Name EFIELD Set to 0 The VSYNC pin will output normal vertical synchronization signals. Set to 1 The VSYNC pin will output field signals. Low at the VSYNC pin for an even field, high for odd field. PAL625 The 525-line operation will be selected. YCSWAP Do not swap Y and Cr/Cb Sequence. PALSA When the PAL625 register is set to high, the PALBDGHI mode is selected. When the PAL625 register is set to low, the NTSC mode is selected. The 625-line operation will be selected Swap Y and Cr/Cb sequence. When the PAL625 register is set to high, the PAL-Nc mode is selected. When the PAL625 register is set to low, the PAL-M mode is selected. --This is only used master mode ---in the Comments This is only used in the master mode.
CLOCK TIMING
A clock signal with a frequency of twice the luminance sampling rate must be present at the CLK pin. and hold timing specifications are measured with respect to the rising edge of this signal. All setup
PIXEL INPUT TIMING ! PIXEL SEQUENCE
Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs. By default, the input sequence for active This pattern video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656.
begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER mode). Cb and Cr order can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing. If the
pixel stream input to the SPCA711A is off by one CLK period, the SPCA711A can lock to the pixel stream by setting the YCSWAP register. This will prevent Y and Cr/Cb pixels from swapping.

SPCA711A
Figure 1. Pix Sequence
CBSWAP (1)
CLK (2) HSYNC* (3)
0
P[7:0]
Cbn
Yn
Crn
Yn + 1
Cbn+2
1
P[7:0]
Crn
Yn
Cbn
Yn + 1
Crn+2
Notes: (1). CBSWAP is pin 11. (2). Pixel transitions must occur observing setup and hold timing about the rising edge of CLK. (3). Pixel sequence will beging with Cbn at 4 x m clock periods following the falling edge of HSYNC*, when m is an integer.

SPCA711A
VIDEO TIMING
The width of analog horizontal sync pulses and the start and end of color burst is automatically calculated and inserted for each mode according to CCIR-624-4. Color burst is disabled on appropriate scan lines. In addition, rise and fall times of
Serration and equalization pulses are generated on appropriate scan lines. sync, and the burst envelope are internally controlled. section.
Video timing figures follow the guidelines given in this
! SYNC AND BURST TIMING
Table 4 lists the resolutions and clock rates for the various modes of operation. Table 5 lists the horizontal counter values for the end of horizontal sync, start of color burst, end of color burst, front porch, back porch, and the first active pixel for the various modes of operation. The front porch is the The horizontal sync The start of color
interval before the next expected falling HSYNC* when outputs are automatically blanked.
width is measured between the 50% points of the falling and rising edges of horizontal sync.
burst is measured between the 50% point of the falling edge of horizontal sync and the first 50% point of the color burst amplitude (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I, Nc above the blanking level). The end of color burst is measured between the 50% point of the falling edge of horizontal sync and the
last 50% point of the color burst envelope (nominally +20 IRE for NTSC and 150 mV for PAL-B, D, G, H, I, Nc above the blanking level).
Table 4. Field Resolutions and Clock Rates for Various Modes of Operation
Operating Mode NTSC/PAL-M CCIR601 PAL-B,D,G,H,I, Nc Active pixels 720 x 240 720 x 288 Total Pixels 858 x 262 864 x 313 CLK Frequency (MHz) 27 27
Table 5. Horizontal Counter Values for Various Video Timings
Operation Mode Front porch (a) NTSC CCIR601 PAL-B CCIR601 20 20 Horizontal Sync Width (b) 63 63 Start of Burst (c) 72 76 Duration of Burst (d) 34 30 Back porch (e) 127 142
Notes: (1) The unit are in number of luminance pixels.
!
SPCA711A
! MASTER MODE
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal timing and optional software bits. HSYNC*, and VSYNC* are output following the rising edge of CLK. The horizontal counter is
incremented on every other rising edge of CLK.
After reaching the appropriate value (determined by the mode The vertical counter is incremented at the start
of operation), it is reset to one, indicating the start of a new line. of each new line.
After reaching the appropriate value, determined by the mode of operation, it is reset to one, VSYNC* is asserted for 3 or 2.5 scan lines for the 262/525 line and the
indicating the start of a new field. 312/625 line, respectively.
! SLAVE MODE
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are inputs that are registered on the rising edge of the CLOCK. The horizontal counter is incremented on the rising edge of the CLOCK. Two clock cycles after The vertical counter is
falling edge of HSYNC*, the counter is reset to one, indicating the start of a new line. incremented on the falling edge of HSYNC*. new field.
A falling edge of VSYNC* resets it to one, indicating the start of a
A falling edge of VSYNC* occurring within 1/4 of a scan line from the falling edge of HSYNC* cycle A falling edge of VSYNC* occurring within 1/4 scan line
time (line time) indicates the beginning of Field 1.
from the mid-point of the line indicates the beginning of Field 2.
The operating mode (NTSC/PAL) can be programmed with the MODEA and MODEB bits when the SETMODE (MASTER pin) bit is set high. changed to the slave mode. Alternatively, when the SETMODE bit is set low, the mode is automatically For example, 525-line operation is assumed, 625-line operation is detected by The frequency of operation (CCIR-601) for both PAL The pixel rate is assumed to be 13.5 MHz, 1
the number of HSYNC* edges between VSYNC* edges.
and NTSC is detected by counting the number of clocks per line. count and is between two successive falling edges of HSYNC*.
! BURST BLANKING
For NTSC, color burst information is automatically disabled on scan lines 1-9 and 264-272, inclusive(SMPTE line numbering convention). For PAL-B, D, G, H, I, Nc color burst information is automatically disabled on scan During fields 3, 4, 7, and 8, color burst
lines 1-6, 310-318, and 623-625, inclusive, for fields 1, 2, 5, and 6.
information is disabled on scan lines 1-5, 311-319, and 622-625, inclusive.
"
SPCA711A
VERTICAL BLANKING INTERVALS NTSC scan lines 1-9 and 263-272, inclusive, are always blanked. 273-284, inclusive. There is no setup on scan lines 10-21 and
All displayed lines in the vertical blanking interval (10-21 and 273-284 for interlaced NTSC; For PAL-B, D, G, H, I, scan lines 1-6, During fields 3, 4, 7, and 8,
7-13 and 320-335 for interlaced PAL-B, D, G, H, I) are forced to blank.
311-318, and 624-625, inclusive, during fields 1, 2, 5, and 6, are always blanked. scan lines 1-5, 311-319, and 624-625, inclusive, are always blanked.
! DIGITAL PROCESSING
Once the input data is converted into internal YUV format, the UV components are low-pass filtered with a filter. The Y and filtered UV components are up-sampled to CLK frequency by a digital filter.
! SUBCARRIER GENERATION
To maintain a synchronous sub-carrier relative to HSYNC*, the sub-carrier phase is reset every frame of theNTSC and every 8 fields of thePAL. the video format. For perfect clock input, the burst frequency is 4.43361875 MHz for PAL-B, D, G, H, I, 3.57561149MHz for PALM, 3.58205625MHz for PAL-Nc (Argentina), 3.579545 MHz for NTSC interlaced. The SCA phase is non-zero and depends upon the clock frequency and
! POWER-DOWN MODE
In the power-down mode (SLEEP pin set to 1), the internal clock is stopped, an internal reset is forced, and the DACs are powered down. When returned to low, the device starts from a reset state (horizontal and vertical This mode should be set when the SPCA711A is If Master = 1, the HSYNC* and VSYNC* pins
counters = 0, which is the start of VSYNC in Field 1).
subjected to clock frequencies outside its functional range.
remain driven to the value of previous output before SLEEP was activated. Power down current is dependent on loading to the HSYNC* and VSYNC* pins.
#
SPCA711A
Figure 2. Interlaced 525-Line (NTSC) Video Timing
Start of YSYNC
Analog Field 1
523
524
525
1
2
3
4
5
6
7
8
9
10
22
Burst Phase Analog Field 2
261
262
263
264
265
266
267
268
269
270
271
272
285
Analog Field 3
523
524
525
1
2 Analog Field 4
3
4
5
6
7
8
9
10
22
Burst Phase
261
262
263
264
265
266
267
268
269
270
271
272
285
Burst Begins with Positive Half-Cycle Burst Phase = Reference Phase = 1800 Relative to B-Y Burst Begins with Negative Half-Cycle Burst Phase = Reference Phase = 1800 Relative to B-Y Note: SMPTE line numbering convention rather than CCIR-624 is used.

SPCA711A
Figure 3a. Interlaced 625-Line (PAL) Video Timing
Start of VSYNC
Analog Field 1
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
-U Phase Analog Field 2
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 3
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
Analog Field 4
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Field One Burst Blanking Intervals Field Two Field Three Field Four
Burst Phase = Reference Phase = 1350 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 0 = 2250 Relative to U PAL Switch = 1, -V Component

SPCA711A
Figure 3b. Interlaced 625-Line (PA L) Video Timing
Start of VSYNC
Analog Field 5
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
-U Phase Analog Field 6
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Analog Field 7
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
Analog Field 8
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
Field Five Burst Blanking Intervals Field Six Field Seven Field Eight
Burst Phase = Reference Phase = 1350 Relative to U PAL Switch = 0, + V Component Burst Phase = Reference Phase + 90 0 = 2250 Relative to U PAL Switch = 1, -V Component

SPCA711A
ELECTRICAL CHARACTERISTICS ! Absolute Maximum Ratings
Parameter Power Supply (Measured to ground) Ambient Operating temperature Voltage on Any Signal Pin Storage Temperature Junction Temperature TS TJ -65 +150 +150 C C GND-0.5 VAA+0.5 V TA -40 +125 C Symbol VAA Min. Tpy. Max. 4.5 Unit V
Note: This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any pin that exceeds the power supply voltage by more than +0.5V can cause destructive latch-up.
! Recommended Operating Conditions
Parameter Power Supply Ambient Operating temperature DAC Output Load External Voltage Reference RL VREFIN -37.5 1.27 - V Symbol VAA TA Min. 3 0 Tpy. 3.3 -Max. 3.6 +70 Unit V C
! DC Characteristics
Characteristics Analog Power Operating Voltage Digital Power Operating Voltage Operating Current
Limit Min Typ 3.3 3.3 90 Max 3.6 3.6 300 3.0 3.0
Unit V V mA
VAA VDD IOP

SPCA711A
Power Down Mode Current Input High Voltage (Digital Input ) Input Low Voltage (Digital Input) Output High I (VOH=2.4V) (Digital Output) Output Sink I (VOL=0.8V) (Digital Output) VREFOUT Output Voltage VREFOUT Current VIH VIL IOH IOL
VREFOUT
20 2.0 GND-0.5 -8 8 1.27 10 VAA+0.5 0.8
mA V V mA mA V uA
IREFOUT
PIXEL INPUT RANGES AND COLORSPACE CONVERSION ! YC INPUTS (4:2:2 YCRCB)
Y has a nominal range of 16-235. Cb and Cr have a nominal range of 16-240, with 128 equal to zero. Y values of 0-15 and 236-255 are interpreted as 16 and 235. CrCb values of 1-15 and 241-254 are interpreted as 16 and 240.
! DAC CODING
White is represented by DAC code 800. represented by DAC code 252. For PAL-B, D, G, H, I, and Nc the standard blanking level is NTSC standard blanking level is represented by DAC code240.
OUTPUTS
All digital-to-analog converters are designed to drive standard video levels into an equivalent 37.5 load. Either two composite video outputs or Y/C S-Video outputs are available (selectable by the SVIDEO pin). SLEEP pin is high, the DACs are essentially turned off and only leakage current is present. If the
COMPOSITE AND LUMINANCE (CVBS/Y)ANALOG OUTPUT
When SVIDEO is a logical zero, digital composite video information drives the 9-bit D/A converter that generates the CVBS output. When SVIDEO is a logical one, digital luminance information drives the DAC that generates
the analog Y video output.

SPCA711A
! COMPOSITE AND CHROMINANCE (CVBS/C) ANALOG OUTPUT
When SVIDEO is a logical zero, digital composite video information drives the 9-bit D/A converter that generates CVBS output. When SVIDEO is a logical one, digital chrominance information drives the 9-bit D/A converter
that generates analog C video output.
PC BOARD CONSIDERATIONS
The layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical to eliminate digital switching noise. The ground
plane must provide a low-impedance return path for the digital circuits.
A PC board with a minimum of four
layers is recommended, with layers 1 (top) and 4 (bottom) for signals and layers 2 and 3 for ground and power, respectively.

SPCA711A
! COMPONENT PLACEMENT
Components should be placed as close as possible to the associated pin. The optimum layout enables the SPCA711A to be located as close as possible to the power supply connector and the video output connector.
! POWER AND GROUND PLANES
For optimum performance, a common digital and analog ground plane is recommended. analog power planes are recommended. Separate digital and The digital power plane should provide power to all digital logic on the
PC board, and the analog power plane should provide power to all SPCA711A power pins, VREF circuitry, and COMP decoupling. plane. At least a 1/8-inch gap is required in between the digital power plane and the analog power
The analog power plane should be connected to the digital power plane (VCC) at a single point through This bead should be located within 3 inches of the
a ferrite bead, as illustrated in Figure 4, Table 6. SPCA711A.
The bead provides resistance to switching-currents, acting as a resistance at high frequencies.
A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF454001.

SPCA711A
Figure 4. Typical Connection Diagram (Internal Voltage Reference)
Analog Power Plane SPCA711A VAA C4 C2,C3 COMP VREFIN VREFOUT C5 Ground (Power Supply Connector) Y/C 75 RF Mod To Video Connector CVBS/C P LPF Buffer 75K RF Audio 75 CVBS/Y 2.0K L1 +3.3V (VCC) VCC
GND RESET
FSADJUST
Schottky Diodes To Filter Schottky Diodes GND 22pF 75 1k Regulated +5V
DAC Output
LPF 22pF
75
10 H
1.8 H
1.8 H 330pF 82
RF Modulator (1) ZIN = 1K
270pF
330pF
270pF
TRAP
Notes: (1). Some modulators may require AC coupling capacitors (10F). (2). Optional for chroma boost. (3). VREFIN must be connected to either VREFOUT or VBIAS.
!
3.3K
C6
C1
SPCA711A
Table 6. Typical Parts List (Internal Voltage Reference)
Locations C5 - 1, C7 C6 L1 L2, L3 RESET TRAP Description 0.1 F Ceramic Capacitor 47 F Capacitor Ferrite Bead - Surface Mount Ferrite Bead(z < 300 @ 5MHz) 1% Metal Film Resistor Ceramic Resonator Vendor Part Number Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743021447 ATC LCB0805, Taiyo Yuden BK2125LM182 Dale CMF-55C Murata TPSx.xMJ or MB2 (where x.x = sound carrier frequency in MHz) Schottky Diodes BAT85 (BAT54F Dual) HP 5082-2305 (1N6263) Siemens BAT 64-04 (Dual)
Note: Vendor numbers are listed only as a guide. SPCA711A performance. Substitution of devices with similar characteristics will not affect
"
SPCA711A
PACKAGE INFORMATION
Model Number SPCA711A
Package 32-pin PLCC
Ambient Temperature Range 0- 70
NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product
#
SPCA711A
inches Symbol Min. A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne 0.1 0.06 0.013 0.026 0.485 0.447 0.39 0.585 0.547 0.49 Typ. 0.05 Max. 0.14 0.09 0.02 0.03 0.49 0.45 0.43 0.59 0.55 0.53 Min. 2.54 1.52 0.33 0.66 12.3 11.3 9.91 14.8 13.8 12.5 -
mm Typ. 1.27 32 7 9 Max. 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.1 13.46 -
DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by
description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS SUNPLUS reserves the right to halt production or alter the specifications and prices at Accordingly, the reader is cautioned to verify that the data sheets and other information Products described herein are intended for use in normal
FOR ANY PURPOSE. any time without notice.
in this publication are current before placing orders. commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military
equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for

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