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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9447/D Rev 1, 05/2002
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Features * 9 LVCMOS Compatible Clock Outputs
MPC9447
* * * *
2 Selectable, LVCMOS Compatible Inputs Maximum Clock Frequency of 350 MHz Maximum Clock Skew of 150 ps
LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:9 CLOCK FANOUT BUFFER
Synchronous Output Stop in Logic Low State Eliminates Output Runt Pulses * High-Impedance Output Control
* * * * *
3.3V or 2.5V Power Supply Drives up to 18 Series Terminated Clock Lines Ambient Temperature Range -40_C to +85_C 32 Lead LQFP Packaging
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Supports Clock Distribution in Networking, Telecommunications, and Computer Applications * Pin and Function Compatible to MPC947
Functional Description MPC9447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50W terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of -40_C to +85_C. The MPC9447 is pin and function compatible but performance-enhanced to the MPC947.
(c) Motorola, Inc. 2002
MPC9447
GND GND GND 17 16 15 14 13 GND Q6 VCC Q7 GND Q8 VCC GND 12 11 10 9 1 2 3 4 5 6 7 8 1 CLK1 input selected Outputs enabled Outputs active GND Condition Per output Inputs VCC VCC 18 Unit V V V mA 10 4.0 pF pF VCC Q3 Q4 Q5 19 OE
Q0 CCLK0 CCLK1 VCC 0 1 CLK STOP 24 Q1 GND Q2 Q3 CLK_SEL VCC SYNC Q6 VCC GND Q7 VCC (all input resistors have a value of 25kW) CLK_SEL CCLK0 CCLK1 Max GND OE CLK_STOP Q8 31 32 Q4 Q5 CLK_STOP Q1 GND Q0 28 Q2 VCC 25 26 27 23 22 21 20
MPC9447
29 30
Figure 1. Logic Diagram
Figure 2. 32-Lead Pinout (Top View)
Table 1. Function Table
Control CLK_SEL OE CLK_STOP Default 1 1 1 CLK0 input selected Outputs disabled (high-impedance state)a Outputs synchronously stopped in logic low state 0
a. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP
Table 2. Pin Configuration
Pin CCLK0 CCLK1 CLK_SEL CLK_STOP OE Q0-8 GND VCC I/O Input Input Input Input Input Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Clock signal input Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high-impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
Table 3. General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 Min Typ VCC / 2
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Table 4. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3V 5%, TA = 40C to +85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum Quiescent Supply Currentc 17 300 2.0 Min 2.0 -0.3 2.4 0.55 0.30 Typ Max VCC + 0.3 0.8 Unit V V V V V Condition LVCMOS LVCMOS IOH = -24 mAa IOL = 24 mA IOL = 12 mA VIN = VCC or GND All VCC Pins
W
A mA
a. The MPC9447 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V). b. Inputs have pull-down or pull-up resistors affecting the input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6. AC Characteristics (VCC = 3.3V 5%, TA = -40C to +85C)a
Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Input Frequency Output Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Output Pulse Skewd Output Duty Cycle Output Rise/Fall Time Cycle-to-cycle jitter RMS (1 ) CCLK0 or CCLK1 to CLK_STOPc CCLK0 or CCLK1 to CLK_STOPc 0.0 1.0 150 2.0 fQ<170 MHz 45 0.1 TBD 50 300 55 1.0 CCLK0 or CCLK1 to any Q 1.3 5Characteristics Min 0 0 1.4 1.0b 3.3 11 11 Typ Max 350 350 Unit MHz MHz ns ns ns ns ns ns ns ps ns ps % ns ps DCREF = 50% 0.55 to 2.4V 0.8 to 2.0V Condition
a. AC characteristics apply for parallel output termination of 50 to VTT. b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. c. Setup and hold times are referenced to the falling edge of the selected clock signal input. d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
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MPC9447
Table 7. DC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICCQ Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum Quiescent Supply Currentc 19 300 2.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V Condition LVCMOS LVCMOS IOH =-15 mAa IOL = 15 mA VIN = VCC or GND All VCC Pins
W
A mA
a. The MPC9447 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines per output (VCC=2.5V). b. Inputs have pull-down or pull-up resistors affecting the input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 8. AC Characteristics (VCC = 2.5V 5%, TA = -40C to +85C)a
Symbol fref fmax fP,REF tr, tf tPLH/HL tPLZ, HZ tPZL, ZH tS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Input Frequency Output frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Propagation Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-Device Skew Ouput Pulse Skewd Output Duty Cycle Output Rise/Fall Time Cycle-to-cycle jitter RMS (1 ) CCLK0 or CCLK1 to CLK_STOPc CCLK0 or CCLK1 to CLK_STOPc 0.0 1.0 150 2.7 fQ<350 MHz 45 0.1 TBD 50 200 55 1.0 CCLK0 or CCLK1 to any Q 1.7 Characteristics Min 0 0 1.4 1.0b 4.4 11 11 Typ Max 350 350 Unit MHz MHz ns ns ns ns ns ns ns ps ns ps % ns ps DCREF = 50% 0.6 to 1.8V 0.7 to 1.7V Condition
a. AC characteristics apply for parallel output termination of 50 to VTT. b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. c. Setup and hold times are referenced to the falling edge of the selected clock signal input. d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |
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MPC9447
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram
CCLK0 or CCLK1 CLK_STOP VOLTAGE (V) Q0 to Q8 3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
2.0 In 1.5
Driving Transmission Lines The MPC9447 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2.
1.0
0.5
0 2 4 6 8 TIME (nS) 10 12 14
Figure 5. Single versus Dual Line Termination Waveforms The waveform plots in Figure 5 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9447 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9447. The output waveform in Figure 5 "Single versus Dual Line Termination Waveforms" shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL Z0 RS R0 VL = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 33 || 33 = 17 = 3.0 ( 25 / (16.5+17+25) = 1.28V
MPC9447 OUTPUT BUFFER IN
17
RS = 33
ZO = 50 OutA
MPC9447 OUTPUT BUFFER IN
17
RS = 33
ZO = 50 OutB0
RS = 33
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9447 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9447 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V.
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6 "Optimized Dual Line Termination" should be used. In this case, the series terminating resistors
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MOTOROLA
MPC9447
are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9447 OUTPUT BUFFER
17
RS = 16
ZO = 50
RS = 16
ZO = 50
17 + 16 k 16 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
The Following Figures Illustrate the Measurement Reference for the MPC9447 Clock Driver Circuit
MPC9447 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
W
RT = 50 VTT
RT = 50 VTT
Figure 7. CCLK MPC9447 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V
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MPC9447
VCC VCC VCC VCC
CCLK
B2 B2
GND QX tP(LH) tP(HL)
GND
Figure 8. Propagation Delay (tPD) Test Reference
VCC VCC VCC VCC
B2
CCLK
GND
VCC VCC VCC VCC
B2 B2
B2
QX tP(LH) tP(HL) tSK(P) = | tPLH - tPHL |
GND
GND tSK(LH) tSK(HL)
GND
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
Figure 9. Output-to-Output Skew tSK(LH, HL)
Figure 10. Output Pulse Skew (tSK(P)) Test Reference
VCC VCC tP T0 DC = (tP
B2
VCC=3.3V 2.4 VCC=2.5V 1.8V 0.6V
GND
T0 x 100%)
tF tR
0.55
The time from the output controlled edge to the non-controlled edge, divided by the time between output controlled edges, expressed as a percentage
Figure 11. Output Duty Cycle (DC)
Figure 12. Output Transition Time Test Reference
CCLK PCLK
VCC VCC VCC VCC
B2 B2
GND
TN
TN+1
TJIT(CC) = |TN -TN+1 |
CLK_STOP
GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs tS tH
Figure 13. Cycle-to-Cycle Jitter
Figure 14. Setup and Hold Time (tS, tH) Test Reference
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MOTOROLA
MPC9447
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
MOTOROLA
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
8
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
TIMING SOLUTIONS
-T-, -U-, -Z-
MPC9447
NOTES
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NOTES
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MPC9447
NOTES
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
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MPC9447/D TIMING SOLUTIONS

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