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| Ordering number : EN5782 CMOS IC LC4608C Printer Head Driver Overview The LC4608C is a driver for ink-jet printer heads with 64bit output. It converts 4-bit parallel input into 16-step gray scale output by regulating the transmission gate's output time. * 16-step gray scale output from 4-bit parallel input * Built-in 64 x 2-channel transmission gate output * Transmission gate on resistance of 60 (typ.) 100 (max) * CMOS process with high withstand voltage (42 V) Features This 64-bit CMOS driver with 16-step gray scale output and high withstand voltage offers the following features. * Built-in 64 x 4-bit static shift register * Built-in 64 x 4-bit static latch Specifications Maximum Ratings Parameter Supply voltage (logic) Supply voltage (high withstand voltage circuits) Driver output breakdown voltage Driver output current Input current Input voltage (logic) Input voltage (COM, output) Operating temperature Storage temperature Junction temperature Symbol VDD VH BVDO IDO IIN VIN1 VIN2 Topr Tstg Tj Peak value within allowable operating range Conditions Ratings -0.5 to +7.0 -0.5 to +42 -0.5 to +42 400 -20 to +20 -0.5 to VDD +0.5 -0.5 to VH +0.5 -10 to +90 -65 to +150 -10 to +125 Unit V V V mA mA V V C C C Allowable Operating Ranges at VDD = 5.0 V10%, Topr = -10 to +90C unless otherwise specified Parameter Symbol VDD VH VIN COM IDO fclk tds tdh tLs twCLK twLAT 40 40 140 50 80 VH = 40 V *2 *1 Conditions Ratings min 4.5 24.0 0 0 200 typ 5.0 max 5.5 40.0 VDD VH 400 8.0 Unit V V V V mA MHz ns ns ns ns ns Supply voltage Input voltage Output current DOn Clock frequency Data setup time Data hold time Latch setup time Clock pulse width Latch pulse width Continued on next page. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 33198RM (OT) No. 5782-1/11 LC4608C Continued from preceding page. Parameter STBCLK frequency CLK LOAD setup time LOAD CLK hold time LOAD pulse width STBCLK LOAD setup time LOAD STBCLK hold time Clock rising edge time Clock falling edge time Latch rising edge time Latch falling edge time Operating temperature Symbol fSTB tSL tHL tWL tSTBL tLSTB tr tf tlr tlf Tjopr -1.0 80 80 80 80 80 35 35 70 70 +90 Conditions Ratings min typ max 1.0 Unit MHz ns ns ns ns ns ns ns ns ns C Note : 1. The figures for normal operation are a load capacitance Cpzt of 1 nF, a power supply voltage VH of 30 V, and a max input level COMmax of 25 V. 2. Value for VH = 40 V, COMmax = 40 V, frequency = 35 kHz, and duty factor = 1/100. Electrical Characteristics DC Characteristics at VDD = 5.0 V10%, Tjopr = -10 to +90C unless otherwise specified Parameter Input high-level voltage Input low-level voltage Input high-level current *2 Input low-level current *3 Output high- level voltage Output low-level voltage Output high-level current transmission gate voltage Output low-level current transmission gate voltage Transmission gate on resistance Symbol VIH VIL -IIH1 -IIH2 IIL VOH VOL VOHT VOLT RON Rx VDD = 5.0 V, VIH = 5.0 V VDD = 5.0 V, VIH = 5.0 V VDD = 5.0 V IO = -400 A IO = 400 A VDD = 5.0 V, VH = 40 V, COMn = 40 V, IOHT = 10 mA VDD = 5.0 V, VH = 40 V, COMn = 40 V, -IOHT = 10 mA VH = 40 V, VDS = 3 V Within chip 2 (MAX - MIN) x 100 -------------------- MAX + MIN VDD - GND, fclk = 3.5 MHz, fSln = 1.75 MHz Leakage current between pins VDD = 5.0 V, VH = 42 V -15 39 39.4 0.6 60 1.0 100 Conditions Ratings min VDD x 0.7 -0.3 0 0 0 VDD - 0.5 0.5 50 typ max VDD +0.3 VDD x 0.3 0.5 100 0.5 Unit V V A A A V V V V A A Transmission gate on resistance variation +15 Current drain Leakage current between pins Output leakage current IDD1 INL ILEAK -15 0 0 +15 10 100 Note : 1. The sign is negative for incoming current and positive for outgoing current. 2. -IIH1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB3. -IIH applies to the following input pins: STB4 and STB5. 3. IIL1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB5. Switching Characteristics at VDD = 5.0 V10%, Tjopr = -10 to +90C unless otherwise specified Parameter SOn output rising edge time SOn input rising edge time STBn DOn propagation delay time CLK SOn propagation delay time Symbol tor tof tdor tdof tsor tsof CL = 10 pF CL = 10 pF *5 *5 CL = 10 pF CL = 10 pF Conditions Ratings min typ max 50 50 1.0 1.0 140 140 Unit ns ns s s ns ns Note : 5. The figures are for a load capacitance Cpzt of 1 nF and a power supply voltage VH of 30 V as measured with RL = 3 k and COMn = 25 V DC. No. 5782-2/11 LC4608C Timing Chart 1 Timing Chart 2 Timing Chart 3 No. 5782-3/11 LC4608C Timing Chart 4 Usage Note The power on and power off sequences must use the following orders. Power on sequence: VDD 5-V input circuits VH COMn Power off sequence: COMn VH 5-V input circuits VDD Block Diagram Level shift circuit Gray scale control logic 4-bit counter 4-bit latche x 64 4-bit shift register x 64 No. 5782-4/11 LC4608C Pad Layout Diagram Chip size 2.67 mm x 9.48 mm Output pad PP 140 m 116 m 106 m 96 m 90 m 200 m 116 m 106 m 96 m 90 m dimensions WSM, LSM WM, LM WSC, LSC WJP, LJ Input pad PP (min) dimensions WSM, LSM WM, LM WSC, LSC WJP, LJ No. 5782-5/11 LC4608C Signal sequence Valid data Invalid data Valid data Invalid data Valid data No. 5782-6/11 LC4608C Pad Functions Pad Name CLK SI0 to SI3 LAT STB1, 2, 3 I/O I I I I Shift register clock input Shift register serial data input. SI0 is the least significant bit of the gray scale data; SI3, the most significant bit. Parallel output latch input. high level input converts serial data to parallel data; low level latches the data. 3-phase selector inputs. high level input turns on the corresponding output. STB1 controls output bits DO1, DO4, DO7, DO10,... DO62. STB2 controls output bits DO2, DO5, DO8, DO11,... DO63. STB3 controls output bits DO3, DO6, DO9, DO12,... DO64. 2-phase selector inputs with pull-down register. high level input turns on the corresponding output. STB4 controls the odd bits: DO1, DO3, DO5,... DO63. STB5 controls the even bits: DO2, DO4, DO6,... DO64. External clock signal input for gray scale signal generator Reset input for 4-bit counter. low level input resets the counter to "0." Scan voltage signal input, latched when the shift register bit is "1" (DO pin pairs 1, 2, 5, 6,... 57, 58, 61, 62) Scan voltage signal input, latched when the shift register bit is "0" (DO pin pairs 1, 2, 5, 6,... 57, 58, 61, 62) Scan voltage signal input, latched when the shift register bit is "1" (DO pin pairs 3, 4, 7, 8,... 59, 60, 63, 64) Scan voltage signal input, latched when the shift register bit is "0" (DO pin pairs 3, 4, 7, 8,... 59, 60, 63, 64) Shift register serial data output. SO0 is the least significant bit of the gray scale data; SO3, the most significant bit. Parallel data output. Transmission gate output. Power supply for logic circuits (+5 V) Ground for logic and level conversion circuits Power supply for level conversion circuits +40 V Function Pin Count 1 4 1 3 STB4, 5 STBCLK LOAD COM1 COM2 COM3 COM4 SO0 to SO3 DO1 to DO64 VDD GND VH I I I I I I I O O -- -- -- 2 1 1 2 2 2 2 4 64 2 4 2 No. 5782-7/11 LC4608C I/O Circuits * Logic circuit inputs Pins: SI0 to SI3, CLK, LAT, STB1 to STB3, STBCLK, LOAD The pull-down resistor *1 is only available for STB4 and STB5. * Logic circuit outputs Pins: SO0 to SO3 * DOn outputs No. 5782-8/11 LC4608C Gray Scale Timing Chart Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 The rising edge is synchronized with the STBCLK falling edge. No. 5782-9/11 LC4608C Pad Coordinates Pin Name DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 DO25 DO26 DO27 DO28 DO29 DO30 DO31 DO32 DO33 DO34 DO35 DO36 DO37 DO38 DO39 DO40 DO41 DO42 DO43 DO44 DO45 DO46 DO47 DO48 DO49 x-Coordinate -4410.0 -4270.0 -4130.0 -3990.0 -3850.0 -3710.0 -3570.0 -3430.0 -3290.0 -3150.0 -3010.0 -2870.0 -2730.0 -2590.0 -2450.0 -2310.0 -2170.0 -2030.0 -1890.0 -1750.0 -1610.0 -1470.0 -1330.0 -1190.0 -1050.0 -910.0 -770.0 -630.0 -490.0 -350.0 -210.0 -70.0 70.0 210.0 350.0 490.0 630.0 770.0 910.0 1050.0 1190.0 1330.0 1470.0 1610.0 1750.0 1890.0 2030.0 2170.0 2310.0 y-Coordinate 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 Pin Name DO50 DO51 DO52 DO53 DO54 DO55 DO56 DO57 DO58 DO59 DO60 DO61 DO62 DO63 DO64 COM1 COM2 COM3 COM4 VH GND SI3 SI2 SI1 SI0 GND VDD STB5 STB4 STB3 STB2 STB1 STBCLK LOAD LAT CLK VDD GND SO0 SO1 SO2 SO3 GND VH COM4 COM3 COM2 COM1 x-Coordinate 2450.0 2590.0 2730.0 2870.0 3010.0 3150.0 3290.0 3430.0 3570.0 3710.0 3850.0 3990.0 4130.0 4270.0 4410.0 -4567.0 -4367.0 -4167.0 -3967.0 -3730.0 -3457.8 -3255.8 -3019.8 -2755.8 -2519.8 -2215.8 -1993.4 -1791.4 -1555.4 -1291.4 -1055.4 802.4 1038.4 1302.4 1538.4 1802.4 1990.4 2212.8 2516.8 2752.8 3016.8 3252.8 3454.8 3727.8 3967.8 4167.0 4367.0 4567.0 y-Coordinate 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 -1162.0 Note: The coordinate system places the origin at the chip center, the output pads across the top, and the input pads across the bottom. No. 5782-10/11 LC4608C Note on COMn Input (Example: input data = 0100) Delay due to inverter causes both switches to turn on simultaneously. Because the chip turns the output analog switches on in pairs using the timing shown above, make sure that there are no potential differences between the pairs COM1-COM2 and COM3-COM4. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5782-11/11 |
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