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PD - 97047
IRFB3077PBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Worldwide Best RDS(on) in TO-220 l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
G S
HEXFET(R) Power MOSFET
D
VDSS RDS(on) typ. max. ID
D
75V 2.8m: 3.3m: 210A
G
D
S
TO-220AB IRFB3077PBF
G D S
G a te
D r a in
S o u rc e
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dV/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
210c 150 c 850 370 2.5 20 2.5 -55 to + 175 300 10lbxin (1.1Nxm)
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy e Avalanche Current c Repetitive Avalanche Energy g 240 See Fig. 14, 15, 22a, 22b, mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case k Case-to-Sink, Flat Greased Surface Junction-to-Ambient jk
Typ.
--- 0.50 ---
Max.
0.402 --- 62
Units
C/W
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1
10/24/05
IRFB3077PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
75 --- --- 2.0 --- --- IGSS RG Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance --- --- --- --- 0.091 2.8 --- --- --- --- --- 1.2 --- --- 3.3 4.0 20 250 100 -100 --- nA V
Conditions
VGS = 0V, ID = 250A
V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS Gate Threshold Voltage Drain-to-Source Leakage Current
V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A g V A VDS = VGS, ID = 250A VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V f = 1MHz, open drain
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
160 --- --- --- --- --- --- --- --- --- --- --- 160 37 42 25 87 69 95 9400 820 350 1090 1260 --- 220 --- --- --- --- --- --- --- --- --- --- --- pF ns S nC ID = 75A VDS = 38V VGS = 10V g VDD = 38V ID = 75A RG = 2.1 VGS = 10V g VGS = 0V VDS = 50V = 1.0MHz
Conditions
VDS = 50V, ID = 75A
Coss eff. (ER) Effective Output Capacitance (Energy Related)i --- Coss eff. (TR) Effective Output Capacitance (Time Related)h ---
VGS = 0V, VDS = 0V to 60V j, See Fig.11 VGS = 0V, VDS = 0V to 60V h, See Fig. 5
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) di Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- 210c --- --- 42 50 59 86 2.5 850 1.3 63 75 89 130 --- A nC V ns A
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. TJ = 25C, IS = 75A, VGS = 0V g VR = 64V, TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C IF = 75A di/dt = 100A/s g
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.08mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 400A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFB3077PBF
1000
TOP
1000
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
BOTTOM
4.5V
100
100
4.5V
60s PULSE WIDTH Tj = 25C
10 0.1 1 10 100 10 0.1 1
60s PULSE WIDTH Tj = 175C
10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
2.5
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
ID = 75A
2.0
ID, Drain-to-Source Current()
VGS = 10V
100
(Normalized)
TJ = 175C
1.5
10
TJ = 25C VDS = 25V
1.0
60s PULSE WIDTH
1 2.0 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
16000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A VDS = 60V VDS= 38V VDS= 17V
16
12000
C, Capacitance (pF)
Ciss
8000
12
8
4000
4
Coss Crss
0 1 10 100
0 0 40 80 120 160 200 240 280 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB3077PBF
1000.0
10000
TJ = 175C
ISD , Reverse Drain Current (A)
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on)
1000 100sec 100 10msec
100.0
10.0
TJ = 25C
1.0
10
LIMITED BY PACKAGE
1msec
1
VGS = 0V
0.1 0.0 0.4 0.8 1.2 1.6 2.0
Tc = 25C Tj = 175C Single Pulse 0.1 1.0
DC
0.1 10.0 100.0
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
Fig 8. Maximum Safe Operating Area
100
240 LIMITED BY PACKAGE 200
ID , Drain Current (A)
160 120 80 40 0 25 50 75 100 125 150 175 TC , Case Temperature (C)
90
80
70 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
3.0
Fig 10. Drain-to-Source Breakdown Voltage
1000
EAS, Single Pulse Avalanche Energy (mJ)
2.5
800
ID 20A 35A BOTTOM 75A
TOP
2.0
Energy (J)
600
1.5
400
1.0
0.5
200
0.0 0 20 40 60 80
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB3077PBF
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05 0.02 0.01
R1 R1 J 1 2 R2 R2 R3 R3 3 C 3
0.01
J
Ri (C/W) i (sec) 0.0766 0.000083 0.1743 0.1513 0.000995 0.007038
1
2
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.0001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01 0.05
10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax
0.10
1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A
200
100
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB3077PBF
4.0
24
VGS(th) Gate threshold Voltage (V)
ID = 1.0A ID = 1.0mA ID = 250A
3.0
20
16
IRRM - (A)
2.0
12
8
4
IF = 30A VR = 64V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
24
Fig. 17 - Typical Recovery Current vs. dif/dt
400
20
300
16
IRRM - (A)
QRR - (nC)
12
200
8
4
IF = 45A VR = 64V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
100
IF = 30A VR = 64V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
400
Fig. 19 - Typical Stored Charge vs. dif/dt
300
QRR - (nC)
200
100
IF = 45A VR = 64V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB3077PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFB3077PBF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/05
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