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STS8DNH3LL
DUAL N-CHANNEL 30V - 0.018 - 8A SO-8 LOW GATE CHARGE STripFETTM III POWER MOSFET
TYPE STS8DNH3LL

VDSS 30 V
RDS(on) <0.022
ID 8A
TYPICAL RDS(on) = 0.018 OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific MOSFET is the Third generation of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.
SO-8
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS
Ordering Information
SALES TYPE STS8DNH3LL MARKING S8DNH3LL PACKAGE SO-8 PACKAGING TAPE & REEL
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM(*) Ptot Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Value 30 30 16 8 5 32 2 Rev.0.2 Unit V V V A A A W
(*) Pulse width limited by safe operating area. June 2004 1/9
STS8DNH3LL
TAB.1 THERMAL DATA
Rthj-amb Tj Tstg
(*)Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature
Max
62.5 150 -55 to 150
C/W C C
(*) When mounted on 1 inch2 FR-4 board, 2 oz of Cu, t 10s
ELECTRICAL CHARACTERISTICS (Tj = 25 C unless otherwise specified) TAB.2 OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 30 1 10 100 Typ. Max. Unit V A A nA
IGSS
TAB.3 ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 4 A ID = 4 A Min. 1 0.018 0.020 0.022 0.025 Typ. Max. Unit V

TAB.4 DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS=15 V ID = 4 A Min. Typ. 8.5 857 147 20 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0
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STS8DNH3LL
ELECTRICAL CHARACTERISTICS (continued) TAB.5 SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 4 A VDD = 15 V VGS = 10 V RG = 4.7 (Resistive Load, Figure 1) VDD= 15 V ID= 8 A VGS= 4.5 V (see test circuit, Figure 2) Min. Typ. 12 14.5 7.0 2.5 2.3 10 Max. Unit ns ns nC nC nC
TAB.6 SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 15 V ID = 4 A VGS = 10 V RG = 4.7, (Resistive Load, Figure 1) Min. Typ. 23 8 Max. Unit ns ns
TAB.7 SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
1.5 %.
Test Conditions
Min.
Typ.
Max. 8 32
Unit A A V ns nC A
ISD = 4 A
VGS = 0 15 5.7 0.76
1.5
ISD = 8 A di/dt = 100A/s Tj = 150C VDD = 15 V (see test circuit, Figure 3)
(*)Pulsed: Pulse duration = 300 s, duty cycle (*)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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STS8DNH3LL
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STS8DNH3LL
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage Temperature.
.
.
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STS8DNH3LL
Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 2: Gate Charge test Circuit
Fig. 3: Test Circuit For Diode Recovery Behaviour
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STS8DNH3LL
SO-8 MECHANICAL DATA
DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
0016023
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STS8DNH3LL
Revision History
Date
Tuesday 15 June 2004
Revision
0.2 FIRST ISSUE
Description of Changes
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STS8DNH3LL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners.
(c) 2004 STMicroelectronics - All Rights Reserved
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