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| For Communications Equipment MN86063 High-Speed CODEC LSI for Facsimile Images Overview The MN86063 is a high-speed LSI codec for compressing and decompressing facsimile images. Features include real-time printing to laser printers, built-in line memory, enlargement and reduction, and code conversion. Function Message coding: MH, MR, MMR, and MG3. The chip also supports data transfers on the image and system buses and DMA transfers on the image bus alone. Coding conversion The chip converts between all supported message coding systems: MH, MR, MMR, and MG3. Enlargement/reduction These may be added to coding, decoding, code conversion, and data transfer operations. (1) In the primary scan direction, the chip uses multiplication on the change point address. The scaling factor can be anywhere between approximately 0.1% and 200% in increments of approximately 0.1%. Integral multiplication is also available beyond this (2) In the subscanning direction, the chip uses decimation and replication. The scaling factor can be anywhere between approximately 0.0015% and 200% in increments of approximately 0.0015%. Integral multiplication is also available from 2 to 65,535. White masks for both edges These may be added to coding, decoding, code conversion, and data transfer operations. They change all pixels within the margins, specified in bit increments, to white. Decoding error processing The chip offers a choice of replacing with the previous line or a white line. Features Pixels per line: between 16 and 4864 bits, in word (16-bit) increments. Processing time per line: Individual pixels are processed within two system clock cycles. For a machine cycle of 10 MHz, processing the worst-case pattern for a 4096-bit line takes no more than 1 ms. Time-shared, multiplex processing Support for time-shared, multiplex processing allows image I/O, enlargement/reduction processing, and coding/decoding to proceed concurrently for a group of lines. Image bus DMA transfers can also proceed concurrently with command processing. Multiple channels If lines consist of 2432 bits or fewer, commands can be processed simultaneously on two channels using time-sharing. These commands may be issued asynchronously. Bus configuration There are separate system and image buses. The latter features two independent master DMA channels; the former, four slave DMA channel pins. Image data I/O Image data I/O can use either the image or system bus. Byte conversion When the system bus is 16 bits wide, the chip can swap the upper and lower bytes of image or coded data. It can also swap the MSB and LSB. Memory management The chip includes pointer management for the image buffer connected to the image bus. Machine cycle The limit is 10 MHz. This means that the maximum input clock is twice this, or 20 MHz. Applications Facsimile equipment MN86063 Pin Assignment For Communications Equipment VSS3 VDD3 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 VSS4 VDD4 TEST3 TEST2 TEST1 TEST0 RESET 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IA9 IA10 IA11 IA12 IA13 IA14 IA15 VDD2 VSS2 DACK1 DACK0 DSTR0 DSTR1 IMLE IMUE DCMP0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DCMP1 IREADY IOW IMW IOR IMR DREQ0 DREQ1 IHACK IHREQ VDD1 VSS1 A0 A1 A2 A3 ACKD1 ACKD0 ACKC1 ACKC0 REQD1 REQD0 REQC1 REQC0 UBE HEX INTR0 INTR1 INTR2 2SYSCLK RD WR SYSCLK D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CS QFP100-P-1818 For Communications Equipment Pin Configuration MN86063 The MN86063 features two buses: the system bus, which is primarily used for transferring coded data to and from a microprocessor and other components and the image bus, which is used for transferring image data to or from a scanner, printer, or the like. Pin Function Chart The chip has a total of 100 pins: 39 for the system bus, 49 for the image bus, and 12 for testing, power supply, and other purposes. System bus pins A0 to A3 D0 to D15 UBE RD WR CS HEX RESET INTR0 to 2 MN8606X REQC0 REQC1 REQD0 REQD1 ACKC0 ACKC1 ACKD0 ACKD1 2SYSCLK SYSCLK Image bus pins IA0 to 15 ID0 to 15 IHREQ IHACK IREADY IMUE IMLE IMR IMW DSTR0 DSTR1 DREQ0 DREQ1 DACK0 DACK1 DCMP0 DCMP1 IOR IOW VDD0 to 3 VSS0 to 3 TEST0 to 3 MN86063 Pin Descriptions System Bus Pin No. 35 36 37 38 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 6 7 25 1 100 2 Symbol A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 UBE RD WR CS HEX RESET INTR0 I I I I I I O Open corrector 3 INTR1 O Open corrector 4 INTR2 O Open corrector 27 28 REQC0 REQC1 O O I/O Tristate I/O I For Communications Equipment Function Description Address. Address bus for accessing internal registers Data. Data bus for bidirectional transfers over system bus Upper byte enable. This input pin specifies whether the data from pins D15-D8 is effective. Read. This input pin specifies a read from the specified register. Write. This input pin specifies a write to the specified register. Chip select. This input pin specifies access to a register. Data bus width selection. This input pin specifies the width of the system data bus: "0" for 16 bits; "1" for 8 bits. Reset. This input pin resets the internal circuitry, clearing all registers. Interrupt request 0. This output pin indicates an interrupt request triggered by the cause given in interrupt register 0 (STIR0) Interrupt request 1. This output pin indicates an interrupt request triggered by the cause given in interrupt register 1 (STIR1) Interrupt request 2. This output pin indicates an interrupt request triggered by the cause given in DMA transfer interrupt register (DMIR). DMA transfer output request 0. This output pin indicates a request for data output on DMA channel 0. DMA transfer output request 1. This output pin indicates a request for data output on DMA channel 1. For Communications Equipment Pin Descriptions (continued) System Bus (continued) Pin No. 29 30 31 32 33 34 5 8 Symbol REQD0 REQD1 ACKC0 ACKC1 ACKD0 ACKD1 2SYSCLK SYSCLK I/O O O I I I I I O MN86063 Function Description DMA transfer input request 0. This output pin indicates a request for data input on DMA channel 0. DMA transfer input request 1. This output pin indicates a request for data input on DMA channel 1. DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC0. DMA transfer output acknowledge 0. This input pin accepts the response to a DMA transfer request with REQC1. DMA transfer input acknowledge 0. This input pin accepts the response to a DMA transfer request with REQD0. DMA transfer input acknowledge 0. This input pin accepts the response to a DMA transfer request with REQD1. 2 system clock. This input pin accepts a clock signal with a frequency twice that of the system clock. System clock. This output pin provides a clock signal with half the frequency of 2SYSCLK. Image Bus Pin No. 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol IA15 1A14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 I/O O Tristate Function Description Image address bus. These pins provide an address on the image data bus. MN86063 Pin Descriptions (continued) Image Bus (continued) Pin No. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 41 42 49 52 53 45 47 55 54 44 43 56 57 Symbol ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 IHREQ IHACK IREADY IMUE IMLE IMR IMW DSTR0 DSTR1 DREQ0 DREQ1 DACK0 DACK1 O I I O Tristate O Tristate O Tristate O Tristate O O I I O O I/O I/O Tristate For Communications Equipment Function Description Image data. These pins form a bus for bidirectional transfers of image data. Image bus request. This output pin indicates a request for control of the image bus. Image bus acknowledge. This input pin indicates when the chip can seize control of the image bus. Image data acknowledge. This input pin indicates the end of the read/ write operation. Image memory upper byte enable. This output pin specifies whether the data from pins ID15-ID8 is effective. Image memory lower byte enable. This output pin specifies whether the data from pins ID7-ID0 is effective. Image memory read. This output pin indicates a read from the address on the image address bus. Image memory write. This output pin indicates a write to the address on the image address bus. DMA start 0. This output indicates that the chip is ready for a DMA transfer from an I/O device to memory. DMA start 1. This output indicates that the chip is ready for a DMA transfer from memory to an I/O device. DMA request 0. This input pin indicates a request for a DMA transfer from an I/O device to memory. DMA request 1. This input pin indicates a request for a DMA transfer from memory to an I/O device. DMA acknowledge 0. This output pin gives the response to the DREQ0 signal, initiating a DMA transfer from an I/O device to memory. DMA acknowledge 1. This output pin gives the response to the DREQ1 signal, initiating a DMA transfer from memory to an I/O device. For Communications Equipment Pin Descriptions (continued) Image Bus (continued) Pin No. 51 50 46 48 Symbol DCMP0 DCMP1 IOR IOW I/O O O O Tristate O Tristate MN86063 Function Description DMA complete 0. This output pin indicates the successful completion of the DMA transfer of 1 line of data from an I/O device to memory. DMA complete 1. This output pin indicates the successful completion of the DMA transfer of 1 line of data from memory to an I/O device. I/O device read. This output pin indicates a read from an I/O device connected to the image address bus. I/O device write. This output pin indicates a write to an I/O device connected to the image address bus. Power on Reset Circuit Pin No. 96 97 98 99 40 59 77 95 39 58 76 94 Symbol TEST3 TEST2 TEST1 TEST0 VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 I Ground. Connect all these pins to the ground. I 5 volt power supply. Connect all these pins to a 5 volt power supply. I/O I Function Description Test mode. Connect all these pins to the ground. MN86063 For Communications Equipment Application Circuit Example #1. Sample Connections to System Bus Address bus (MPU) BUFR/W BUFEN AD(0 to 15) A(16 to 15) BS(0 to 2) ASTB HDACK UBE IORD IOWR +5V MRD MWT DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3 DMAAK3 INTR0 INTR1 INTR2 CLKIN RST 16 4 3 74HC573 D Q C OC 3 pieces 23 74HC245 G B DIR A 2 pieces 16 Data bus MN86063 A(0 to 3) D(0 to 15) 16 4 A(0 to 3) D(0 to 15) UBE RD WT BS(0 to 2) A(4 to 19) Address Decoder CS HEX REQC0 ACKC0 REQC1 ACKC1 REQD0 ACKD0 REQD1 ACKD1 INTR0 INTR1 INTR2 +5V 2SYSCLK RESET (Upper half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) CS WE OE (Lower half of memory) 256-Kbit SRAM A(0 to 14) I/O(0 to 7) CS WE OE A(1 to 15) D(0 to 7) Address Decoder 15 8 A0 BS(0 to 2) A(16 to 19) A(1 to 15) D(8 to 15) 15 8 Crystal oscillator circuit (20 MHz) Power on reset circuit For Communications Equipment Application Circuit Example #2. Sample Connections to Image Bus MN86063 Address bus Data bus MN86063 IHREQ IHACK IA(0 to 15) ID(0 to 15) DSTR0 DCMP0 DREQ0 DACK0 IOR +5V SYSCLK IREADY DSTR1 DCMP1 DREQ1 DACK1 IOW +5V IMUE IMLE IMR IMW Low-speed device Bus Arbiter Scanner 8 Timing control Printer 8 (Upper half of memory) 256-Kbit SRAM IA(1 to 15) ID(8 to 15) 15 8 A(0 to 14) I/O(0 to 7) CS WE OE (Lower half of memory) 256-Kbit SRAM IA(1 to 15) ID(0 to 7) 15 8 A(0 to 14) I/O(0 to 7) CS WE OE MN86063 Package Dimensions (Unit: mm) QFP100-P-1818 For Communications Equipment 22.900.40 18.000.20 75 51 50 (1.20) 18.000.20 100 26 (1.20) 0.65 2.90 max. 1 25 2.500.20 0.300.10 0.100.10 +0.10 76 22.900.40 (2.450.20) 0.15-0.05 0 to 10 (1.300.20) 0.15 SEATING PLANE |
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