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KS51840 DESCRIPTION KS51840, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset circuit generates reset pulse every certain period, and every halt mode termination time. The KS51840 microcontroller has been designed for use in small system control applications that require a low-power, cost-sensitive design solution. In addition, the KS51840 has been optimized for remote control transmitter. FEATURES ROM Size 1,024 bytes RAM Size 32 nibbles Instruction Set 39 instructions Instruction Cycle Time 13.2 sec at Fxx=455 kHz Input Ports Two 4-bit ports(24 pins)/One 4-bit port, one 2-bit ports(20 pins) Output Ports One 4-bitport,Seven1-bitports(24pins)/One 4-bit port, Five1-bit ports(20pins) Built-in Oscillator Crystal/Ceramic resonator Built-in Power-on reset and auto reset circuit for generating reset pulse every 131072/Fxx(288ms at Fxx=455kHz) Four Transmission Frequencies Fxx/12 (1/4 duty), Fxx/12 (1/3 duty), Fxx/8 (1/2 duty), and no-carrier frequency Supply Voltage 1.8V-3.6V(Fosc:250kHz-3.9MHz),2.2V-3.6V(Fosc:4MHz-6MHz) Power Consumption Halt mode: 1 A (maximum) Normal mode: 0.5 mA (typical) Operating temperature -20C to 85C Package Type 24 SOP, 20 DIP, 20 SOP Oscillator Frequency divide select Mask Option= Fosc or Fosc/8 BLOCK DIAGRAM P2.1 - P2.6 6 P2-output Latch 5 8 Internal P2.13 ROM 64x16x8 bits 4 PA 6 PC RAM 16x2x4bits 2 4 H 16 L Decoder 1 4 4 L 4 4 PB 3-Level Stack 4 MUX ALU & A 4 P3 Output Register ( PR ) SF 4 Internal P2.0 4 4 4 P1.0 - P1.3 P0.0 - P0.3 P3.0 - P3.3 Internal P2.9 and P2.10 Fxx/8 (1/2) Fxx/12 (1/3) Fxx/12 (1/4) DIV OSC Auto Reset HALT Internal P2.12 No carrier P2.0/REM XI XO S MSUN G MSU N ELECTRONICS 1-1 KS51840 PIN CONFIGURATION (24 SOP) VSS XI XO P2.6 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 1 2 3 4 5 6 8 9 10 11 12 24 23 22 21 20 VDD P2.0/REM TEST P2.1 P2.2 P2.3 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3 KS51840 19 17 16 15 14 13 7 (Top View) 18 PIN DESCRIPTION FOR 24 PINS I/O Circuit Type A A B Symbols P0.0 - P0.3 P1.0 - P1.3 P2.0/REM P2.2 - P2.5 Pin No. 5, 6, 7, 8 9,10,11,12 23 20,19,18, 17 21,4 Type Input Input Output Output Functions 4-bit input port when P2.13 is low 4-bit input port when P2.13 is high 1-bit individual output for remote carrier frequency (1) 1-bit individual output port C D Output Input Input Output -- -- 4-bit parallel output port Input pin for test (Normally connected to VSS) Oscillation clock input Oscillation clock output Power supply Ground C -- -- -- -- -- P2.1, P2.6 P3.0 - P3.3 16,15,14,13 TEST XI XO VDD VSS 22 2 3 24 1 NOTES: 1.The carrier can be selected by software as Fxx/12 (1/3 duty), Fxx/12 (1/4 duty), Fxx/8 (1/2 duty), or no-carrier frequency. 2.Package type can be selected as 24 SOP in the ordering sheet. 1-2 S MSUN G ELECTRONICS KS51840 PIN CONFIGURATION (20 DIP, 20 SOP) VSS XI XO P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P3.3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 14 13 12 11 VDD P2.0/REM TEST P2.1 P2.2 P2.3 P2.4 P3.0 P3.1 P3.2 KS51840 (Top View) 15 PIN DESCRIPTION FOR 20 PINS Type Input Input Output Output I/O Circuit Type A A (1) Symbols P0.0 - P0.3 P1.0 - P1.1 P2.0/REM P2.2 - P2.4 Pin No. 4, 5, 6, 7 8, 9 19 16,15, 14 17 Functions 4-bit input port when P2.13 is low 2-bit input port when P2.13 is high 1-bit individual output for remote carrier frequency 1-bit individual output port B C D Output Input Input Output -- -- 4-bit parallel output port Input pin for test (Normally connected to VSS) Oscillation clock input Oscillation clock output Power supply Ground C -- -- -- -- -- P2.1 P3.0 - P3.3 13,12,11,10 TEST XI XO VDD VSS 18 2 3 20 1 NOTES: 1.The carrier can be selected by software as Fxx/12 (1/3 duty), Fxx/12 (1/4 duty), Fxx/8 (1/2 duty), or no-carrier frequency. 2.Package type can be selected as 20 DIP, or 20 SOP in the ordering sheet. S MSUN G MSU N ELECTRONICS 1-3 |
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