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Philips Semiconductors
Product specification
Quadruple filter DAC
FEATURES * High dynamic range to enable digital DSP (Digital Signal Processor) volume control * 18 bits data input format for each of the four channels * Four times bit-serial oversampling filter * 1st-order 4fas (audio sampling frequency) noise shaper * Four very low noise DACs * Only 1st-order analog post filtering required * Smooth power-on of the DAC output currents * Because of the automatic digital PLL divider range setting the master clock is selectable in a wide 4fas integer range * Insensitive to jitter on the I2S-bus signals with respect to the DAC total harmonic distortion deterioration. QUICK REFERENCE DATA Vref = 2.5 and 5 V; Tamb = 25 C; all voltages referenced to ground; unless otherwise specified. SYMBOL VDDA VDDD IO(DAC) VO(DAC) PARAMETER analog supply voltage digital supply voltage DAC output current (FS) DAC output voltage, nominal DAC operational amplifier output voltage DAC resolution total harmonic distortion plus noise-to-signal ratio dynamic range of DAC digital silence total power dissipation operating ambient temperature Rref = 20.5 k RL 5 k; Rfb = 3 k CONDITIONS MIN. 4.5 4.5 0.4 1.0 TYP. 5.0 5.0 0.5 - APPLICATIONS
TDA1314T
* Stand-alone quadruple low noise DAC * Car radio DAC in conjunction with DSP. GENERAL DESCRIPTION The TDA1314T is a quadruple very low noise high dynamic range DAC which is intended for use in motor cars and is controlled by the car radio DSP. Each channel incorporates an 8th-order IIR up-sampling filter from 1ASF to 4ASF followed by a 1st-order noise shaper and DAC. The DAC currents are converted to audio voltage signals using operational amplifiers (one per channel).
MAX. 5.5 5.5 0.6 4.0 V V
UNIT
mA V
RES (THD + N)/S DR DS Ptot Tamb
length of data input word fi = 1 kHz; 0 dB signal level fi = 1 kHz; -60 dB signal level no signal; A-weighted
- - 92 - - -40
- -66 96 -110 85 +25
18 -56 - -100 - +85
bits dB dB dB mW C
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1314T SO28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm VERSION SOT136-1
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Product specification
TDA1314T
Fig.1 Block diagram.
handbook, full pagewidth
August 1994
V ref 21
BLOCK DIAGRAM
Philips Semiconductors
UP-SAMPLE CLOCK GENERATOR
TDA1314T
4 ASF GENERATOR
5 I out 19 20 I OFL VOFL FASF DAC MSB I out-f I out-c 5 4 fs UP-SAMPLE FILTER 20 20 15 5 COARSE CURRENT SOURCES 17 NOISE SHAPER DAC LATCH THERM. DEC. 1 2 3 31 32 I ref 4 fs 20-bit DATA WORD LATCH 15-bit DATA WORD LATCH 14 9 FINE CURRENT MATRIX CURRENT DIRECTION SWITCH
DAC LATCH
DAC FL
MCLK UPSAMPLE CLOCKS
Quadruple filter DAC
SELINPH
3
SYNTHESIZER DIVIDED BY 45 . . . 128
NOISE SHAPER
R ref
WS 18
2
26 18
SCK 18 18
4
3
DAC FR
18 NOISE SHAPER DAC LATCH 4 fs UP-SAMPLE FILTER
25
SDF
IS INTERFACE
4 fs UP-SAMPLE FILTER
IOFR VOFR
24
SDR
12
DAC RL
13
I ORL VORL
AT/DT 4 fs UP-SAMPLE FILTER NOISE SHAPER DAC LATCH test signals
2
10
TC
1
DAC RR
11
I ORR V ORR
SCOUT1
27
TEST INTERFACE
SCOUT2
28
CMT 6 DGND AGND 7
23
8 V DDD
9 V DDA
22 POWER-UP
16
15 VDDO OGND
MBE001
Philips Semiconductors
Product specification
Quadruple filter DAC
PINNING SYMBOL TC AT/DT SELINPH SCK MCLK DGND AGND VDDD VDDA IORR VORR IORL VORL Rref OGND VDDO IOFR VOFR IOFL VOFL Vref POWER-UP CMT SDR SDF WS SCOUT1 SCOUT2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 analog test/digital test select input select in-phase 4fas mode/scan input signal 1 in test mode serial clock input; I2S-bus master clock input; fi = N x 4fas (45 N 128) digital ground analog ground digital supply voltage analog supply voltage DAC output current; rear right DAC output voltage; rear right DAC output current; rear left DAC output voltage; rear left resistor reference input for DACs current operational amplifier ground operational amplifier supply DAC output current; front right DAC output voltage; front right DAC output current; front left DAC output voltage; front left reference voltage input (12 operational amplifier supply voltage) analog mute input for all DACs current mirror input test signal DESCRIPTION test control signal input (test/operational)
TDA1314T
serial data input for rear DACs (I2S-bus); scan input signal 2 in test mode serial data input for front DACs (I2S-bus) word select input (I2S-bus) scan output signal 1 in test mode; 4fas signal scan output signal 2 in test mode; PLL lock indicator
August 1994
4
Philips Semiconductors
Product specification
Quadruple filter DAC
FUNCTIONAL DESCRIPTION I2S-bus interface
TDA1314T
The word select input (pin 26) is connected to the word select line of the I2S-bus interface. This interface has a standard I2S-bus specification as described in the Philips "I2S-bus specification" (ordering number 9398 332 10011). Figure 4 shows an excerpt of the Philips I2S-bus specification interface report with respect to the general timing and format of the I2S-bus. WS logic 0 means left channel word, logic 1 means right channel word. The serial clock input (pin 4) must be in accordance with the I2S-bus specification, i.e. a continuous clock. Serial data front (SDF, pin 25) and serial data rear (SDR, pin 24) are the I2S-bus serial data lines to be processed in the DACs for the loudspeakers of the car (see Fig.2, blocks DACFL and DACFR for the front loudspeakers and blocks DACRL and DACRR for the right loudspeakers). FL stands for Front Left, FR for Front Right, RL for Rear Left and RR for Rear Right. In order to utilize the capabilities of this IC fully, the data word length should be 18 bits. Signals derived from this block are 4 x 18-bit parallel data words which are applied to the 4fs up-sample filters. 4ASF generator SYNTHESIZER SELINPH (pin 3) and WS (pin 26) are the data inputs for this block which generates the FASFDAC, this being the 4fas signal (at 4 times the audio sample frequency), which is used to latch the data words to the DACs and as a reference to the clock generator block for the up-sample filters. It consists of a digital PLL operating at the master clock signal MCLK (pin 5). In normal mode (i.e. in the event that the MCLK signal on pin 5 is a jitter free clock, with a frequency of integer multiples between 45 and 128, of 4 times the frequency of the WS signal) this block is able to generate a jitter free FASFDAC signal for optimum performance of the DAC. This mode is called the free running mode. If, in some applications, there is considerable jitter on the MCLK while WS is more stable (less jitter), the phase-locked mode should be selected. This mode is normally not used and is not recommended.
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Quadruple filter DAC
UP-SAMPLE GENERATOR This block generates the clocks for the up-sample filters.The external pinning of the 4fas generator block is: * MCLK (see Fig.4), which is a jitter free (maximum 30 ns jitter) external clock at any multiple integer from 45 to 128 times 4fas (4 times the frequency of WS) of the I2S-bus input, thus for a sample frequency of 38 kHz this clock frequency will range from 6.840 MHz to 19.456 MHz in multiples of 152 kHz. * The select in-phase (SELINPH) or free running mode of the synthesizer 45 to 128. In the normal application the free-running mode is used and this pin is not connected (this pin is pulled down by an internal resistor). The phase-locked mode can be selected by hard-wiring this pin to VDDD (pin 8). However, this mode is not recommended. Test interface This block controls the circuit in the test mode, which can be either an analog or digital test mode. Test pins TC (pin 1), AT/DT (pin 2), CMT (pin 23), SCOUT1 (pin 27) and SCOUT2 (pin 28) are not connected in Fig.6. Up-sample filter and noise shaper The signal flow applied to the up-sample filter and noise shaper blocks is the 4 x 18-bit parallel data words in two's complement format from the I2S-bus interface at the audio sampling frequency. The signal flow from these blocks is the 4 x 15-bit parallel data words in two's complement format at a frequency of 4fas. Each of the four digital filters is a four times up-sampling filter. This up-sampling filter is an elliptic filter of 8th order. The filters produce an attenuation of 29 dB (min) for signals outside the audio band. The noise shaper operates at 4fas and reduces the word length from 22 bits to 15 bits which is the word length of the DAC. DAC input signals
TDA1314T
The following signals are input to the DAC blocks FL, FR, RL and RR: * DATA WORD (bits 10 to 14). These 5 bits are used to control, via a thermometer decoder, the current of the 32 coarse current sources of the analog DAC part. The value of this data word determines the total coarse current flowing to the DAC current output. The value of the current of each coarse current source is determined by the following: Rref; this is the current reference input at pin 14 and is at the same voltage level as Vref. A resistor connected to OGND results in a current. This being the reference current of the coarse current sources and subsequently of the DAC in total. * DATA WORD (bits 1 to 9). A current from one of the coarse current sources is fed into a 512 transistor matrix. The value of the DATA WORD (bits 1 to 9) determines which part of one coarse current flows to the DAC current output. * DATA WORD (bit 15). This data word MSB controls the direction of the flow of the DAC output current by switching the current direction switch. * Vref. Voltage reference pin internally connected to a resistor divider to obtain half of the power supply voltage. This voltage is buffered and used as reference voltage input for the operational amplifiers and as a reference voltage in the DAC. * POWER-UP. The analog signal on this pin controls the current biasing circuit of the DACs. This pin is connected internally via a high value resistor to VDDA. Together with an external capacitor a soft switch-on of the DAC output currents is obtained. This pin can also be used as the analog mute input for all DAC output currents by pulling it to ground.
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
Fig.3 I2S-bus timing and format.
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
Fig.4 Total harmonic distortion plus noise-to-signal ratio as a function of output volume.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VDDO Vn Txtal Tstg Tamb Ves Notes 1. All voltages (pins 6, 7 and 15) referenced to ground. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 76 UNIT K/W PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage voltage on any other pin crystal temperature storage temperature operating ambient temperature electrostatic handling note 2 CONDITIONS note 1 note 1 note 1 0 0 0 0 - -55 -40 -2000 MIN. MAX. 6.0 6.0 6.0 VDD +150 +150 +85 +2000 V V V V C C C V UNIT
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
DC CHARACTERISTICS VDD = 4.5 to 5.5 V; VDDA = VDDO = 4.75 to 5.25 V; all voltage referenced to ground (pins 6, 7 and 15); measured in test circuit of Fig.6; Tamb = 25 C; unless otherwise specified. SYMBOL VDDD VDDA VDDO IDDD IDDA IDDO Ptot PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage digital supply current analog supply current operational amplifiers supply current total power dissipation MCLK = 6.84 MHz at digital silence no operational amplifier load resistor MCLK = 6.84 MHz; at digital silence; no operational amplifier load resistor CONDITIONS MIN. 4.5 4.75 4.75 - - - - TYP. 5.0 5.0 5.0 10 5 2 85 5.5 5.25 5.25 17 8 4 145 MAX. UNIT V V V mA mA mA mW
VIH VIL VOH VOL Vref ZI VI IODAC(max)
HIGH level input voltage pins 1 to 5 and 23 to 26 LOW level input voltage pins 1 to 5 and 23 to 26 HIGH level output voltage pins 27 and 28 LOW level output voltage pins 27 and 28 reference input voltage input impedance at pin 21 input voltage pin 14 maximum output current from DACs pins 10, 12, 17 and 19 DC offset voltage at pins 10, 12, 17 and 19 HIGH level output voltage of operational amplifiers at pins 11, 13, 18 and 20 LOW level output voltage of operational amplifiers at pins 11, 13, 18 and 20 internal resistance at pin 22 internal resistance at pins 1 to 3 and 23 VDDD = 4.5 V; IO = -4 mA VDDD = 4.5 V; IO = 4 mA VDDD = 5.5 V; IO = 4.5 mA with respect to OGND with respect to VDDO with respect to OGND with respect to OGND
0.7VDDD - 4.1 - - 0.45VDDO 15 15 0.43VDDO
- - - - - - 0.5VDDO 20 20 0.5VDDO 500
- 0.2VDDD - - 0.4 0.4 0.55VDDO 30 30 0.57VDDO 600
V V V V V V V k k V A
VDDD = 5.5 V; IO = -4.5 mA 5.1
Rref = 20.5 k; VDDO = 5 V 400
VO(os) VOH(O)
with respect to Vref note 1; RL > 5 k; Rfb = 3 k; maximum signal note 1; RL > 5 k; Rfb = 3 k; maximum signal with respect to VDDO Vi = VDDD; with respect to DGND
-
5
-
mV
VDDO - 1.3 VDDO - 1 VDDO - 0.45 V
VOL(O)
0.45
1.0
1.3
V
Rpu Rpd Note
110 27
160 -
240 80
k k
1. RL is the AC impedance of the external circuitry connected to the audio outputs in the application diagram of Fig.6.
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
AC CHARACTERISTICS VDDD = VDDA = VDDO = 5 V; Tamb = 25 C; all voltages referenced to ground (pins 6, 7 and 15) measured in test circuit of Fig.5; unless otherwise specified. SYMBOL ANALOG DACS SVRR supply voltage ripple rejection pins 9 and 16 fripple = 1 kHz; Vripple = 100 mV (peak); CVref = 22 F 30 46 - dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IO(DAC)
maximum deviation of maximum volume output level of the 4 DAC output currents with respect to the average of the 4 outputs crosstalk between the 4 DAC current outputs DAC resolution total harmonic distortion plus noise-to-signal ratio dynamic range digital silence fi = 1 kHz; 0 dB signal fi = 1 kHz; -60 dB signal; A-weighted fi = 1 kHz; -60 dB signal; A-weighted fi = 20 Hz to 17 kHz; A-weighted 2 outputs at digital silence; 2 outputs at maximum volume
-
-
0.38
dB
DAC
-
-90
-60
dB
RES (THD + N)/S
- - - 92 -
- -66 -36 96 -110
18 -56 -32 - -100
bits dB dB dB dB
DR DS
Operational amplifiers Gv PSRR (THD + N)/S open loop voltage gain power supply ripple rejection total harmonic distortion plus noise as a function of the operational amplifiers signal unity gain frequency output impedance fripple = 3 kHz; Vripple = 100 mV (peak) RL > 5 k (AC); Rfb = 3 k; VO = 0.28 V (p-p); fi = 1 kHz; A-weighted open loop RL > 5 k - - - 85 90 -82 - - - dB dB dB
fug Zo
- -
4.5 1.5
- 150
MHz
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
SYMBOL DIGITAL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2S-BUS, UP-SAMPLING FILTER AND NOISE SHAPER fSCK tLC tHC fWS tsr serial clock input frequency serial clock LOW time ASF = 38 kHz 1 at 20% VDDD; T = ----------f SCK 1 at 70% VDDD; T = ----------f SCK 1.368 0.35T - - - 44.1 - 19.456 - - 48 - MHz s s kHz s
serial clock HIGH time
0.35T
word select input frequency set-up time from SDF, SDR and WS to HIGH going edge of SCK hold time from SDF, SDR and WS to HIGH going edge of SCK master clock input frequency master clock LOW time 1 T = ----------f SCK 1 T = ----------f SCK N x 4 x fWS; where N = integer 1 TM = ----------f SCK 1 TM = ----------f SCK with sample-and-hold from DAC fi > 22 kHz; no post filter
38 0.2T
thr
0
-
-
s
fMCLK tMLC tMHC PR SB
45 x 4fWS 64 x 4fWS 128 x 4fWS 0.35TM - - 0.46 - - - - -
kHz s s dB dB
master clock HIGH time
0.35TM - 29
pass band ripple of digital filter stop band attenuation
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
August 1994
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Fig.5 Test circuit.
Philips Semiconductors
Product specification
Quadruple filter DAC
APPLICATION INFORMATION The application diagram is illustrated in Fig.6. All pins used for testing (pins 1, 2, 23, 27 and 28 need not to be connected due to internal resistors being connected to ground or being used as test outputs. In the normal free-running mode it is also not required to connect pin 3. Jitter on the clock edges of MCLK must be as low as possible so as not to deteriorate the DAC THD performance. The jitter time must not be greater than 30 ns. Vref is the voltage reference pin with an internal resistor divider. A capacitor of 22 F is used to get the specified power ripple rejection ratio. The output operational amplifiers are current-to-voltage converters by means of the 3 kW resistors connected between the DAC current outputs (pins 10, 12, 17 and 19) and the voltage outputs (pins 11, 13, 18 and 20) respectively. The voltage on the DAC current outputs is equal to the operational amplifiers virtual ground at Vref in the event that the operational amplifier is used according to the application diagram of Fig.6. Care should be taken, in order to reduce the electromagnetic compatibility (EMC) that the bandwidth of the digital signals being applied to pins MCLK, WS, SCK, SDF and SDR is not larger than necessary. This can be achieved by controlling the slew rate of the digital source outputs or connecting a series resistor close to the digital source output of the driving circuits.
TDA1314T
The resistor connected between Rref (pin 14) and ground is the current reference of the DACs. The voltage on Rref is equal to Vref. On the printed-circuit board VSSA (pin 7) is also the substrate and has the most negative voltage of the IC, a large as possible ground plane is therefore recommended. The connection between VSSA, VSSD and VSSO must be as short as possible. Pins VDDO and VDDA (pins 9 and 16) must have capacitors connected to the VSSA ground plane closest to the chip. Pin VDDD (pin 8) is fed via a small series resistor (25 ). This resistor must be connected as close as possible to pin 8. The POWER-UP (pin 22) is connected via an electrolytic capacitor to ground. This results in a smooth rising of the DAC output currents at power-on. If this is not required then this capacitor can be omitted. Suppression of the higher harmonics by the up-sample filter should be sufficient to protect the amplifiers and the tweeter loudspeakers from excessive HF noise. The band around 4fs cannot be attenuated by the 4ASF filter and is only attenuated by the sample-and-hold effect of the DAC. At frequencies above 100 kHz, additional attenuation achieved by the 1st order post filter, which is built around the buffer operational amplifiers. In total a 2nd order level of filtering can be found above 100 kHz. In terms of power the audio out-of-band power is approximately 15 x 10-4 of the audio in-band power.
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Philips Semiconductors
Product specification
Quadruple filter DAC
TDA1314T
August 1994
14
Fig.6 Application diagram.
Philips Semiconductors
Product specification
Quadruple filter DAC
PACKAGE OUTLINE
TDA1314T
handbook, full pagewidth
18.1 17.7
7.6 7.4 A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
28
15 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 1.1 0.5 detail A 2.65 2.35
pin 1 index 1 14 0 to 8o
MBC236 - 1
1.27
0.49 0.36
0.25 M (28x)
Dimensions in mm.
Fig.7 Plastic small outline package; 28 leads; body width 7.5 mm (SO28; SOT136-1).
August 1994
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Philips Semiconductors
Product specification
Quadruple filter DAC
SOLDERING INFORMATION Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1314T
Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1994
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