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| HM534251B Series 262144-word x 4-bit Multiport CMOS Video RAM Description The HM534251B is a 1-Mbit multiport video RAM equipped with a 256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM and has write mask function. Features * Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 256-kword x 4-bit SAM: 512-word x 4-bit * Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max * Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min * Low power Active RAM: 413 mW max SAM: 275 mW max Standby 38.5 mW max * High-speed page mode capability * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Real time read transfer cycle capability * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible HM534251B Series Ordering Information Type No. HM534251BJ-6 HM534251BJ-7 HM534251BJ-8 HM534251BJ-10 HM534251BZ-6 HM534251BZ-7 HM534251BZ-8 HM534251BZ-10 Access Time 60 ns 70 ns 80 ns 100 ns 60 ns 70 ns 80 ns 100 ns 400-mil 28-pin plastic ZIP (ZP-28) Package 400-mil 28-pin plastic SOJ (CP-28D) Pin Arrangement HM534251BJ Series SC SI/O0 SI/O1 DT/OE I/O0 I/O1 WE NC RAS A8 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS SI/O3 SI/O2 SE I/O3 I/O2 NC CAS NC A0 A1 A2 A3 A7 I/O2 SE SI/O3 SC SI/O1 I/O0 WE RAS A6 A4 A7 A2 A0 CAS HM534251BZ Series 2 4 6 8 10 12 14 16 18 20 22 24 26 28 1 3 5 7 9 11 13 15 17 19 21 23 25 27 (Bottom View) NC I/O3 SI/O2 VSS SI/O0 DT/OE I/O1 NC A8 A5 VCC A3 A1 NC 2 HM534251B Series Pin Description Pin Name A0 - A8 I/O0 - I/O3 SI/O0 - SI/O3 RAS CAS WE DT/OE SC SE VCC VSS NC Function Address inputs RAM port data inputs/outputs SAM port data inputs/outputs Row address strobe Column address strobe Write enable Data transfer/Output enable Serial clock SAM port enable Power supply Ground No connection 3 HM534251B Series Block Diagram A0 - A8 Column Address Buffer Row Address Buffer Refresh Counter Row Decoder Sense Amplifier & I/O Bus Serial Address Counter SAM Column Decoder Serial Input Buffer Memory Array SAM I/O Bus Data Register Serial Output Buffer Output Buffer Timing Generator RAS CAS DT/OE WE SC SE Input Data Control Mask Register Column Decoder SI/O0 - SI/O3 Input Buffer I/O0 - I/O3 4 HM534251B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals determine the operation cycle of the HM534251B. Table 1. Operation Cycles of the HM534251B Input Level At The Falling Edge Of RAS CAS L H H H H H DT/OE X L L L H H WE X L L H L H SE X L H X X X Operation Mode CBR refresh Write transfer Pseudo transfer Read transfer Read/mask write Read/write Note: X : Don't care. CAS (input pin): Column address is fetched into chip at the falling edge of CAS. CAS controls output impedance of I/O in RAM. A0-A8 (input pins): Row address is determined by A0-A8 level at the falling edge of RAS. Column address is determined by A0-A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WE (input pin): WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM534251B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). I/O0 - I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. 5 HM534251B Series SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. SI/O0-SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a pseudo transfer cycle or write transfer cycle, SI/O inputs data. Operation of HM534251B RAM Read Cycle (DT/OE high and CAS high at the falling edge of RAS) Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in standard DRAM. Then, when WE is high and DT/OE is low while CAS is low, the selected address data outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (t AA ) and RAS to column address delay time (tRAD) specifications are added to enable high-speed page mode. RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high and CAS high at the falling edge of RAS) * Normal Mode Write Cycle (WE high at the falling edge of RAS) When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to distinguish normal mode from mask write mode. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and I/O becomes in high impedance. Data is entered at the CAS falling edge. If WE is set low after the CAS falling edge, this cycle becomes a delalyed write cycle. Data is input at the WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modifywrite cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. * Mask Write Mode (WE low at the falling edge of RAS) If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode cycle which writes only to selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This mask data is effective during the RAS cycle. So, in high-speed page mode cycle, the mask data is retained during the page access. 6 HM534251B Series High-Speed Page Mode Cycle (DT/OE high and CAS high at the falling edge of RAS) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. Note that address access time (tAA), RAS to column address delay time (tRAD ), and access time from CAS precharge (t ACP ) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Transfer Operation The HM534251B provides the read transfer cycle, pseudo transfer cycle and write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle:RAM to SAM Write transfer cycle:SAM to RAM (2) Determine SI/O state Read transfer cycle:SI/O output Pseudo transfer cycle and write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or pseudo transfer cycle after power on, and determined for each transfer cycle. Read Transfer Cycle (CAS high, DT/OE low and WE high at the falling edge of RAS) This cycle becomes read transfer cycle by driving DT/OE low and WE high at the falling edge of RAS. The row address data (512 x 4-bit) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and t SDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 1.). 7 HM534251B Series RAS CAS Address DT/OE L t SDD SC SI/O SAM Data before Transfer Yj Yj + 1 t SDH Xi Yj SAM Data after Transfer Figure 1. Real Time Read Transfer When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. Pseudo Transfer Cycle (CAS high, DT/OE low, WE low and SE high at the falling edge of RAS) Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM. This cycle starts when CAS is high, D T/OE low, W E low and SE high at the falling edge of RAS. Data should be input to SI/O later than t SID (min) after RAS becomes low to avoid data contention. SAM access becomes enabled after t SRD (min) after RAS becomes high. In this cycle, SAM access is inhibited during RAS low, therefore, SC must not be risen. Write Transfer Cycle (CAS high, DT/OE low, WE low and SE low at the falling edge of RAS) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle can be written to other address of RAM by write transfer cycle. However, the address to write data must be the same MSB of row address (AX8) as that of the read transfer cycle. 8 HM534251B Series SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into data register. Internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) R AS -only refresh cycle, (2) CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only R AS cycle with CAS fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits don't operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. 9 HM534251B Series Absolute Maximum Ratings Parameter Terminal voltage *1 *1 Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -0.5 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Power supply voltage Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Relative to VSS . Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage *1 *1 Symbol VCC VIH VIL *1 Min 4.5 2.4 -0.5 *2 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Input high voltage Input low voltage Notes: 1. All voltages referred to V SS . 2. -3.0 V for pulse width 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM534251B -6 Parameter Operating current Symbol Min I CC1 I CC7 -- -- -7 -8 -10 Test Conditions SAM Port Max Min Max Min Max Min Max Unit RAM Port 75 -- 70 -- 60 -- 55 95 mA RAS, CAS cycling SC = VIL, t RC = min SE = VIH mA SE = VIL, SC cycling t SCC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min 125 -- 120 -- 100 -- Standby current I CC2 I CC8 -- 7 -- 7 -- 7 -- 7 mA RAS, CAS = VIH mA -- 50 -- 50 -- 40 -- 40 10 HM534251B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM534251B -6 Parameter RAS -only refresh current Symbol Min I CC3 -- -7 -8 -10 Test Conditions SAM Port SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min SC = VIL, SE = VIH SE = VIL, SC cycling t SCC = min Max Min Max Min Max Min Max Unit RAM Port 75 -- 70 -- 60 -- 55 mA RAS cycling CAS = VIH t RC = min mA I CC9 -- 125 -- 120 -- 100 -- 95 Page mode current I CC4 -- 80 -- 80 -- 70 -- 65 mA CAS cycling RAS = VIL t PC = min I CC10 -- 130 -- 130 -- 110 -- 105 mA CAS -beforeRAS refresh current I CC5 -- 50 -- 45 -- 40 -- 35 mA RAS cycling t RC = min mA I CC11 -- 100 -- 95 -- 80 -- 75 Data transfer current I CC6 I CC12 -- -- 80 -- 75 -- 65 -- 60 mA RAS, CAS cycling SC = VIL, t RC = min SE = VIH SE = VIL, SC cycling t SCC = min 130 -- 125 -- 105 -- 100 mA Input leakage current I LI -10 -10 2.4 -- 10 10 -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 -10 10 -10 10 2.4 -- -- 0.4 A A V V I OH = -2 mA I OL = 4.2 mA Output leakage I LO current Output high voltage Output low voltage VOH VOL Notes: 1. I CC depends on output loading condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. 11 HM534251B Series Capacitance (Ta = 25C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS) Parameter Address Clock I/O, SI/O Symbol CI1 CI2 CI/O Min -- -- -- Typ -- -- -- Max 5 5 7 Unit pF pF pF AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *16 Test Conditions * * * * * Input rise and fall time: 5 ns Input pulse levels : V SS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: See figures +5V +5V I OH = - 2 mA I OL = 4.2 mA I/O I OH = - 2 mA I OL = 4.2 mA SI / O *1 100 pF *1 50 pF Output Load (A) Note: 1. Including scope & jig. Output Load (B) 12 HM534251B Series Common Parameter HM534251B -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time referred to CAS CAS hold time referred to RAS CAS to RAS precharge time Transition time (rise to fall) Refresh period DT to RAS setup time DT to RAS hold time Data-in to CAS delay time Data-in to OE delay time Output buffer turn-off delay referred to CAS Output buffer turn-off delay referred to OE Symbol t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RSH t CSH t CRP tT t REF t DTS t DTH t DZC t DZO t OFF1 t OFF2 Min Max 125 -- 55 60 20 0 10 0 15 20 20 60 10 3 -- 0 10 0 0 -- -- -- -7 Min Max 135 -- 55 -- -8 Min Max 150 -- 60 -- -10 Min Max 180 -- 70 -- Unit Notes ns ns 10000 70 -- -- -- -- -- 40 -- -- -- 50 8 -- -- -- -- 20 20 20 0 10 0 15 20 20 70 10 3 -- 0 10 0 0 -- -- 10000 80 -- -- -- -- -- 50 -- -- -- 50 8 -- -- -- -- 20 20 20 0 10 0 15 20 20 80 10 3 -- 0 10 0 0 -- -- 10000 100 10000 ns -- -- -- -- -- 60 -- -- -- 50 8 -- -- -- -- 20 20 25 0 10 0 15 20 25 -- -- -- -- -- 75 -- ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns 4 4 5 5 3 2 100 -- 10 3 -- 0 10 0 0 -- -- -- 50 8 -- -- -- -- 20 20 13 HM534251B Series Read Cycle (RAM), Page Mode Read Cycle HM534251B -6 Parameter Access time from RAS Access time from CAS Access time from OE Address access time Read command setup time Symbol t RAC t CAC t OAC t AA t RCS Min Max -- -- -- -- 0 0 10 15 35 35 45 10 -- 60 60 20 20 35 -- -- -- 25 -- -- -- -- 40 -7 Min Max -- -- -- -- 0 0 10 15 35 35 45 10 -- 70 20 20 35 -- -- -- 35 -- -- -- -- 40 -8 Min Max -- -- -- -- 0 0 10 15 40 40 50 10 -- 80 20 20 40 -- -- -- 40 -- -- -- -- 45 -10 Min Max -- -- -- -- 0 0 10 15 45 45 55 10 -- 100 25 25 45 -- -- -- 55 -- -- -- -- 50 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 2 6, 7 7, 8 7 7, 9 Read command hold time t RCH Read command hold time t RRH referred to RAS RAS to column address delay time Column address to RAS lead time Column address to CAS lead time Page mode cycle time CAS precharge time Access time from CAS precharge Page mode RAS pulse width t RAD t RAL t CAL t PC t CP t ACP t RASP 100000 70 100000 80 100000 100 100000 ns 14 HM534251B Series Write Cycle (RAM), Page Mode Write Cycle HM534251B -6 Parameter Write command setup time Symbol t WCS Min Max 0 15 15 20 20 0 15 0 10 0 10 20 45 10 20 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -7 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 45 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 50 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 Min Max 0 15 15 20 20 0 15 0 10 0 10 20 55 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 12 12 11 Write command hold time t WCH Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time WE to RAS setup time WE to RAS hold time Mask data to RAS setup time Mask data to RAS hold time OE hold time referred to WE Page mode cycle time CAS precharge time Page mode RAS pulse width t WP t RWL t CWL t DS t DH t WS t WH t MS t MH t OEH t PC t CP CAS to data-in delay time t CDD t RASP 100000 70 100000 80 100000 100 100000 ns 15 HM534251B Series Read-Modify-Write Cycle HM534251B -6 Parameter Read-modify-write cycle time RAS pulse width (read-modify-write cycle) CAS to WE delay time Column address to WE delay time OE to data-in delay time Access time from RAS Access time form CAS Access time from OE Address access time RAS to column address delay time Read command setup time Write command to RAS lead time Write command to CAS lead time Write command pulse width Data-in setup time Data-in hold time OE hold time referred to WE Symbol t RWC t RWS t CWD t AWD t ODD t RAC t CAC t OAC t AA t RAD t RCS t RWL t CWL t WP t DS t DH t OEH Min Max 175 -- 110 10000 45 60 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 60 20 20 35 25 -- -- -- -- -- -- -- -7 Min Max 185 -- 120 10000 45 60 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 70 20 20 35 35 -- -- -- -- -- -- -- -8 Min Max 200 -- 130 10000 45 65 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 80 20 20 40 40 -- -- -- -- -- -- -- -10 Min Max 230 -- 150 10000 50 70 20 -- -- -- -- 15 0 20 20 15 0 15 20 -- -- -- 100 25 25 45 55 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 14 14 12 6, 7 7, 8 7 7, 9 16 HM534251B Series Refresh Cycle HM534251B -6 Parameter Symbol Min 10 10 10 Max -- -- -- -7 Min 10 10 10 Max -- -- -- -8 Min 10 10 10 Max -- -- -- -10 Min 10 10 10 Max -- -- -- Unit ns ns ns Notes CAS setup time t CSR (CAS-before-RAS refresh) CAS hold time t CHR (CAS-before-RAS refresh) RAS precharge to CAS hold time t RPC 17 HM534251B Series Read Transfer Cycle HM534251B -6 Parameter DT hold time referred to RAS DT hold time referred to CAS DT hold time referred to column address DT precharge time DT to RAS delay time SC to RAS setup time 1st SC to RAS hold time 1st SC to CAS hold time 1st SC to column address hold time Last SC to DT delay time 1st SC to DT hold time Serial data-in to 1st SC delay time Serial clock cycle time SC pulse width SC precharge time SC access time Serial data-out hold time Serial data-in setup time Serial data-in hold time RAS to column address delay time Column address to RAS lead time DT high hold time from RAS precharge Symbol Min t RDH t CDH t ADH t DTP t DRD t SRS t SRH t SCH t SAH t SDD t SDH t SZS t SCC t SC t SCP t SCA t SOH t SIS t SIH t RAD t RAL t DTHH 50 20 25 20 65 25 60 25 40 5 10 0 25 5 10 -- 5 0 15 15 35 10 Max -7 Min Max -8 Min Max -10 Min Max Unit Notes 10000 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20 -- -- -- 25 -- -- 20 25 20 65 25 70 25 40 5 10 0 25 5 10 -- 5 0 15 15 35 10 10000 65 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 22 -- -- -- 35 -- -- 20 30 20 70 30 80 25 45 5 15 0 30 10 10 -- 5 0 15 15 40 10 10000 80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 -- -- -- 40 -- -- 25 30 30 80 30 100 25 50 5 15 0 30 10 10 -- 5 0 15 15 45 10 10000 ns -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 -- -- -- 55 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 18 HM534251B Series Pseudo Transfer Cycle, Write Transfer Cycle HM534251B -6 Parameter SE setup time referred to RAS SE hold time referred to RAS SC setup time referred to RAS RAS to SC delay time Symbol Min t ES t EH t SRS t SRD 0 10 25 20 10 40 25 5 10 -- -- 5 5 0 15 Max -- -- -- -- 40 -- -- -- -- 20 20 -- -- -- -- -7 Min 0 10 25 20 10 40 25 5 10 -- -- 5 5 0 15 Max -- -- -- -- 40 -- -- -- -- 22 22 -- -- -- -- -8 Min 0 10 30 25 10 45 30 10 10 -- -- 5 5 0 15 Max -- -- -- -- 45 -- -- -- -- 25 25 -- -- -- -- -10 Min 0 10 30 25 10 50 30 10 10 -- -- 5 5 0 15 Max -- -- -- -- 50 -- -- -- -- 25 25 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 15 Notes Serial output buffer turn-off t SRZ time referenced to RAS RAS to serial data-in delay t SID time Serial clock cycle time SC pulse width SC precharge time SC access time SE access time Serial data-out hold time Serial write enable setup time Serial data-in setup time Serial data-in hold time t SCC t SC t SCP t SCA t SEA t SOH t SWS t SIS t SIH 19 HM534251B Series Serial Read Cycle, Serial Write Cycle HM534251B -6 Parameter Serial clock cycle time SC pulse width SC precharge width Access time from SC Access time from SE Serial data-out hold time Symbol Min t SCC t SC t SCP t SCA t SEA t SOH 25 5 10 -- -- 5 -- 0 15 5 15 5 15 Max -- -- -- 20 20 -- 20 -- -- -- -- -- -- -7 Min 25 5 10 -- -- 5 -- 0 15 5 15 5 15 Max -- -- -- 22 22 -- 20 -- -- -- -- -- -- -8 Min 30 10 10 -- -- 5 -- 0 15 5 15 5 15 Max -- -- -- 25 25 -- 20 -- -- -- -- -- -- -10 Min 30 10 10 -- -- 5 -- 0 15 5 15 5 15 Max -- -- -- 25 25 -- 20 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 5 15 15 Notes Serial output buffer turn-off t SEZ time referred to SE Serial data-in setup time Serial data-in hold time Serial write enable setup time Serial write enable hold time Serial write disable setup time Serial write disable hold time t SIS t SIH t SWS t SWH t SWIS t SWIH Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > tRCD (max) or tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. t OFF1 (max), tOFF2 (max) and tSEZ (max) are defined as the time at which the output acheives the open circuit condition (V OH -100 mV, VOL +100 mV). 6. Assume that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tCAC . 9. When t RCD tRCD (max) and tRAD tRAD (max), access time is specified by tAA . 10. If either tRCH of tRRH is satisfied, operation is guaranteed. 11. When t WCS tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WE. 13. Either t CDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. 20 HM534251B Series 14. When t AWD tAWD (min) and tCWD tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. t ODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 16. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. XXX: H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout Timing Waveforms *17 Read Cycle t RC t RAS RAS t CSH t RCD CAS t ASR Address Row t RSH t CAS t RAL t ASC Column t RCS t CAC t AA t RAC t DZC t DZO t DTS DT/OE t DTH t OAC t OFF1 Valid Dout t OFF2 t CAH t RRH t CAL t CRP t RP t RAD t RAH t RCH t CDD WE I/O (Output) I/O (Input) 21 HM534251B Series Early Write Cycle t RC t RAS RAS t CSH t RCD CAS Address t ASR t RAH t RSH t CAS t CAH t RP t CRP t ASC Row t WS t WH *1 Column t WCS t WCH WE I/O (Output) I/O (Input) DT/OE High-Z t MS t MH t DS t DH Mask Data t DTS t DTH Valid Din Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Delayed Write Cycle t RC t RAS RAS t RCD CAS Address t ASR t RAH Row t WS WE I/O (Output) I/O (Input) *1 t WH t ASC Columun t RWL t WP t CWL t CSH t RSH t CAS t CAH t RP t CRP t MS t MH t DZC t OFF2 t ODD t DS t DH Mask Data t DTH t DTS Valid Din t OEH DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 22 HM534251B Series Read-Modify-Write Cycle t RWC t RWS RAS t RCD CAS t RAD t ASR Address t WS WE I/O (Output) I/O (Input) DT/OE *1 t RAH t ASC t CAH t AWD t CWD t CAC t AA t RAC Valid Dout t MS t MH t DZC t DZO t OAC t OFF2 t ODD Mask Data t DTS t DTH t DS t DH t RWL t CWL t WP t CRP t RP Row t WH Columun tRCS Valid Din t OEH Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Read Cycle t RC t RASP RAS t CSH t RCD t CAS t RAD t ASR Address t RAH t ASC Row t CAL t CAH t PC t CP t CAS t CAL t CAH t RAL t ASC t RCS t OFF1 Valid Dout t RP t RSH t CAS t CAL t CAH Columun t RRH t RCH t AA t ACP t CAC Valid Dout t CP t CRP CAS t ASC Columun t RCS Columun t RCH t RCS t AA t ACP t CAC t DZC t OAC t RCH WE t RAC t OFF1 t AA t CAC t DZC t CDD t OAC t OFF2 Valid Dout t OFF1 I/O (Output) t CDD t OFF2 t DZC t OAC t CDD I/O (Input) t DTS DT/OE t DZO t DTH 23 HM534251B Series Page Mode Write Cycle (Early Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC t CAS t CP t PC t CAS t CP t RSH t CAS t CAH Column t WCS t WCH t CRP t RP t CAH t ASC Column t CAH t ASC Row Column t WS t WH t WCS t WCH *1 t WCS t WCH WE I/O (Output) I/O (Input) t DTS DT/OE t MS High-Z t MH t DS t DH t DS t DH Valid Din t DS t DH Valid Din Mask Data Valid Din t DTH Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Page Mode Write Cycle (Delayed Write) t RC t RASP RAS t CSH t RCD CAS Address t ASR t RAH t ASC Row t WS WE I/O (Output) I/O (Input) t DTS DT/OE t MS *1 t MH Mask Data t RP t PC t CAS t CAH t CWL t WP t CP t ASC Column t CWL t WP t CAS t CAH t CP t RSH t CAS t CAH t RWL t WP t CRP t ASC Column Column t WH t CWL t DS t DH t DS t DH t DS t DH Valid Din Valid Din Valid Din t OEH Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 24 HM534251B Series RAS-Only Refresh Cycle t RC t RAS RAS CAS Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS DT/OE t DTH t CRP t ASR t RAH t RPC t RP Row CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC t CP t RAS t RPC t CSR t CHR Inhibit Falling Transition CAS Address t RP t CSR WE I/O (Output) DT/OE t OFF1 High-Z 25 HM534251B Series Hidden Refresh Cycle t RC t RAS RAS t RCD CAS t ASR Address Row t RCS WE t CAC t AA t RAC I/O (Output) I/O (Input) t DTS DT/OE Valid Dout t DZC t DZO t DTH t OAC t OFF2 t OFF1 t RSH t CHR t CRP t RP t RAS t RC t RP t RAD t RAL t RAH t ASC t CAH Column t RRH Read Transfer Cycle (1) tRC t RAS RAS t CSH t RCD CAS t ASR Address Row t WS WE I/O (Output) t DTS DT/OE t SCC SC t SCC t SDD t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCC t SDH t SC t SCA t SOH Valid Sout Previous Row t SCC t SCP High-Z t CDH t ADH t RDH t DTP t DRD t DTHH t WH t RAD t RAH t RAL t ASC t CAH SAM Start Address t RP t CRP t RSH t CAS t SOH Valid Sout New Row SI/O (Output) SI/O (Input) 26 HM534251B Series Read Transfer Cycle (2) t RC t RAS RAS t CSH t RCD CAS t ASR Address t WS WE I/O (Output) DT/OE t SRS t SC SC Inhibit Rising Transition t SRH SI/O (Output) SI/O (Input) t SIS t SIH t SZS t SCA t SOH Valid Sout t SCH t SAH t SDH t SCP t SC High-Z t DTS t DTH t DTHH t DRD t DTP t RAD t RAH t ASC t CAH t RSH t CAS t RAL Sam Start Address t RP t CRP Row t WH t SCC t SCP t SCA Valid Sin 27 HM534251B Series Pseudo Transfer Cycle t RC t RAS t RP RAS t CSH t RCD t RSH t CAS t ASR t RAH t ASC t CAH t CRP CAS Address t WS Row t WH SAM Start Address WE I/O (Output) DT/OE t ES t SEZ t EH t SWS High - Z t DTS t DTH SE t SRS t SC t SRD t SCP t SCC t SC t SCP SC Inhibit Rising Transition t SCA t SOH t SRZ SI/O (Output) SI/O (Input) Valid Sout Valid Sout t SID t SIS t SIH t SIS t SIH Valid Sin Valid Sin 28 HM534251B Series Write Transfer Cycle t RC t RAS t RP RAS t RCD t CSH t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address t WS Row t WH SAM Start Address WE I/O (Output) DT/OE High-Z t DTS t DTH t ES t EH t SWS SE t SRS t SWS t SC t SRD t SCP t SC t SCC t SCP SC Inhibit Rising Transition SI/O (Output) SI/O (Input) t SIS t SIH t SIS t SIH t SIS t SIH Valid Sin Valid Sin Valid Sin 29 HM534251B Series Serial Read Cycle SE tSCC SC tSC tSCA tSOH Valid Sout tSCP tSC tSCC tSCP tSC tSEA tSCA tSCP tSCC tSC tSEZ Valid Sout tSCA tSOH Valid Sout Valid Sout SI/O (Output) Serial Write Cycle tSWH SE tSCC tSC SC tSIS SI/O (Input) tSIH tSCP tSCC tSC tSCP tSIS tSIH tSCC tSC tSCP tSIS tSIH tSC tSWIS tSWIH tSWS Valid Sin Valid Sin Valid Sin 30 HM534251B Series Package Dimensions HM534251BJ Series (CP-28D) 18.17 18.54 Max 28 15 10.16 0.13 11.18 0.13 Unit: mm 1 0.74 14 3.50 0.26 0.21 2.40 + 0.24 - 1.30 Max 0.43 0.10 1.27 0.10 0.80 +0.25 -0.17 9.40 0.25 31 HM534251B Series HM534251BZ Series (ZP-28) Unit: mm 35.58 36.57 Max 10.16 Max 8.71 1 0.50 - 0.12 + 0.08 28 1.27 0.3 M 1.045 Max 2.85 2.80 Min 0.10 0.25 + 0.05 - 2.54 32 |
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