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Analog-Digital-Converter for Picture in Picture
SDA 9187-2X
Preliminary Data
MOS IC
Features
q q q q q q q q
3 separate A/D-converters Resolution: 6 bit Sampling rate: 13.5 MHz, 3.375 MHz Clamping circuit for the input signals Adjustable delay for the luminance signal (8 steps) Color difference signals Y and V can be inverted Internal clock synchronization by sandcastle signal System clock generation for picture insertion processor
P-DSO-28-1
Type SDA 9187-2X
Ordering Code Q67100-H5141
Package P-DSO-28-1 (300 mil)
The 9187-2X converts the analog output signals Y, U, V of any color decorder into the digital input signals of the PIP PLUS Processor SDA 9188-3X. A clock generator which is synchronized to the sync signals of the insert channel is integrated on this chip. At the input for the channel of the inset picture an analog CVBS signal is required. An analog operating chroma decoder as well as a sync processor are generating the analog luminance- and chrominance signals Y, U, V and the horizontal and vertical sync signals of the inset picture. Y, U and V are digitized by 6-bit flash converters and output in a format that matches the interface of the PIP-processor SDA 9188-3X. Furthermore, with the aid of PLL, the SDA 9187-2X generates the line locked clock LL3 (nominal 13.5 MHz) and the blanking signal BLN.
Semiconductore Group
5
08.93
SDA 9187-2X
The luminance signal Y and the chrominance signals U, V are fed to the SDA 9187-2X by means of coupling capacitors. The color subcarrier must be filtered out of Y. The sampling rate of the three 6-bit A/D-flash converters is the LL3 clock. The dynamic range of the converter is the range between VREFH and VREFL. The black level of Y is clamped to VREFL. The luminance information is generated as a 6-bit binary offset code. The digitized luminance signal Y can be delayed to compensate the different signal propagation times of the preceding decoder. This delay can be set in increments of two LL3 cycles in a range of 0 through 15 LL3 cycles (nominally 0 to 1.11) on pins YD0, YD1 and YD2. The white level of U and V is clamped to 0.5 x (VREFH + VREFL). U, V are then converted into a 6-bit two's complement code. The digitized U-, V-signals can be inverted via the CNEG-control input. A multiplexer selects every fourth U-, V-sample and applies this 10-bit information in four clock cycles in a nibble format to pins UV (0:3). The horizontal PLL, consisting of a horizontal timer, phase comparator and VCO, generates the line-locked picture-in-picture system clock LL3 and the internal chip timing. The horizontal timer divides the LL3-clock by 864 (the same for PAL and NTSC) and applies this signal as a horizontal reference signal to the phase comparator. The external horizontal signal is decoded from the sandcastle signal and matched in its pulse width (= 345 LL3-cycles) to the reference signal. The digital phase comparator is frequency- and phase-sensitive and produces current pulses at its output. The up/down pulses of the phase comparator are filtered on pin RC. The filtered signal is the control voltage of the VCO. The horizontal timer also determines the start time and the width of the clamping pulse as well as the location of the blanking signal BLN, which in turn defines the horizontal duration of the picture information on the Y output and should be synchronous with it. BLN is consequently delayed to the same degree as Y.
Clamping An internal clamping circuit is provided in each of the three analog channels. The external clamping capacitance is loaded by on chip current sources during clamping (typ. 100 A). So the loading time depends on the values of the ext. clamping capacitor.
Semiconductor Group
6
SDA 9187-2X
Pin Configuration (top view)
Semiconductor Group
7
SDA 9187-2X
Pin Definitions and Function Pin No. 1 2-7 8-11 12 13 14 Symbol BLN YQ (5:0) UV (3:0) LL3 Function Blanking signal output Digital Y-output signal (Index 0 = LSB) Digital chrominance signal (nibble format) Output of the line locked system clock (nom. 13.5 MHz) Digital ground Color negated. By H-level the chrominance signals are multiplied by - 1 and are output. No wiring = H-level. Input for the sandcastle synchronous signal of the gate signal
VSS
CNEG
15 16 17 18 19 20 21 22 23 1) 24 25, 26, 27 28 1)
1)
ISC
VSSO
RC
VSS connection for the oscillator
Pin to the analog loop filter connection of the PLL Analog ground Analog input for the Y-signal Low reference voltage for the A/D-converter Analog input for the U-signal High reference voltage for the A/D-converter Analog input for the Y-signal Analog 5 V supply voltage To adjust the Y-delay no connection = L-level Digital 5 V supply voltage
VSSA
VIN
VREFL
UIN
VREFH
YIN
VDDA
YD0, YD1, YD2
VDD
VDD must be applied before VDDA VDD must not exceed VDDA
Semiconductor Group
8
SDA 9187-2X
Block Diagram
Semiconductor Group
9
SDA 9187-2X
Absolute Maximum Ratings Note: Maximum ratings cannot be exceeded without causing irreversible damage to the integrated circuit. Ambient temperatur TA = 25 C (all voltages refer to VSS) Parameter Supply voltage Voltages at I/O pins Voltages differences between VREF H and VREF L Ambient temperature Storage temperature Power dissipation Operating Range Note: Within the functional range, the integrated circuit operates as described; deviations from the characteristics data are possible (all voltages refer to VSS) Supply voltages Ambient temperature Reference voltage 1) Reference voltage difference
1)
Symbol min.
Limit Values max. 6,5 6,5 6,5 4 70 125 0.8 - 0.3 - 0.3 - 0.3 -4 - 20 - 20
Unit V V V V C C W
VDD VDD A VIN
VREF
TA Tstg Ptot
VDD VDD A TA VREF H VREF L
4.5 4.5 0 1.5 0.5
5.5 5.5 70 2.5 1.5 2
V V C V V V
VREF H - VREF L 0.5
if the standard configuration is not used, additional external components are necessary (please refer to page 11, reference circuitry)
Semiconductor Group
10
SDA 9187-2X
Characteristics Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not stated otherwise, typical characteristics will apply at TA = 25 C and the listed supply voltage. (all voltages refer to VSS) Parameter Supply voltages Current consumption Supply voltage differential Digital Outputs YQ (0:5), UV (0:3), BLN, LL3 Load capacitance Low level High level Delay to the positive transition of LL3 LL3 Pulse Form Rise time Fall time H-pulse width L-pulse width LL3 period duration Digital Inputs CNEG Low level High level Input current Symbol min. Limit Values typ. 5 5 40 20 max. 5.5 5.5 80 40 0.5 V V mA V 4.5 4.5 Unit Test Condition
VDD VDDA IDD IDDA
1)
VDDA- VDD 0
CL VQL VQH td
0 0 2.4 6 15
20 0.4
pF V V ns
VDD
25
IQL = 1.6 mA IQH = - 0.2 mA
LL3 = VQL
tLL3R tLL3F tLL3H tLL3L TLL3
0 0 28 28 < 68
7 5
74
< 80.6
ns ns ns ns ns
TLL3 = 68 ns TLL3 = 68 ns
VCNL VCNH ICN
0.8 2.0 30
V V A
internal pull up for CNEG pin
VCNH = 5 V
1)
VDD VDD
must not be applied before VDDA must not exceed VDDA
Semiconductor Group
11
SDA 9187-2X
Characteristics (cont'd) Parameter YD (0, 1, 2) Low level Mid level High level Input current Sandcastle Input ISC Switching threshold for VHSC high level Low level Input current 0.6 VDD 0.6 VDD - 0.3 V 0.34 VDD 0.34 VDD - 0.5 V2) - 1 A 0.6 VDD + 0.3 V 0.34 VDD + 0.5 V2) 1 A Symbol min. Limit Values typ. max. 0.8 V 0.55 VDD V V 30 A internal pull down for YD0, YD1, YD2 pins Unit Test Condition
VYDL VYDM VYDH IYD
2.0 4.0
VYDH = 5 V
ISC
VSCH = 5 V VSCL = 0 V
VCO Frequency range < 12.7 < 12.7 13.5 > 14.3 MHz MHz
VRC = 1.0 V VDD = 4.5 V TA = 0 C VRC = 4.3 V VDD = 5.5 V TA = 70 C
> 14.3
MHz
PLL Loop Filter 1) (recommended value)
R1 C1 C2
1) 2)
56 56 1
k nF nF
see application circuit
Design of the loop filter network of the PLL see page 14 Value has been increased from 0.3 V to 0.5 V compared to the SDA 9187X!
Semiconductor Group
12
SDA 9187-2X
Characteristics (cont'd) Parameter Input capacitance Leakage current at YIN, UIN, VIN Start of the clamping pulse refer to the transmission of the horizontal ISC-pulse Clamping pulse duration (3 pulses) Coupling capacitor for YIN, UIN, VIN Clamping current Symbol min. Limit Values typ. 5 1 0.5 1) 0.2 2) 0.3 3) 10 100 60 max. pF A s U/V channel s Y channel s /pulse nF A clamp level deviation > 2 LSB A clamp level deviation > 1 LSB < 2 LSB A clamp level deviation < 1LSB Unit
C IN C
tCPD CU, CV, CY Iclamp 1 Iclamp 2
Iclamp 3
30
Dynamic Range of the Converter Y-converter U-converter V-converter
1) (= 7 LL3 period) 2) (= 3 LL3 period) 3) (= 4LL3 period)
0 - 31 - 31
63 31 31
Semiconductor Group
13
SDA 9187-2X
Characteristics (cont'd) Parameter Symbol min. DC-Transfer Function of the A/D-converter Integral non-linearity1) Differential non-linearity Reference Voltage VREFH, VREFL
1)
Limit Values typ. max.
Unit Test Condition
- 1 LSB - 0,5 LSB
1 LSB 0.5 LSB
VREFH = 2.0 V VREFL = 1.0 V
VREFH VREFL
1.5 0.5
2.0 1.0
2.5 1.5
V V
1) The absolute tolerance of the coupling level and the converter characteristic line are not influenced by the
difference VREFH - VREFL (dynamic range of the converter). This increases the relative errors when VREFH - VREFL < 1 V.
Semiconductor Group
14
SDA 9187-2X
Reference Circuitry For the standard input signal (Y, U, V = 1 Vpp) the reference voltage is generated internally (figure 1). For all the other cases with input signals bigger or smaller than 1 Vpp the adjustment of the reference range can be done via an external resistor circuit (figure 2, 3).
Figure 1
Figure 2
Figure 3
the absolute tolerance of internal resistors is 20 % the relative tolerance of internal resistors is 2 %
Semiconductor Group
15
SDA 9187-2X
Clamping For each analog channel there is an internal clamping circuit. Analog inputs YIN, UIN and VIN are pulled to internally generated clamping levels. The clamping signals necessary for this are also generated internally (see Fig. 7). Clamping levels: Analog signal YIN UIN, VIN Binary Code 000000 100000
The external clamping capacitor is charged to the appropriate clamping level every line for 42 CLK cycles by internal current sources.
Semiconductor Group
16
SDA 9187-2X
Application Circuit
Semiconductor Group
17
SDA 9187-2X
Design of the Loop Filter Network For the calculation of the control response the following formulas can be applied. Characteristic circuit frequency: loop bandwidth damping factor K = 0.52 typical K = 0.75 maximum The parallel capacitance C2 should not exceed 5 % of C1. Because of the discrete detection of the phase differences every 64 s, phase modulation of half the line frequency is superimposed on the transient response of the PLL. To make sure that this phase modulation is damped sufficiently. 1.74 > R1 x 47 x 10 - 6 x 1/ x (1 - 2 / (1 + e)) with or approx. by 0 = (K/C1) 0.5 = 0.5 x R x (K x C1) 0.5
a = 64 s. / (R1 x C2) R1 x C2 << 64 s 1.74 > R1 x 47 x 10 - 6 x 1/
For the board layout it is important to a) block supply lines near the supply pins, b) keep the wiring of C2 short.
Semiconductor Group
18
SDA 9187-2X
Pulse Diagram Input Voltage Range of Y, U, and V and their Translation in Initial Values ("Digital Values")
Semiconductor Group
19
SDA 9187-2X
Clamping Pulse Timing
Semiconductor Group
20
SDA 9187-2X
Signal Delay Time for U, V and Y (used indication: number of scanning values). Additionally programmable delay time in DELAY-Block-0.
Semiconductor Group
21
SDA 9187-2X
Relation between SC, BLN and Y and UV (used indication: number of pixels) - Y, U, V have no delay time differences. - Delay between SC and Y, U, V is smaller than provided for the optimal case.
Semiconductor Group
22
SDA 9187-2X
Relation between SC, BLN and Y and UV (used indication: number of pixels) Semiconductor Group 23
SDA 9187-2X
Relation between SC and BLN
Semiconductor Group
24
SDA 9187-2X
Conversion of U and V in a Nibble Form with 13.5 MHz, 4 Bit It means: 1. index: number of scanning value (pixels) 2. index. number of bits; 5 = MSB
Semiconductor Group
25
SDA 9187-2X
Specification of Edges
Sandcastle Pulse Adjusting of Y-Delay via YD0, YD1, YD2 Level Range Pin YD2 0 0 0 0 1 1 1 1 Pin YD1 0 0 1 1 0 0 1 1 Pin YD0 0 1 0 1 0 1 0 1 Additional Delay for Y and BLN LL3 clocks 0 2 4 6 8 10 12 14 typ. value 0 148 ns 296 ns 444 ns 592 ns 740 ns 888 ns 1.04 s
No connection of YD0, YD1, YD2 = L-level! Level range: 0 = VYDL 1 = VYDH
Semiconductor Group
26
SDA 9187-2X
Function of SC-Pulse Extention and Phase Comparison (PLL is unlocked, behind the external H-phase)
Semiconductor Group
27

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